1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 
19 #include "htc.h"
20 
21 MODULE_AUTHOR("Atheros Communications");
22 MODULE_LICENSE("Dual BSD/GPL");
23 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
24 
25 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
26 module_param_named(debug, ath9k_debug, uint, 0);
27 MODULE_PARM_DESC(debug, "Debugging mask");
28 
29 int htc_modparam_nohwcrypt;
30 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 
33 static int ath9k_htc_btcoex_enable;
34 module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
35 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
36 
37 static int ath9k_ps_enable;
38 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
39 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
40 
41 int htc_use_dev_fw = 0;
42 module_param_named(use_dev_fw, htc_use_dev_fw, int, 0444);
43 MODULE_PARM_DESC(use_dev_fw, "Use development FW version");
44 
45 #ifdef CONFIG_MAC80211_LEDS
46 int ath9k_htc_led_blink = 1;
47 module_param_named(blink, ath9k_htc_led_blink, int, 0444);
48 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
49 
50 static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
51 	{ .throughput = 0 * 1024, .blink_time = 334 },
52 	{ .throughput = 1 * 1024, .blink_time = 260 },
53 	{ .throughput = 5 * 1024, .blink_time = 220 },
54 	{ .throughput = 10 * 1024, .blink_time = 190 },
55 	{ .throughput = 20 * 1024, .blink_time = 170 },
56 	{ .throughput = 50 * 1024, .blink_time = 150 },
57 	{ .throughput = 70 * 1024, .blink_time = 130 },
58 	{ .throughput = 100 * 1024, .blink_time = 110 },
59 	{ .throughput = 200 * 1024, .blink_time = 80 },
60 	{ .throughput = 300 * 1024, .blink_time = 50 },
61 };
62 #endif
63 
64 static void ath9k_htc_op_ps_wakeup(struct ath_common *common)
65 {
66 	ath9k_htc_ps_wakeup((struct ath9k_htc_priv *) common->priv);
67 }
68 
69 static void ath9k_htc_op_ps_restore(struct ath_common *common)
70 {
71 	ath9k_htc_ps_restore((struct ath9k_htc_priv *) common->priv);
72 }
73 
74 static const struct ath_ps_ops ath9k_htc_ps_ops = {
75 	.wakeup = ath9k_htc_op_ps_wakeup,
76 	.restore = ath9k_htc_op_ps_restore,
77 };
78 
79 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
80 {
81 	unsigned long time_left;
82 
83 	if (atomic_read(&priv->htc->tgt_ready) > 0) {
84 		atomic_dec(&priv->htc->tgt_ready);
85 		return 0;
86 	}
87 
88 	/* Firmware can take up to 50ms to get ready, to be safe use 1 second */
89 	time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
90 	if (!time_left) {
91 		dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
92 		return -ETIMEDOUT;
93 	}
94 
95 	atomic_dec(&priv->htc->tgt_ready);
96 
97 	return 0;
98 }
99 
100 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
101 {
102 	ath9k_hw_deinit(priv->ah);
103 	kfree(priv->ah);
104 	priv->ah = NULL;
105 }
106 
107 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
108 {
109 	struct ieee80211_hw *hw = priv->hw;
110 
111 	wiphy_rfkill_stop_polling(hw->wiphy);
112 	ath9k_deinit_leds(priv);
113 	ath9k_htc_deinit_debug(priv);
114 	ieee80211_unregister_hw(hw);
115 	ath9k_rx_cleanup(priv);
116 	ath9k_tx_cleanup(priv);
117 	ath9k_deinit_priv(priv);
118 }
119 
120 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
121 					u16 service_id,
122 					void (*tx) (void *,
123 						    struct sk_buff *,
124 						    enum htc_endpoint_id,
125 						    bool txok),
126 					enum htc_endpoint_id *ep_id)
127 {
128 	struct htc_service_connreq req;
129 
130 	memset(&req, 0, sizeof(struct htc_service_connreq));
131 
132 	req.service_id = service_id;
133 	req.ep_callbacks.priv = priv;
134 	req.ep_callbacks.rx = ath9k_htc_rxep;
135 	req.ep_callbacks.tx = tx;
136 
137 	return htc_connect_service(priv->htc, &req, ep_id);
138 }
139 
140 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
141 				   u32 drv_info)
142 {
143 	int ret;
144 
145 	/* WMI CMD*/
146 	ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
147 	if (ret)
148 		goto err;
149 
150 	/* Beacon */
151 	ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
152 				    &priv->beacon_ep);
153 	if (ret)
154 		goto err;
155 
156 	/* CAB */
157 	ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
158 				    &priv->cab_ep);
159 	if (ret)
160 		goto err;
161 
162 
163 	/* UAPSD */
164 	ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
165 				    &priv->uapsd_ep);
166 	if (ret)
167 		goto err;
168 
169 	/* MGMT */
170 	ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
171 				    &priv->mgmt_ep);
172 	if (ret)
173 		goto err;
174 
175 	/* DATA BE */
176 	ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
177 				    &priv->data_be_ep);
178 	if (ret)
179 		goto err;
180 
181 	/* DATA BK */
182 	ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
183 				    &priv->data_bk_ep);
184 	if (ret)
185 		goto err;
186 
187 	/* DATA VI */
188 	ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
189 				    &priv->data_vi_ep);
190 	if (ret)
191 		goto err;
192 
193 	/* DATA VO */
194 	ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
195 				    &priv->data_vo_ep);
196 	if (ret)
197 		goto err;
198 
199 	/*
200 	 * Setup required credits before initializing HTC.
201 	 * This is a bit hacky, but, since queuing is done in
202 	 * the HIF layer, shouldn't matter much.
203 	 */
204 
205 	if (IS_AR7010_DEVICE(drv_info))
206 		priv->htc->credits = 45;
207 	else
208 		priv->htc->credits = 33;
209 
210 	ret = htc_init(priv->htc);
211 	if (ret)
212 		goto err;
213 
214 	dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
215 		 priv->htc->credits);
216 
217 	return 0;
218 
219 err:
220 	dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
221 	return ret;
222 }
223 
224 static void ath9k_reg_notifier(struct wiphy *wiphy,
225 			       struct regulatory_request *request)
226 {
227 	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
228 	struct ath9k_htc_priv *priv = hw->priv;
229 
230 	ath_reg_notifier_apply(wiphy, request,
231 			       ath9k_hw_regulatory(priv->ah));
232 }
233 
234 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
235 {
236 	struct ath_hw *ah = hw_priv;
237 	struct ath_common *common = ath9k_hw_common(ah);
238 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
239 	__be32 val, reg = cpu_to_be32(reg_offset);
240 	int r;
241 
242 	r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
243 			  (u8 *) &reg, sizeof(reg),
244 			  (u8 *) &val, sizeof(val),
245 			  100);
246 	if (unlikely(r)) {
247 		ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
248 			reg_offset, r);
249 		return -EIO;
250 	}
251 
252 	return be32_to_cpu(val);
253 }
254 
255 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
256 				u32 *val, u16 count)
257 {
258 	struct ath_hw *ah = hw_priv;
259 	struct ath_common *common = ath9k_hw_common(ah);
260 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
261 	__be32 tmpaddr[8];
262 	__be32 tmpval[8];
263 	int i, ret;
264 
265 	for (i = 0; i < count; i++) {
266 		tmpaddr[i] = cpu_to_be32(addr[i]);
267 	}
268 
269 	ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
270 			   (u8 *)tmpaddr , sizeof(u32) * count,
271 			   (u8 *)tmpval, sizeof(u32) * count,
272 			   100);
273 	if (unlikely(ret)) {
274 		ath_dbg(common, WMI,
275 			"Multiple REGISTER READ FAILED (count: %d)\n", count);
276 	}
277 
278 	for (i = 0; i < count; i++) {
279 		val[i] = be32_to_cpu(tmpval[i]);
280 	}
281 }
282 
283 static void ath9k_regwrite_multi(struct ath_common *common)
284 {
285 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
286 	u32 rsp_status;
287 	int r;
288 
289 	r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
290 			  (u8 *) &priv->wmi->multi_write,
291 			  sizeof(struct register_write) * priv->wmi->multi_write_idx,
292 			  (u8 *) &rsp_status, sizeof(rsp_status),
293 			  100);
294 	if (unlikely(r)) {
295 		ath_dbg(common, WMI,
296 			"REGISTER WRITE FAILED, multi len: %d\n",
297 			priv->wmi->multi_write_idx);
298 	}
299 	priv->wmi->multi_write_idx = 0;
300 }
301 
302 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
303 {
304 	struct ath_hw *ah = hw_priv;
305 	struct ath_common *common = ath9k_hw_common(ah);
306 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
307 	const __be32 buf[2] = {
308 		cpu_to_be32(reg_offset),
309 		cpu_to_be32(val),
310 	};
311 	int r;
312 
313 	r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
314 			  (u8 *) &buf, sizeof(buf),
315 			  (u8 *) &val, sizeof(val),
316 			  100);
317 	if (unlikely(r)) {
318 		ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
319 			reg_offset, r);
320 	}
321 }
322 
323 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
324 {
325 	struct ath_hw *ah = hw_priv;
326 	struct ath_common *common = ath9k_hw_common(ah);
327 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
328 
329 	mutex_lock(&priv->wmi->multi_write_mutex);
330 
331 	/* Store the register/value */
332 	priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
333 		cpu_to_be32(reg_offset);
334 	priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
335 		cpu_to_be32(val);
336 
337 	priv->wmi->multi_write_idx++;
338 
339 	/* If the buffer is full, send it out. */
340 	if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER)
341 		ath9k_regwrite_multi(common);
342 
343 	mutex_unlock(&priv->wmi->multi_write_mutex);
344 }
345 
346 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
347 {
348 	struct ath_hw *ah = hw_priv;
349 	struct ath_common *common = ath9k_hw_common(ah);
350 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
351 
352 	if (atomic_read(&priv->wmi->mwrite_cnt))
353 		ath9k_regwrite_buffer(hw_priv, val, reg_offset);
354 	else
355 		ath9k_regwrite_single(hw_priv, val, reg_offset);
356 }
357 
358 static void ath9k_enable_regwrite_buffer(void *hw_priv)
359 {
360 	struct ath_hw *ah = hw_priv;
361 	struct ath_common *common = ath9k_hw_common(ah);
362 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
363 
364 	atomic_inc(&priv->wmi->mwrite_cnt);
365 }
366 
367 static void ath9k_regwrite_flush(void *hw_priv)
368 {
369 	struct ath_hw *ah = hw_priv;
370 	struct ath_common *common = ath9k_hw_common(ah);
371 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
372 
373 	atomic_dec(&priv->wmi->mwrite_cnt);
374 
375 	mutex_lock(&priv->wmi->multi_write_mutex);
376 
377 	if (priv->wmi->multi_write_idx)
378 		ath9k_regwrite_multi(common);
379 
380 	mutex_unlock(&priv->wmi->multi_write_mutex);
381 }
382 
383 static void ath9k_reg_rmw_buffer(void *hw_priv,
384 				 u32 reg_offset, u32 set, u32 clr)
385 {
386 	struct ath_hw *ah = hw_priv;
387 	struct ath_common *common = ath9k_hw_common(ah);
388 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
389 	u32 rsp_status;
390 	int r;
391 
392 	mutex_lock(&priv->wmi->multi_rmw_mutex);
393 
394 	/* Store the register/value */
395 	priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].reg =
396 		cpu_to_be32(reg_offset);
397 	priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].set =
398 		cpu_to_be32(set);
399 	priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].clr =
400 		cpu_to_be32(clr);
401 
402 	priv->wmi->multi_rmw_idx++;
403 
404 	/* If the buffer is full, send it out. */
405 	if (priv->wmi->multi_rmw_idx == MAX_RMW_CMD_NUMBER) {
406 		r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
407 			  (u8 *) &priv->wmi->multi_rmw,
408 			  sizeof(struct register_write) * priv->wmi->multi_rmw_idx,
409 			  (u8 *) &rsp_status, sizeof(rsp_status),
410 			  100);
411 		if (unlikely(r)) {
412 			ath_dbg(common, WMI,
413 				"REGISTER RMW FAILED, multi len: %d\n",
414 				priv->wmi->multi_rmw_idx);
415 		}
416 		priv->wmi->multi_rmw_idx = 0;
417 	}
418 
419 	mutex_unlock(&priv->wmi->multi_rmw_mutex);
420 }
421 
422 static void ath9k_reg_rmw_flush(void *hw_priv)
423 {
424 	struct ath_hw *ah = hw_priv;
425 	struct ath_common *common = ath9k_hw_common(ah);
426 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
427 	u32 rsp_status;
428 	int r;
429 
430 	if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
431 		return;
432 
433 	atomic_dec(&priv->wmi->m_rmw_cnt);
434 
435 	mutex_lock(&priv->wmi->multi_rmw_mutex);
436 
437 	if (priv->wmi->multi_rmw_idx) {
438 		r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
439 			  (u8 *) &priv->wmi->multi_rmw,
440 			  sizeof(struct register_rmw) * priv->wmi->multi_rmw_idx,
441 			  (u8 *) &rsp_status, sizeof(rsp_status),
442 			  100);
443 		if (unlikely(r)) {
444 			ath_dbg(common, WMI,
445 				"REGISTER RMW FAILED, multi len: %d\n",
446 				priv->wmi->multi_rmw_idx);
447 		}
448 		priv->wmi->multi_rmw_idx = 0;
449 	}
450 
451 	mutex_unlock(&priv->wmi->multi_rmw_mutex);
452 }
453 
454 static void ath9k_enable_rmw_buffer(void *hw_priv)
455 {
456 	struct ath_hw *ah = hw_priv;
457 	struct ath_common *common = ath9k_hw_common(ah);
458 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
459 
460 	if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
461 		return;
462 
463 	atomic_inc(&priv->wmi->m_rmw_cnt);
464 }
465 
466 static u32 ath9k_reg_rmw_single(void *hw_priv,
467 				 u32 reg_offset, u32 set, u32 clr)
468 {
469 	struct ath_hw *ah = hw_priv;
470 	struct ath_common *common = ath9k_hw_common(ah);
471 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
472 	struct register_rmw buf, buf_ret;
473 	int ret;
474 	u32 val = 0;
475 
476 	buf.reg = cpu_to_be32(reg_offset);
477 	buf.set = cpu_to_be32(set);
478 	buf.clr = cpu_to_be32(clr);
479 
480 	ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
481 			  (u8 *) &buf, sizeof(buf),
482 			  (u8 *) &buf_ret, sizeof(buf_ret),
483 			  100);
484 	if (unlikely(ret)) {
485 		ath_dbg(common, WMI, "REGISTER RMW FAILED:(0x%04x, %d)\n",
486 			reg_offset, ret);
487 	}
488 	return val;
489 }
490 
491 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
492 {
493 	struct ath_hw *ah = hw_priv;
494 	struct ath_common *common = ath9k_hw_common(ah);
495 	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
496 
497 	if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags)) {
498 		u32 val;
499 
500 		val = REG_READ(ah, reg_offset);
501 		val &= ~clr;
502 		val |= set;
503 		REG_WRITE(ah, reg_offset, val);
504 
505 		return 0;
506 	}
507 
508 	if (atomic_read(&priv->wmi->m_rmw_cnt))
509 		ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr);
510 	else
511 		ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr);
512 
513 	return 0;
514 }
515 
516 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
517 {
518 	*csz = L1_CACHE_BYTES >> 2;
519 }
520 
521 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
522 {
523 	struct ath_hw *ah = (struct ath_hw *) common->ah;
524 
525 	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
526 
527 	if (!ath9k_hw_wait(ah,
528 			   AR_EEPROM_STATUS_DATA,
529 			   AR_EEPROM_STATUS_DATA_BUSY |
530 			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
531 			   AH_WAIT_TIMEOUT))
532 		return false;
533 
534 	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
535 		   AR_EEPROM_STATUS_DATA_VAL);
536 
537 	return true;
538 }
539 
540 static const struct ath_bus_ops ath9k_usb_bus_ops = {
541 	.ath_bus_type = ATH_USB,
542 	.read_cachesize = ath_usb_read_cachesize,
543 	.eeprom_read = ath_usb_eeprom_read,
544 };
545 
546 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
547 {
548 	struct ath_common *common = ath9k_hw_common(priv->ah);
549 	int i;
550 
551 	for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
552 		priv->hwq_map[i] = -1;
553 
554 	priv->beacon.beaconq = ath9k_hw_beaconq_setup(priv->ah);
555 	if (priv->beacon.beaconq == -1) {
556 		ath_err(common, "Unable to setup BEACON xmit queue\n");
557 		goto err;
558 	}
559 
560 	priv->cabq = ath9k_htc_cabq_setup(priv);
561 	if (priv->cabq == -1) {
562 		ath_err(common, "Unable to setup CAB xmit queue\n");
563 		goto err;
564 	}
565 
566 	if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BE)) {
567 		ath_err(common, "Unable to setup xmit queue for BE traffic\n");
568 		goto err;
569 	}
570 
571 	if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BK)) {
572 		ath_err(common, "Unable to setup xmit queue for BK traffic\n");
573 		goto err;
574 	}
575 	if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VI)) {
576 		ath_err(common, "Unable to setup xmit queue for VI traffic\n");
577 		goto err;
578 	}
579 	if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VO)) {
580 		ath_err(common, "Unable to setup xmit queue for VO traffic\n");
581 		goto err;
582 	}
583 
584 	return 0;
585 
586 err:
587 	return -EINVAL;
588 }
589 
590 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
591 {
592 	struct ath_common *common = ath9k_hw_common(priv->ah);
593 
594 	memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
595 
596 	common->last_rssi = ATH_RSSI_DUMMY_MARKER;
597 	priv->ah->opmode = NL80211_IFTYPE_STATION;
598 
599 	priv->spec_priv.ah = priv->ah;
600 	priv->spec_priv.spec_config.enabled = 0;
601 	priv->spec_priv.spec_config.short_repeat = true;
602 	priv->spec_priv.spec_config.count = 8;
603 	priv->spec_priv.spec_config.endless = false;
604 	priv->spec_priv.spec_config.period = 0x12;
605 	priv->spec_priv.spec_config.fft_period = 0x02;
606 }
607 
608 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
609 			   u16 devid, char *product,
610 			   u32 drv_info)
611 {
612 	struct ath_hw *ah = NULL;
613 	struct ath_common *common;
614 	int i, ret = 0, csz = 0;
615 
616 	ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
617 	if (!ah)
618 		return -ENOMEM;
619 
620 	ah->dev = priv->dev;
621 	ah->hw = priv->hw;
622 	ah->hw_version.devid = devid;
623 	ah->hw_version.usbdev = drv_info;
624 	ah->ah_flags |= AH_USE_EEPROM;
625 	ah->reg_ops.read = ath9k_regread;
626 	ah->reg_ops.multi_read = ath9k_multi_regread;
627 	ah->reg_ops.write = ath9k_regwrite;
628 	ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
629 	ah->reg_ops.write_flush = ath9k_regwrite_flush;
630 	ah->reg_ops.enable_rmw_buffer = ath9k_enable_rmw_buffer;
631 	ah->reg_ops.rmw_flush = ath9k_reg_rmw_flush;
632 	ah->reg_ops.rmw = ath9k_reg_rmw;
633 	priv->ah = ah;
634 
635 	common = ath9k_hw_common(ah);
636 	common->ops = &ah->reg_ops;
637 	common->ps_ops = &ath9k_htc_ps_ops;
638 	common->bus_ops = &ath9k_usb_bus_ops;
639 	common->ah = ah;
640 	common->hw = priv->hw;
641 	common->priv = priv;
642 	common->debug_mask = ath9k_debug;
643 	common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
644 	set_bit(ATH_OP_INVALID, &common->op_flags);
645 
646 	spin_lock_init(&priv->beacon_lock);
647 	spin_lock_init(&priv->tx.tx_lock);
648 	mutex_init(&priv->mutex);
649 	mutex_init(&priv->htc_pm_lock);
650 	tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
651 		     (unsigned long)priv);
652 	tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
653 		     (unsigned long)priv);
654 	INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
655 	INIT_WORK(&priv->ps_work, ath9k_ps_work);
656 	INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
657 	timer_setup(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer, 0);
658 
659 	/*
660 	 * Cache line size is used to size and align various
661 	 * structures used to communicate with the hardware.
662 	 */
663 	ath_read_cachesize(common, &csz);
664 	common->cachelsz = csz << 2; /* convert to bytes */
665 
666 	ret = ath9k_hw_init(ah);
667 	if (ret) {
668 		ath_err(common,
669 			"Unable to initialize hardware; initialization status: %d\n",
670 			ret);
671 		goto err_hw;
672 	}
673 
674 	ret = ath9k_init_queues(priv);
675 	if (ret)
676 		goto err_queues;
677 
678 	for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
679 		priv->beacon.bslot[i] = NULL;
680 	priv->beacon.slottime = 9;
681 
682 	ath9k_cmn_init_channels_rates(common);
683 	ath9k_cmn_init_crypto(ah);
684 	ath9k_init_misc(priv);
685 	ath9k_htc_init_btcoex(priv, product);
686 
687 	return 0;
688 
689 err_queues:
690 	ath9k_hw_deinit(ah);
691 err_hw:
692 
693 	kfree(ah);
694 	priv->ah = NULL;
695 
696 	return ret;
697 }
698 
699 static const struct ieee80211_iface_limit if_limits[] = {
700 	{ .max = 2,	.types = BIT(NL80211_IFTYPE_STATION) |
701 				 BIT(NL80211_IFTYPE_P2P_CLIENT) },
702 	{ .max = 2,	.types = BIT(NL80211_IFTYPE_AP) |
703 #ifdef CONFIG_MAC80211_MESH
704 				 BIT(NL80211_IFTYPE_MESH_POINT) |
705 #endif
706 				 BIT(NL80211_IFTYPE_P2P_GO) },
707 };
708 
709 static const struct ieee80211_iface_combination if_comb = {
710 	.limits = if_limits,
711 	.n_limits = ARRAY_SIZE(if_limits),
712 	.max_interfaces = 2,
713 	.num_different_channels = 1,
714 };
715 
716 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
717 			       struct ieee80211_hw *hw)
718 {
719 	struct ath_hw *ah = priv->ah;
720 	struct ath_common *common = ath9k_hw_common(priv->ah);
721 	struct base_eep_header *pBase;
722 
723 	ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
724 	ieee80211_hw_set(hw, MFP_CAPABLE);
725 	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
726 	ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
727 	ieee80211_hw_set(hw, RX_INCLUDES_FCS);
728 	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
729 	ieee80211_hw_set(hw, SPECTRUM_MGMT);
730 	ieee80211_hw_set(hw, SIGNAL_DBM);
731 	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
732 
733 	if (ath9k_ps_enable)
734 		ieee80211_hw_set(hw, SUPPORTS_PS);
735 
736 	hw->wiphy->interface_modes =
737 		BIT(NL80211_IFTYPE_STATION) |
738 		BIT(NL80211_IFTYPE_ADHOC) |
739 		BIT(NL80211_IFTYPE_AP) |
740 		BIT(NL80211_IFTYPE_P2P_GO) |
741 		BIT(NL80211_IFTYPE_P2P_CLIENT) |
742 		BIT(NL80211_IFTYPE_MESH_POINT) |
743 		BIT(NL80211_IFTYPE_OCB);
744 
745 	hw->wiphy->iface_combinations = &if_comb;
746 	hw->wiphy->n_iface_combinations = 1;
747 
748 	hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
749 
750 	hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
751 			    WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
752 			    WIPHY_FLAG_HAS_CHANNEL_SWITCH;
753 
754 	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
755 
756 	hw->queues = 4;
757 	hw->max_listen_interval = 1;
758 
759 	hw->vif_data_size = sizeof(struct ath9k_htc_vif);
760 	hw->sta_data_size = sizeof(struct ath9k_htc_sta);
761 
762 	/* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
763 	hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
764 		sizeof(struct htc_frame_hdr) + 4;
765 
766 	if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
767 		hw->wiphy->bands[NL80211_BAND_2GHZ] =
768 			&common->sbands[NL80211_BAND_2GHZ];
769 	if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
770 		hw->wiphy->bands[NL80211_BAND_5GHZ] =
771 			&common->sbands[NL80211_BAND_5GHZ];
772 
773 	ath9k_cmn_reload_chainmask(ah);
774 
775 	pBase = ath9k_htc_get_eeprom_base(priv);
776 	if (pBase) {
777 		hw->wiphy->available_antennas_rx = pBase->rxMask;
778 		hw->wiphy->available_antennas_tx = pBase->txMask;
779 	}
780 
781 	SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
782 
783 	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
784 }
785 
786 static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
787 {
788 	struct ieee80211_hw *hw = priv->hw;
789 	struct wmi_fw_version cmd_rsp;
790 	int ret;
791 
792 	memset(&cmd_rsp, 0, sizeof(cmd_rsp));
793 
794 	WMI_CMD(WMI_GET_FW_VERSION);
795 	if (ret)
796 		return -EINVAL;
797 
798 	priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
799 	priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
800 
801 	snprintf(hw->wiphy->fw_version, sizeof(hw->wiphy->fw_version), "%d.%d",
802 		 priv->fw_version_major,
803 		 priv->fw_version_minor);
804 
805 	dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
806 		 priv->fw_version_major,
807 		 priv->fw_version_minor);
808 
809 	/*
810 	 * Check if the available FW matches the driver's
811 	 * required version.
812 	 */
813 	if (priv->fw_version_major != MAJOR_VERSION_REQ ||
814 	    priv->fw_version_minor < MINOR_VERSION_REQ) {
815 		dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
816 			MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
817 		return -EINVAL;
818 	}
819 
820 	if (priv->fw_version_major == 1 && priv->fw_version_minor < 4)
821 		set_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags);
822 
823 	dev_info(priv->dev, "FW RMW support: %s\n",
824 		test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags) ? "Off" : "On");
825 
826 	return 0;
827 }
828 
829 static int ath9k_init_device(struct ath9k_htc_priv *priv,
830 			     u16 devid, char *product, u32 drv_info)
831 {
832 	struct ieee80211_hw *hw = priv->hw;
833 	struct ath_common *common;
834 	struct ath_hw *ah;
835 	int error = 0;
836 	struct ath_regulatory *reg;
837 	char hw_name[64];
838 
839 	/* Bring up device */
840 	error = ath9k_init_priv(priv, devid, product, drv_info);
841 	if (error != 0)
842 		goto err_init;
843 
844 	ah = priv->ah;
845 	common = ath9k_hw_common(ah);
846 	ath9k_set_hw_capab(priv, hw);
847 
848 	error = ath9k_init_firmware_version(priv);
849 	if (error != 0)
850 		goto err_fw;
851 
852 	/* Initialize regulatory */
853 	error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
854 			      ath9k_reg_notifier);
855 	if (error)
856 		goto err_regd;
857 
858 	reg = &common->regulatory;
859 
860 	/* Setup TX */
861 	error = ath9k_tx_init(priv);
862 	if (error != 0)
863 		goto err_tx;
864 
865 	/* Setup RX */
866 	error = ath9k_rx_init(priv);
867 	if (error != 0)
868 		goto err_rx;
869 
870 	ath9k_hw_disable(priv->ah);
871 #ifdef CONFIG_MAC80211_LEDS
872 	/* must be initialized before ieee80211_register_hw */
873 	priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
874 		IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
875 		ARRAY_SIZE(ath9k_htc_tpt_blink));
876 #endif
877 
878 	/* Register with mac80211 */
879 	error = ieee80211_register_hw(hw);
880 	if (error)
881 		goto err_register;
882 
883 	/* Handle world regulatory */
884 	if (!ath_is_world_regd(reg)) {
885 		error = regulatory_hint(hw->wiphy, reg->alpha2);
886 		if (error)
887 			goto err_world;
888 	}
889 
890 	error = ath9k_htc_init_debug(priv->ah);
891 	if (error) {
892 		ath_err(common, "Unable to create debugfs files\n");
893 		goto err_world;
894 	}
895 
896 	ath_dbg(common, CONFIG,
897 		"WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
898 		priv->wmi_cmd_ep,
899 		priv->beacon_ep,
900 		priv->cab_ep,
901 		priv->uapsd_ep,
902 		priv->mgmt_ep,
903 		priv->data_be_ep,
904 		priv->data_bk_ep,
905 		priv->data_vi_ep,
906 		priv->data_vo_ep);
907 
908 	ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
909 	wiphy_info(hw->wiphy, "%s\n", hw_name);
910 
911 	ath9k_init_leds(priv);
912 	ath9k_start_rfkill_poll(priv);
913 
914 	return 0;
915 
916 err_world:
917 	ieee80211_unregister_hw(hw);
918 err_register:
919 	ath9k_rx_cleanup(priv);
920 err_rx:
921 	ath9k_tx_cleanup(priv);
922 err_tx:
923 	/* Nothing */
924 err_regd:
925 	/* Nothing */
926 err_fw:
927 	ath9k_deinit_priv(priv);
928 err_init:
929 	return error;
930 }
931 
932 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
933 			   u16 devid, char *product, u32 drv_info)
934 {
935 	struct ieee80211_hw *hw;
936 	struct ath9k_htc_priv *priv;
937 	int ret;
938 
939 	hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
940 	if (!hw)
941 		return -ENOMEM;
942 
943 	priv = hw->priv;
944 	priv->hw = hw;
945 	priv->htc = htc_handle;
946 	priv->dev = dev;
947 	htc_handle->drv_priv = priv;
948 	SET_IEEE80211_DEV(hw, priv->dev);
949 
950 	ret = ath9k_htc_wait_for_target(priv);
951 	if (ret)
952 		goto err_free;
953 
954 	priv->wmi = ath9k_init_wmi(priv);
955 	if (!priv->wmi) {
956 		ret = -EINVAL;
957 		goto err_free;
958 	}
959 
960 	ret = ath9k_init_htc_services(priv, devid, drv_info);
961 	if (ret)
962 		goto err_init;
963 
964 	ret = ath9k_init_device(priv, devid, product, drv_info);
965 	if (ret)
966 		goto err_init;
967 
968 	return 0;
969 
970 err_init:
971 	ath9k_deinit_wmi(priv);
972 err_free:
973 	ieee80211_free_hw(hw);
974 	return ret;
975 }
976 
977 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
978 {
979 	if (htc_handle->drv_priv) {
980 
981 		/* Check if the device has been yanked out. */
982 		if (hotunplug)
983 			htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
984 
985 		ath9k_deinit_device(htc_handle->drv_priv);
986 		ath9k_deinit_wmi(htc_handle->drv_priv);
987 		ieee80211_free_hw(htc_handle->drv_priv->hw);
988 	}
989 }
990 
991 #ifdef CONFIG_PM
992 
993 void ath9k_htc_suspend(struct htc_target *htc_handle)
994 {
995 	ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
996 }
997 
998 int ath9k_htc_resume(struct htc_target *htc_handle)
999 {
1000 	struct ath9k_htc_priv *priv = htc_handle->drv_priv;
1001 	int ret;
1002 
1003 	ret = ath9k_htc_wait_for_target(priv);
1004 	if (ret)
1005 		return ret;
1006 
1007 	ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
1008 				      priv->ah->hw_version.usbdev);
1009 	ath9k_configure_leds(priv);
1010 
1011 	return ret;
1012 }
1013 #endif
1014 
1015 static int __init ath9k_htc_init(void)
1016 {
1017 	if (ath9k_hif_usb_init() < 0) {
1018 		pr_err("No USB devices found, driver not installed\n");
1019 		return -ENODEV;
1020 	}
1021 
1022 	return 0;
1023 }
1024 module_init(ath9k_htc_init);
1025 
1026 static void __exit ath9k_htc_exit(void)
1027 {
1028 	ath9k_hif_usb_exit();
1029 	pr_info("Driver unloaded\n");
1030 }
1031 module_exit(ath9k_htc_exit);
1032