1 /* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "htc.h" 18 19 MODULE_AUTHOR("Atheros Communications"); 20 MODULE_LICENSE("Dual BSD/GPL"); 21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); 22 23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 24 module_param_named(debug, ath9k_debug, uint, 0); 25 MODULE_PARM_DESC(debug, "Debugging mask"); 26 27 int htc_modparam_nohwcrypt; 28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30 31 #define CHAN2G(_freq, _idx) { \ 32 .center_freq = (_freq), \ 33 .hw_value = (_idx), \ 34 .max_power = 20, \ 35 } 36 37 #define CHAN5G(_freq, _idx) { \ 38 .band = IEEE80211_BAND_5GHZ, \ 39 .center_freq = (_freq), \ 40 .hw_value = (_idx), \ 41 .max_power = 20, \ 42 } 43 44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193" 45 46 static struct ieee80211_channel ath9k_2ghz_channels[] = { 47 CHAN2G(2412, 0), /* Channel 1 */ 48 CHAN2G(2417, 1), /* Channel 2 */ 49 CHAN2G(2422, 2), /* Channel 3 */ 50 CHAN2G(2427, 3), /* Channel 4 */ 51 CHAN2G(2432, 4), /* Channel 5 */ 52 CHAN2G(2437, 5), /* Channel 6 */ 53 CHAN2G(2442, 6), /* Channel 7 */ 54 CHAN2G(2447, 7), /* Channel 8 */ 55 CHAN2G(2452, 8), /* Channel 9 */ 56 CHAN2G(2457, 9), /* Channel 10 */ 57 CHAN2G(2462, 10), /* Channel 11 */ 58 CHAN2G(2467, 11), /* Channel 12 */ 59 CHAN2G(2472, 12), /* Channel 13 */ 60 CHAN2G(2484, 13), /* Channel 14 */ 61 }; 62 63 static struct ieee80211_channel ath9k_5ghz_channels[] = { 64 /* _We_ call this UNII 1 */ 65 CHAN5G(5180, 14), /* Channel 36 */ 66 CHAN5G(5200, 15), /* Channel 40 */ 67 CHAN5G(5220, 16), /* Channel 44 */ 68 CHAN5G(5240, 17), /* Channel 48 */ 69 /* _We_ call this UNII 2 */ 70 CHAN5G(5260, 18), /* Channel 52 */ 71 CHAN5G(5280, 19), /* Channel 56 */ 72 CHAN5G(5300, 20), /* Channel 60 */ 73 CHAN5G(5320, 21), /* Channel 64 */ 74 /* _We_ call this "Middle band" */ 75 CHAN5G(5500, 22), /* Channel 100 */ 76 CHAN5G(5520, 23), /* Channel 104 */ 77 CHAN5G(5540, 24), /* Channel 108 */ 78 CHAN5G(5560, 25), /* Channel 112 */ 79 CHAN5G(5580, 26), /* Channel 116 */ 80 CHAN5G(5600, 27), /* Channel 120 */ 81 CHAN5G(5620, 28), /* Channel 124 */ 82 CHAN5G(5640, 29), /* Channel 128 */ 83 CHAN5G(5660, 30), /* Channel 132 */ 84 CHAN5G(5680, 31), /* Channel 136 */ 85 CHAN5G(5700, 32), /* Channel 140 */ 86 /* _We_ call this UNII 3 */ 87 CHAN5G(5745, 33), /* Channel 149 */ 88 CHAN5G(5765, 34), /* Channel 153 */ 89 CHAN5G(5785, 35), /* Channel 157 */ 90 CHAN5G(5805, 36), /* Channel 161 */ 91 CHAN5G(5825, 37), /* Channel 165 */ 92 }; 93 94 /* Atheros hardware rate code addition for short premble */ 95 #define SHPCHECK(__hw_rate, __flags) \ 96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) 97 98 #define RATE(_bitrate, _hw_rate, _flags) { \ 99 .bitrate = (_bitrate), \ 100 .flags = (_flags), \ 101 .hw_value = (_hw_rate), \ 102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 103 } 104 105 static struct ieee80211_rate ath9k_legacy_rates[] = { 106 RATE(10, 0x1b, 0), 107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ 108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ 109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ 110 RATE(60, 0x0b, 0), 111 RATE(90, 0x0f, 0), 112 RATE(120, 0x0a, 0), 113 RATE(180, 0x0e, 0), 114 RATE(240, 0x09, 0), 115 RATE(360, 0x0d, 0), 116 RATE(480, 0x08, 0), 117 RATE(540, 0x0c, 0), 118 }; 119 120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) 121 { 122 int time_left; 123 124 if (atomic_read(&priv->htc->tgt_ready) > 0) { 125 atomic_dec(&priv->htc->tgt_ready); 126 return 0; 127 } 128 129 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ 130 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); 131 if (!time_left) { 132 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); 133 return -ETIMEDOUT; 134 } 135 136 atomic_dec(&priv->htc->tgt_ready); 137 138 return 0; 139 } 140 141 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) 142 { 143 ath9k_htc_exit_debug(priv->ah); 144 ath9k_hw_deinit(priv->ah); 145 kfree(priv->ah); 146 priv->ah = NULL; 147 } 148 149 static void ath9k_deinit_device(struct ath9k_htc_priv *priv) 150 { 151 struct ieee80211_hw *hw = priv->hw; 152 153 wiphy_rfkill_stop_polling(hw->wiphy); 154 ath9k_deinit_leds(priv); 155 ieee80211_unregister_hw(hw); 156 ath9k_rx_cleanup(priv); 157 ath9k_tx_cleanup(priv); 158 ath9k_deinit_priv(priv); 159 } 160 161 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, 162 u16 service_id, 163 void (*tx) (void *, 164 struct sk_buff *, 165 enum htc_endpoint_id, 166 bool txok), 167 enum htc_endpoint_id *ep_id) 168 { 169 struct htc_service_connreq req; 170 171 memset(&req, 0, sizeof(struct htc_service_connreq)); 172 173 req.service_id = service_id; 174 req.ep_callbacks.priv = priv; 175 req.ep_callbacks.rx = ath9k_htc_rxep; 176 req.ep_callbacks.tx = tx; 177 178 return htc_connect_service(priv->htc, &req, ep_id); 179 } 180 181 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid, 182 u32 drv_info) 183 { 184 int ret; 185 186 /* WMI CMD*/ 187 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); 188 if (ret) 189 goto err; 190 191 /* Beacon */ 192 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep, 193 &priv->beacon_ep); 194 if (ret) 195 goto err; 196 197 /* CAB */ 198 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, 199 &priv->cab_ep); 200 if (ret) 201 goto err; 202 203 204 /* UAPSD */ 205 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, 206 &priv->uapsd_ep); 207 if (ret) 208 goto err; 209 210 /* MGMT */ 211 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, 212 &priv->mgmt_ep); 213 if (ret) 214 goto err; 215 216 /* DATA BE */ 217 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, 218 &priv->data_be_ep); 219 if (ret) 220 goto err; 221 222 /* DATA BK */ 223 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, 224 &priv->data_bk_ep); 225 if (ret) 226 goto err; 227 228 /* DATA VI */ 229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, 230 &priv->data_vi_ep); 231 if (ret) 232 goto err; 233 234 /* DATA VO */ 235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, 236 &priv->data_vo_ep); 237 if (ret) 238 goto err; 239 240 /* 241 * Setup required credits before initializing HTC. 242 * This is a bit hacky, but, since queuing is done in 243 * the HIF layer, shouldn't matter much. 244 */ 245 246 if (IS_AR7010_DEVICE(drv_info)) 247 priv->htc->credits = 45; 248 else 249 priv->htc->credits = 33; 250 251 ret = htc_init(priv->htc); 252 if (ret) 253 goto err; 254 255 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n", 256 priv->htc->credits); 257 258 return 0; 259 260 err: 261 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); 262 return ret; 263 } 264 265 static int ath9k_reg_notifier(struct wiphy *wiphy, 266 struct regulatory_request *request) 267 { 268 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 269 struct ath9k_htc_priv *priv = hw->priv; 270 271 return ath_reg_notifier_apply(wiphy, request, 272 ath9k_hw_regulatory(priv->ah)); 273 } 274 275 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) 276 { 277 struct ath_hw *ah = (struct ath_hw *) hw_priv; 278 struct ath_common *common = ath9k_hw_common(ah); 279 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 280 __be32 val, reg = cpu_to_be32(reg_offset); 281 int r; 282 283 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 284 (u8 *) ®, sizeof(reg), 285 (u8 *) &val, sizeof(val), 286 100); 287 if (unlikely(r)) { 288 ath_dbg(common, ATH_DBG_WMI, 289 "REGISTER READ FAILED: (0x%04x, %d)\n", 290 reg_offset, r); 291 return -EIO; 292 } 293 294 return be32_to_cpu(val); 295 } 296 297 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) 298 { 299 struct ath_hw *ah = (struct ath_hw *) hw_priv; 300 struct ath_common *common = ath9k_hw_common(ah); 301 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 302 const __be32 buf[2] = { 303 cpu_to_be32(reg_offset), 304 cpu_to_be32(val), 305 }; 306 int r; 307 308 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 309 (u8 *) &buf, sizeof(buf), 310 (u8 *) &val, sizeof(val), 311 100); 312 if (unlikely(r)) { 313 ath_dbg(common, ATH_DBG_WMI, 314 "REGISTER WRITE FAILED:(0x%04x, %d)\n", 315 reg_offset, r); 316 } 317 } 318 319 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) 320 { 321 struct ath_hw *ah = (struct ath_hw *) hw_priv; 322 struct ath_common *common = ath9k_hw_common(ah); 323 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 324 u32 rsp_status; 325 int r; 326 327 mutex_lock(&priv->wmi->multi_write_mutex); 328 329 /* Store the register/value */ 330 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = 331 cpu_to_be32(reg_offset); 332 priv->wmi->multi_write[priv->wmi->multi_write_idx].val = 333 cpu_to_be32(val); 334 335 priv->wmi->multi_write_idx++; 336 337 /* If the buffer is full, send it out. */ 338 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) { 339 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 340 (u8 *) &priv->wmi->multi_write, 341 sizeof(struct register_write) * priv->wmi->multi_write_idx, 342 (u8 *) &rsp_status, sizeof(rsp_status), 343 100); 344 if (unlikely(r)) { 345 ath_dbg(common, ATH_DBG_WMI, 346 "REGISTER WRITE FAILED, multi len: %d\n", 347 priv->wmi->multi_write_idx); 348 } 349 priv->wmi->multi_write_idx = 0; 350 } 351 352 mutex_unlock(&priv->wmi->multi_write_mutex); 353 } 354 355 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) 356 { 357 struct ath_hw *ah = (struct ath_hw *) hw_priv; 358 struct ath_common *common = ath9k_hw_common(ah); 359 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 360 361 if (atomic_read(&priv->wmi->mwrite_cnt)) 362 ath9k_regwrite_buffer(hw_priv, val, reg_offset); 363 else 364 ath9k_regwrite_single(hw_priv, val, reg_offset); 365 } 366 367 static void ath9k_enable_regwrite_buffer(void *hw_priv) 368 { 369 struct ath_hw *ah = (struct ath_hw *) hw_priv; 370 struct ath_common *common = ath9k_hw_common(ah); 371 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 372 373 atomic_inc(&priv->wmi->mwrite_cnt); 374 } 375 376 static void ath9k_regwrite_flush(void *hw_priv) 377 { 378 struct ath_hw *ah = (struct ath_hw *) hw_priv; 379 struct ath_common *common = ath9k_hw_common(ah); 380 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 381 u32 rsp_status; 382 int r; 383 384 atomic_dec(&priv->wmi->mwrite_cnt); 385 386 mutex_lock(&priv->wmi->multi_write_mutex); 387 388 if (priv->wmi->multi_write_idx) { 389 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 390 (u8 *) &priv->wmi->multi_write, 391 sizeof(struct register_write) * priv->wmi->multi_write_idx, 392 (u8 *) &rsp_status, sizeof(rsp_status), 393 100); 394 if (unlikely(r)) { 395 ath_dbg(common, ATH_DBG_WMI, 396 "REGISTER WRITE FAILED, multi len: %d\n", 397 priv->wmi->multi_write_idx); 398 } 399 priv->wmi->multi_write_idx = 0; 400 } 401 402 mutex_unlock(&priv->wmi->multi_write_mutex); 403 } 404 405 static const struct ath_ops ath9k_common_ops = { 406 .read = ath9k_regread, 407 .write = ath9k_regwrite, 408 .enable_write_buffer = ath9k_enable_regwrite_buffer, 409 .write_flush = ath9k_regwrite_flush, 410 }; 411 412 static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 413 { 414 *csz = L1_CACHE_BYTES >> 2; 415 } 416 417 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 418 { 419 struct ath_hw *ah = (struct ath_hw *) common->ah; 420 421 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 422 423 if (!ath9k_hw_wait(ah, 424 AR_EEPROM_STATUS_DATA, 425 AR_EEPROM_STATUS_DATA_BUSY | 426 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 427 AH_WAIT_TIMEOUT)) 428 return false; 429 430 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 431 AR_EEPROM_STATUS_DATA_VAL); 432 433 return true; 434 } 435 436 static const struct ath_bus_ops ath9k_usb_bus_ops = { 437 .ath_bus_type = ATH_USB, 438 .read_cachesize = ath_usb_read_cachesize, 439 .eeprom_read = ath_usb_eeprom_read, 440 }; 441 442 static void setup_ht_cap(struct ath9k_htc_priv *priv, 443 struct ieee80211_sta_ht_cap *ht_info) 444 { 445 struct ath_common *common = ath9k_hw_common(priv->ah); 446 u8 tx_streams, rx_streams; 447 int i; 448 449 ht_info->ht_supported = true; 450 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 451 IEEE80211_HT_CAP_SM_PS | 452 IEEE80211_HT_CAP_SGI_40 | 453 IEEE80211_HT_CAP_DSSSCCK40; 454 455 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 456 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 457 458 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 459 460 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 461 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 462 463 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 464 465 /* ath9k_htc supports only 1 or 2 stream devices */ 466 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); 467 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); 468 469 ath_dbg(common, ATH_DBG_CONFIG, 470 "TX streams %d, RX streams: %d\n", 471 tx_streams, rx_streams); 472 473 if (tx_streams != rx_streams) { 474 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 475 ht_info->mcs.tx_params |= ((tx_streams - 1) << 476 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 477 } 478 479 for (i = 0; i < rx_streams; i++) 480 ht_info->mcs.rx_mask[i] = 0xff; 481 482 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 483 } 484 485 static int ath9k_init_queues(struct ath9k_htc_priv *priv) 486 { 487 struct ath_common *common = ath9k_hw_common(priv->ah); 488 int i; 489 490 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) 491 priv->hwq_map[i] = -1; 492 493 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); 494 if (priv->beaconq == -1) { 495 ath_err(common, "Unable to setup BEACON xmit queue\n"); 496 goto err; 497 } 498 499 priv->cabq = ath9k_htc_cabq_setup(priv); 500 if (priv->cabq == -1) { 501 ath_err(common, "Unable to setup CAB xmit queue\n"); 502 goto err; 503 } 504 505 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { 506 ath_err(common, "Unable to setup xmit queue for BE traffic\n"); 507 goto err; 508 } 509 510 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { 511 ath_err(common, "Unable to setup xmit queue for BK traffic\n"); 512 goto err; 513 } 514 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { 515 ath_err(common, "Unable to setup xmit queue for VI traffic\n"); 516 goto err; 517 } 518 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { 519 ath_err(common, "Unable to setup xmit queue for VO traffic\n"); 520 goto err; 521 } 522 523 return 0; 524 525 err: 526 return -EINVAL; 527 } 528 529 static void ath9k_init_crypto(struct ath9k_htc_priv *priv) 530 { 531 struct ath_common *common = ath9k_hw_common(priv->ah); 532 int i = 0; 533 534 /* Get the hardware key cache size. */ 535 common->keymax = priv->ah->caps.keycache_size; 536 if (common->keymax > ATH_KEYMAX) { 537 ath_dbg(common, ATH_DBG_ANY, 538 "Warning, using only %u entries in %u key cache\n", 539 ATH_KEYMAX, common->keymax); 540 common->keymax = ATH_KEYMAX; 541 } 542 543 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) 544 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; 545 546 /* 547 * Reset the key cache since some parts do not 548 * reset the contents on initial power up. 549 */ 550 for (i = 0; i < common->keymax; i++) 551 ath_hw_keyreset(common, (u16) i); 552 } 553 554 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) 555 { 556 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 557 priv->sbands[IEEE80211_BAND_2GHZ].channels = 558 ath9k_2ghz_channels; 559 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 560 priv->sbands[IEEE80211_BAND_2GHZ].n_channels = 561 ARRAY_SIZE(ath9k_2ghz_channels); 562 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 563 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 564 ARRAY_SIZE(ath9k_legacy_rates); 565 } 566 567 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 568 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels; 569 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 570 priv->sbands[IEEE80211_BAND_5GHZ].n_channels = 571 ARRAY_SIZE(ath9k_5ghz_channels); 572 priv->sbands[IEEE80211_BAND_5GHZ].bitrates = 573 ath9k_legacy_rates + 4; 574 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 575 ARRAY_SIZE(ath9k_legacy_rates) - 4; 576 } 577 } 578 579 static void ath9k_init_misc(struct ath9k_htc_priv *priv) 580 { 581 struct ath_common *common = ath9k_hw_common(priv->ah); 582 583 common->tx_chainmask = priv->ah->caps.tx_chainmask; 584 common->rx_chainmask = priv->ah->caps.rx_chainmask; 585 586 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 587 588 priv->ah->opmode = NL80211_IFTYPE_STATION; 589 } 590 591 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv) 592 { 593 int qnum; 594 595 switch (priv->ah->btcoex_hw.scheme) { 596 case ATH_BTCOEX_CFG_NONE: 597 break; 598 case ATH_BTCOEX_CFG_3WIRE: 599 priv->ah->btcoex_hw.btactive_gpio = 7; 600 priv->ah->btcoex_hw.btpriority_gpio = 6; 601 priv->ah->btcoex_hw.wlanactive_gpio = 8; 602 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 603 ath9k_hw_btcoex_init_3wire(priv->ah); 604 ath_htc_init_btcoex_work(priv); 605 qnum = priv->hwq_map[WME_AC_BE]; 606 ath9k_hw_init_btcoex_hw(priv->ah, qnum); 607 break; 608 default: 609 WARN_ON(1); 610 break; 611 } 612 } 613 614 static int ath9k_init_priv(struct ath9k_htc_priv *priv, 615 u16 devid, char *product, 616 u32 drv_info) 617 { 618 struct ath_hw *ah = NULL; 619 struct ath_common *common; 620 int ret = 0, csz = 0; 621 622 priv->op_flags |= OP_INVALID; 623 624 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 625 if (!ah) 626 return -ENOMEM; 627 628 ah->hw_version.devid = devid; 629 ah->hw_version.subsysid = 0; /* FIXME */ 630 ah->hw_version.usbdev = drv_info; 631 ah->ah_flags |= AH_USE_EEPROM; 632 priv->ah = ah; 633 634 common = ath9k_hw_common(ah); 635 common->ops = &ath9k_common_ops; 636 common->bus_ops = &ath9k_usb_bus_ops; 637 common->ah = ah; 638 common->hw = priv->hw; 639 common->priv = priv; 640 common->debug_mask = ath9k_debug; 641 642 spin_lock_init(&priv->wmi->wmi_lock); 643 spin_lock_init(&priv->beacon_lock); 644 spin_lock_init(&priv->tx_lock); 645 mutex_init(&priv->mutex); 646 mutex_init(&priv->htc_pm_lock); 647 tasklet_init(&priv->swba_tasklet, ath9k_swba_tasklet, 648 (unsigned long)priv); 649 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, 650 (unsigned long)priv); 651 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, 652 (unsigned long)priv); 653 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work); 654 INIT_WORK(&priv->ps_work, ath9k_ps_work); 655 INIT_WORK(&priv->fatal_work, ath9k_fatal_work); 656 657 /* 658 * Cache line size is used to size and align various 659 * structures used to communicate with the hardware. 660 */ 661 ath_read_cachesize(common, &csz); 662 common->cachelsz = csz << 2; /* convert to bytes */ 663 664 ret = ath9k_hw_init(ah); 665 if (ret) { 666 ath_err(common, 667 "Unable to initialize hardware; initialization status: %d\n", 668 ret); 669 goto err_hw; 670 } 671 672 ret = ath9k_htc_init_debug(ah); 673 if (ret) { 674 ath_err(common, "Unable to create debugfs files\n"); 675 goto err_debug; 676 } 677 678 ret = ath9k_init_queues(priv); 679 if (ret) 680 goto err_queues; 681 682 ath9k_init_crypto(priv); 683 ath9k_init_channels_rates(priv); 684 ath9k_init_misc(priv); 685 686 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) { 687 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE; 688 ath9k_init_btcoex(priv); 689 } 690 691 return 0; 692 693 err_queues: 694 ath9k_htc_exit_debug(ah); 695 err_debug: 696 ath9k_hw_deinit(ah); 697 err_hw: 698 699 kfree(ah); 700 priv->ah = NULL; 701 702 return ret; 703 } 704 705 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, 706 struct ieee80211_hw *hw) 707 { 708 struct ath_common *common = ath9k_hw_common(priv->ah); 709 710 hw->flags = IEEE80211_HW_SIGNAL_DBM | 711 IEEE80211_HW_AMPDU_AGGREGATION | 712 IEEE80211_HW_SPECTRUM_MGMT | 713 IEEE80211_HW_HAS_RATE_CONTROL | 714 IEEE80211_HW_RX_INCLUDES_FCS | 715 IEEE80211_HW_SUPPORTS_PS | 716 IEEE80211_HW_PS_NULLFUNC_STACK; 717 718 hw->wiphy->interface_modes = 719 BIT(NL80211_IFTYPE_STATION) | 720 BIT(NL80211_IFTYPE_ADHOC); 721 722 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 723 724 hw->queues = 4; 725 hw->channel_change_time = 5000; 726 hw->max_listen_interval = 10; 727 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 728 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 729 730 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ 731 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + 732 sizeof(struct htc_frame_hdr) + 4; 733 734 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 735 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 736 &priv->sbands[IEEE80211_BAND_2GHZ]; 737 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 738 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 739 &priv->sbands[IEEE80211_BAND_5GHZ]; 740 741 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 742 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 743 setup_ht_cap(priv, 744 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); 745 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 746 setup_ht_cap(priv, 747 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap); 748 } 749 750 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 751 } 752 753 static int ath9k_init_device(struct ath9k_htc_priv *priv, 754 u16 devid, char *product, u32 drv_info) 755 { 756 struct ieee80211_hw *hw = priv->hw; 757 struct ath_common *common; 758 struct ath_hw *ah; 759 int error = 0; 760 struct ath_regulatory *reg; 761 762 /* Bring up device */ 763 error = ath9k_init_priv(priv, devid, product, drv_info); 764 if (error != 0) 765 goto err_init; 766 767 ah = priv->ah; 768 common = ath9k_hw_common(ah); 769 ath9k_set_hw_capab(priv, hw); 770 771 /* Initialize regulatory */ 772 error = ath_regd_init(&common->regulatory, priv->hw->wiphy, 773 ath9k_reg_notifier); 774 if (error) 775 goto err_regd; 776 777 reg = &common->regulatory; 778 779 /* Setup TX */ 780 error = ath9k_tx_init(priv); 781 if (error != 0) 782 goto err_tx; 783 784 /* Setup RX */ 785 error = ath9k_rx_init(priv); 786 if (error != 0) 787 goto err_rx; 788 789 /* Register with mac80211 */ 790 error = ieee80211_register_hw(hw); 791 if (error) 792 goto err_register; 793 794 /* Handle world regulatory */ 795 if (!ath_is_world_regd(reg)) { 796 error = regulatory_hint(hw->wiphy, reg->alpha2); 797 if (error) 798 goto err_world; 799 } 800 801 ath9k_init_leds(priv); 802 ath9k_start_rfkill_poll(priv); 803 804 return 0; 805 806 err_world: 807 ieee80211_unregister_hw(hw); 808 err_register: 809 ath9k_rx_cleanup(priv); 810 err_rx: 811 ath9k_tx_cleanup(priv); 812 err_tx: 813 /* Nothing */ 814 err_regd: 815 ath9k_deinit_priv(priv); 816 err_init: 817 return error; 818 } 819 820 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 821 u16 devid, char *product, u32 drv_info) 822 { 823 struct ieee80211_hw *hw; 824 struct ath9k_htc_priv *priv; 825 int ret; 826 827 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); 828 if (!hw) 829 return -ENOMEM; 830 831 priv = hw->priv; 832 priv->hw = hw; 833 priv->htc = htc_handle; 834 priv->dev = dev; 835 htc_handle->drv_priv = priv; 836 SET_IEEE80211_DEV(hw, priv->dev); 837 838 ret = ath9k_htc_wait_for_target(priv); 839 if (ret) 840 goto err_free; 841 842 priv->wmi = ath9k_init_wmi(priv); 843 if (!priv->wmi) { 844 ret = -EINVAL; 845 goto err_free; 846 } 847 848 ret = ath9k_init_htc_services(priv, devid, drv_info); 849 if (ret) 850 goto err_init; 851 852 ret = ath9k_init_device(priv, devid, product, drv_info); 853 if (ret) 854 goto err_init; 855 856 return 0; 857 858 err_init: 859 ath9k_deinit_wmi(priv); 860 err_free: 861 ieee80211_free_hw(hw); 862 return ret; 863 } 864 865 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 866 { 867 if (htc_handle->drv_priv) { 868 869 /* Check if the device has been yanked out. */ 870 if (hotunplug) 871 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED; 872 873 ath9k_deinit_device(htc_handle->drv_priv); 874 ath9k_deinit_wmi(htc_handle->drv_priv); 875 ieee80211_free_hw(htc_handle->drv_priv->hw); 876 } 877 } 878 879 #ifdef CONFIG_PM 880 881 void ath9k_htc_suspend(struct htc_target *htc_handle) 882 { 883 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP); 884 } 885 886 int ath9k_htc_resume(struct htc_target *htc_handle) 887 { 888 struct ath9k_htc_priv *priv = htc_handle->drv_priv; 889 int ret; 890 891 ret = ath9k_htc_wait_for_target(priv); 892 if (ret) 893 return ret; 894 895 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid, 896 priv->ah->hw_version.usbdev); 897 return ret; 898 } 899 #endif 900 901 static int __init ath9k_htc_init(void) 902 { 903 int error; 904 905 error = ath9k_htc_debug_create_root(); 906 if (error < 0) { 907 printk(KERN_ERR 908 "ath9k_htc: Unable to create debugfs root: %d\n", 909 error); 910 goto err_dbg; 911 } 912 913 error = ath9k_hif_usb_init(); 914 if (error < 0) { 915 printk(KERN_ERR 916 "ath9k_htc: No USB devices found," 917 " driver not installed.\n"); 918 error = -ENODEV; 919 goto err_usb; 920 } 921 922 return 0; 923 924 err_usb: 925 ath9k_htc_debug_remove_root(); 926 err_dbg: 927 return error; 928 } 929 module_init(ath9k_htc_init); 930 931 static void __exit ath9k_htc_exit(void) 932 { 933 ath9k_hif_usb_exit(); 934 ath9k_htc_debug_remove_root(); 935 printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); 936 } 937 module_exit(ath9k_htc_exit); 938