1fb9987d0SSujith /* 2fb9987d0SSujith * Copyright (c) 2010 Atheros Communications Inc. 3fb9987d0SSujith * 4fb9987d0SSujith * Permission to use, copy, modify, and/or distribute this software for any 5fb9987d0SSujith * purpose with or without fee is hereby granted, provided that the above 6fb9987d0SSujith * copyright notice and this permission notice appear in all copies. 7fb9987d0SSujith * 8fb9987d0SSujith * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9fb9987d0SSujith * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10fb9987d0SSujith * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11fb9987d0SSujith * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12fb9987d0SSujith * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13fb9987d0SSujith * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14fb9987d0SSujith * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15fb9987d0SSujith */ 16fb9987d0SSujith 17fb9987d0SSujith #include "htc.h" 18fb9987d0SSujith 19fb9987d0SSujith MODULE_AUTHOR("Atheros Communications"); 20fb9987d0SSujith MODULE_LICENSE("Dual BSD/GPL"); 21fb9987d0SSujith MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); 22fb9987d0SSujith 23fb9987d0SSujith static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 24fb9987d0SSujith module_param_named(debug, ath9k_debug, uint, 0); 25fb9987d0SSujith MODULE_PARM_DESC(debug, "Debugging mask"); 26fb9987d0SSujith 27e1572c5eSSujith int htc_modparam_nohwcrypt; 28e1572c5eSSujith module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 29fb9987d0SSujith MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30fb9987d0SSujith 31fb9987d0SSujith #define CHAN2G(_freq, _idx) { \ 32fb9987d0SSujith .center_freq = (_freq), \ 33fb9987d0SSujith .hw_value = (_idx), \ 34fb9987d0SSujith .max_power = 20, \ 35fb9987d0SSujith } 36fb9987d0SSujith 37fb9987d0SSujith static struct ieee80211_channel ath9k_2ghz_channels[] = { 38fb9987d0SSujith CHAN2G(2412, 0), /* Channel 1 */ 39fb9987d0SSujith CHAN2G(2417, 1), /* Channel 2 */ 40fb9987d0SSujith CHAN2G(2422, 2), /* Channel 3 */ 41fb9987d0SSujith CHAN2G(2427, 3), /* Channel 4 */ 42fb9987d0SSujith CHAN2G(2432, 4), /* Channel 5 */ 43fb9987d0SSujith CHAN2G(2437, 5), /* Channel 6 */ 44fb9987d0SSujith CHAN2G(2442, 6), /* Channel 7 */ 45fb9987d0SSujith CHAN2G(2447, 7), /* Channel 8 */ 46fb9987d0SSujith CHAN2G(2452, 8), /* Channel 9 */ 47fb9987d0SSujith CHAN2G(2457, 9), /* Channel 10 */ 48fb9987d0SSujith CHAN2G(2462, 10), /* Channel 11 */ 49fb9987d0SSujith CHAN2G(2467, 11), /* Channel 12 */ 50fb9987d0SSujith CHAN2G(2472, 12), /* Channel 13 */ 51fb9987d0SSujith CHAN2G(2484, 13), /* Channel 14 */ 52fb9987d0SSujith }; 53fb9987d0SSujith 54fb9987d0SSujith /* Atheros hardware rate code addition for short premble */ 55fb9987d0SSujith #define SHPCHECK(__hw_rate, __flags) \ 56fb9987d0SSujith ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) 57fb9987d0SSujith 58fb9987d0SSujith #define RATE(_bitrate, _hw_rate, _flags) { \ 59fb9987d0SSujith .bitrate = (_bitrate), \ 60fb9987d0SSujith .flags = (_flags), \ 61fb9987d0SSujith .hw_value = (_hw_rate), \ 62fb9987d0SSujith .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 63fb9987d0SSujith } 64fb9987d0SSujith 65fb9987d0SSujith static struct ieee80211_rate ath9k_legacy_rates[] = { 66fb9987d0SSujith RATE(10, 0x1b, 0), 67fb9987d0SSujith RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ 68fb9987d0SSujith RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ 69fb9987d0SSujith RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ 70fb9987d0SSujith RATE(60, 0x0b, 0), 71fb9987d0SSujith RATE(90, 0x0f, 0), 72fb9987d0SSujith RATE(120, 0x0a, 0), 73fb9987d0SSujith RATE(180, 0x0e, 0), 74fb9987d0SSujith RATE(240, 0x09, 0), 75fb9987d0SSujith RATE(360, 0x0d, 0), 76fb9987d0SSujith RATE(480, 0x08, 0), 77fb9987d0SSujith RATE(540, 0x0c, 0), 78fb9987d0SSujith }; 79fb9987d0SSujith 80fb9987d0SSujith static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) 81fb9987d0SSujith { 82fb9987d0SSujith int time_left; 83fb9987d0SSujith 84fb9987d0SSujith /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ 85fb9987d0SSujith time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); 86fb9987d0SSujith if (!time_left) { 87fb9987d0SSujith dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); 88fb9987d0SSujith return -ETIMEDOUT; 89fb9987d0SSujith } 90fb9987d0SSujith 91fb9987d0SSujith return 0; 92fb9987d0SSujith } 93fb9987d0SSujith 94fb9987d0SSujith static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) 95fb9987d0SSujith { 96e1572c5eSSujith ath9k_htc_exit_debug(priv->ah); 97fb9987d0SSujith ath9k_hw_deinit(priv->ah); 98fb9987d0SSujith tasklet_kill(&priv->wmi_tasklet); 99fb9987d0SSujith tasklet_kill(&priv->rx_tasklet); 100fb9987d0SSujith tasklet_kill(&priv->tx_tasklet); 101fb9987d0SSujith kfree(priv->ah); 102fb9987d0SSujith priv->ah = NULL; 103fb9987d0SSujith } 104fb9987d0SSujith 105fb9987d0SSujith static void ath9k_deinit_device(struct ath9k_htc_priv *priv) 106fb9987d0SSujith { 107fb9987d0SSujith struct ieee80211_hw *hw = priv->hw; 108fb9987d0SSujith 109fb9987d0SSujith wiphy_rfkill_stop_polling(hw->wiphy); 110fb9987d0SSujith ath9k_deinit_leds(priv); 111fb9987d0SSujith ieee80211_unregister_hw(hw); 112fb9987d0SSujith ath9k_rx_cleanup(priv); 113fb9987d0SSujith ath9k_tx_cleanup(priv); 114fb9987d0SSujith ath9k_deinit_priv(priv); 115fb9987d0SSujith } 116fb9987d0SSujith 117fb9987d0SSujith static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, 118fb9987d0SSujith u16 service_id, 119fb9987d0SSujith void (*tx) (void *, 120fb9987d0SSujith struct sk_buff *, 121fb9987d0SSujith enum htc_endpoint_id, 122fb9987d0SSujith bool txok), 123fb9987d0SSujith enum htc_endpoint_id *ep_id) 124fb9987d0SSujith { 125fb9987d0SSujith struct htc_service_connreq req; 126fb9987d0SSujith 127fb9987d0SSujith memset(&req, 0, sizeof(struct htc_service_connreq)); 128fb9987d0SSujith 129fb9987d0SSujith req.service_id = service_id; 130fb9987d0SSujith req.ep_callbacks.priv = priv; 131fb9987d0SSujith req.ep_callbacks.rx = ath9k_htc_rxep; 132fb9987d0SSujith req.ep_callbacks.tx = tx; 133fb9987d0SSujith 134fb9987d0SSujith return htc_connect_service(priv->htc, &req, ep_id); 135fb9987d0SSujith } 136fb9987d0SSujith 137fb9987d0SSujith static int ath9k_init_htc_services(struct ath9k_htc_priv *priv) 138fb9987d0SSujith { 139fb9987d0SSujith int ret; 140fb9987d0SSujith 141fb9987d0SSujith /* WMI CMD*/ 142fb9987d0SSujith ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); 143fb9987d0SSujith if (ret) 144fb9987d0SSujith goto err; 145fb9987d0SSujith 146fb9987d0SSujith /* Beacon */ 147fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, NULL, 148fb9987d0SSujith &priv->beacon_ep); 149fb9987d0SSujith if (ret) 150fb9987d0SSujith goto err; 151fb9987d0SSujith 152fb9987d0SSujith /* CAB */ 153fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, 154fb9987d0SSujith &priv->cab_ep); 155fb9987d0SSujith if (ret) 156fb9987d0SSujith goto err; 157fb9987d0SSujith 158fb9987d0SSujith 159fb9987d0SSujith /* UAPSD */ 160fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, 161fb9987d0SSujith &priv->uapsd_ep); 162fb9987d0SSujith if (ret) 163fb9987d0SSujith goto err; 164fb9987d0SSujith 165fb9987d0SSujith /* MGMT */ 166fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, 167fb9987d0SSujith &priv->mgmt_ep); 168fb9987d0SSujith if (ret) 169fb9987d0SSujith goto err; 170fb9987d0SSujith 171fb9987d0SSujith /* DATA BE */ 172fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, 173fb9987d0SSujith &priv->data_be_ep); 174fb9987d0SSujith if (ret) 175fb9987d0SSujith goto err; 176fb9987d0SSujith 177fb9987d0SSujith /* DATA BK */ 178fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, 179fb9987d0SSujith &priv->data_bk_ep); 180fb9987d0SSujith if (ret) 181fb9987d0SSujith goto err; 182fb9987d0SSujith 183fb9987d0SSujith /* DATA VI */ 184fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, 185fb9987d0SSujith &priv->data_vi_ep); 186fb9987d0SSujith if (ret) 187fb9987d0SSujith goto err; 188fb9987d0SSujith 189fb9987d0SSujith /* DATA VO */ 190fb9987d0SSujith ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, 191fb9987d0SSujith &priv->data_vo_ep); 192fb9987d0SSujith if (ret) 193fb9987d0SSujith goto err; 194fb9987d0SSujith 195fb9987d0SSujith ret = htc_init(priv->htc); 196fb9987d0SSujith if (ret) 197fb9987d0SSujith goto err; 198fb9987d0SSujith 199fb9987d0SSujith return 0; 200fb9987d0SSujith 201fb9987d0SSujith err: 202fb9987d0SSujith dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); 203fb9987d0SSujith return ret; 204fb9987d0SSujith } 205fb9987d0SSujith 206fb9987d0SSujith static int ath9k_reg_notifier(struct wiphy *wiphy, 207fb9987d0SSujith struct regulatory_request *request) 208fb9987d0SSujith { 209fb9987d0SSujith struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 210fb9987d0SSujith struct ath9k_htc_priv *priv = hw->priv; 211fb9987d0SSujith 212fb9987d0SSujith return ath_reg_notifier_apply(wiphy, request, 213fb9987d0SSujith ath9k_hw_regulatory(priv->ah)); 214fb9987d0SSujith } 215fb9987d0SSujith 216fb9987d0SSujith static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 217fb9987d0SSujith { 218fb9987d0SSujith struct ath_hw *ah = (struct ath_hw *) hw_priv; 219fb9987d0SSujith struct ath_common *common = ath9k_hw_common(ah); 220fb9987d0SSujith struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 221fb9987d0SSujith __be32 val, reg = cpu_to_be32(reg_offset); 222fb9987d0SSujith int r; 223fb9987d0SSujith 224fb9987d0SSujith r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 225fb9987d0SSujith (u8 *) ®, sizeof(reg), 226fb9987d0SSujith (u8 *) &val, sizeof(val), 227fb9987d0SSujith 100); 228fb9987d0SSujith if (unlikely(r)) { 229fb9987d0SSujith ath_print(common, ATH_DBG_WMI, 230fb9987d0SSujith "REGISTER READ FAILED: (0x%04x, %d)\n", 231fb9987d0SSujith reg_offset, r); 232fb9987d0SSujith return -EIO; 233fb9987d0SSujith } 234fb9987d0SSujith 235fb9987d0SSujith return be32_to_cpu(val); 236fb9987d0SSujith } 237fb9987d0SSujith 238fb9987d0SSujith static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 239fb9987d0SSujith { 240fb9987d0SSujith struct ath_hw *ah = (struct ath_hw *) hw_priv; 241fb9987d0SSujith struct ath_common *common = ath9k_hw_common(ah); 242fb9987d0SSujith struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 243fb9987d0SSujith __be32 buf[2] = { 244fb9987d0SSujith cpu_to_be32(reg_offset), 245fb9987d0SSujith cpu_to_be32(val), 246fb9987d0SSujith }; 247fb9987d0SSujith int r; 248fb9987d0SSujith 249fb9987d0SSujith r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 250fb9987d0SSujith (u8 *) &buf, sizeof(buf), 251fb9987d0SSujith (u8 *) &val, sizeof(val), 252fb9987d0SSujith 100); 253fb9987d0SSujith if (unlikely(r)) { 254fb9987d0SSujith ath_print(common, ATH_DBG_WMI, 255fb9987d0SSujith "REGISTER WRITE FAILED:(0x%04x, %d)\n", 256fb9987d0SSujith reg_offset, r); 257fb9987d0SSujith } 258fb9987d0SSujith } 259fb9987d0SSujith 260fb9987d0SSujith static const struct ath_ops ath9k_common_ops = { 261fb9987d0SSujith .read = ath9k_ioread32, 262fb9987d0SSujith .write = ath9k_iowrite32, 263fb9987d0SSujith }; 264fb9987d0SSujith 265fb9987d0SSujith static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 266fb9987d0SSujith { 267fb9987d0SSujith *csz = L1_CACHE_BYTES >> 2; 268fb9987d0SSujith } 269fb9987d0SSujith 270fb9987d0SSujith static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 271fb9987d0SSujith { 272fb9987d0SSujith struct ath_hw *ah = (struct ath_hw *) common->ah; 273fb9987d0SSujith 274fb9987d0SSujith (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 275fb9987d0SSujith 276fb9987d0SSujith if (!ath9k_hw_wait(ah, 277fb9987d0SSujith AR_EEPROM_STATUS_DATA, 278fb9987d0SSujith AR_EEPROM_STATUS_DATA_BUSY | 279fb9987d0SSujith AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 280fb9987d0SSujith AH_WAIT_TIMEOUT)) 281fb9987d0SSujith return false; 282fb9987d0SSujith 283fb9987d0SSujith *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 284fb9987d0SSujith AR_EEPROM_STATUS_DATA_VAL); 285fb9987d0SSujith 286fb9987d0SSujith return true; 287fb9987d0SSujith } 288fb9987d0SSujith 289fb9987d0SSujith static const struct ath_bus_ops ath9k_usb_bus_ops = { 290fb9987d0SSujith .read_cachesize = ath_usb_read_cachesize, 291fb9987d0SSujith .eeprom_read = ath_usb_eeprom_read, 292fb9987d0SSujith }; 293fb9987d0SSujith 294fb9987d0SSujith static void setup_ht_cap(struct ath9k_htc_priv *priv, 295fb9987d0SSujith struct ieee80211_sta_ht_cap *ht_info) 296fb9987d0SSujith { 297fb9987d0SSujith ht_info->ht_supported = true; 298fb9987d0SSujith ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 299fb9987d0SSujith IEEE80211_HT_CAP_SM_PS | 300fb9987d0SSujith IEEE80211_HT_CAP_SGI_40 | 301fb9987d0SSujith IEEE80211_HT_CAP_DSSSCCK40; 302fb9987d0SSujith 303fb9987d0SSujith ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 304fb9987d0SSujith ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 305fb9987d0SSujith 306fb9987d0SSujith memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 307fb9987d0SSujith ht_info->mcs.rx_mask[0] = 0xff; 308fb9987d0SSujith ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 309fb9987d0SSujith } 310fb9987d0SSujith 311fb9987d0SSujith static int ath9k_init_queues(struct ath9k_htc_priv *priv) 312fb9987d0SSujith { 313fb9987d0SSujith struct ath_common *common = ath9k_hw_common(priv->ah); 314fb9987d0SSujith int i; 315fb9987d0SSujith 316fb9987d0SSujith for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) 317fb9987d0SSujith priv->hwq_map[i] = -1; 318fb9987d0SSujith 319fb9987d0SSujith if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BE)) { 320fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 321fb9987d0SSujith "Unable to setup xmit queue for BE traffic\n"); 322fb9987d0SSujith goto err; 323fb9987d0SSujith } 324fb9987d0SSujith 325fb9987d0SSujith if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BK)) { 326fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 327fb9987d0SSujith "Unable to setup xmit queue for BK traffic\n"); 328fb9987d0SSujith goto err; 329fb9987d0SSujith } 330fb9987d0SSujith if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VI)) { 331fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 332fb9987d0SSujith "Unable to setup xmit queue for VI traffic\n"); 333fb9987d0SSujith goto err; 334fb9987d0SSujith } 335fb9987d0SSujith if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VO)) { 336fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 337fb9987d0SSujith "Unable to setup xmit queue for VO traffic\n"); 338fb9987d0SSujith goto err; 339fb9987d0SSujith } 340fb9987d0SSujith 341fb9987d0SSujith return 0; 342fb9987d0SSujith 343fb9987d0SSujith err: 344fb9987d0SSujith return -EINVAL; 345fb9987d0SSujith } 346fb9987d0SSujith 347fb9987d0SSujith static void ath9k_init_crypto(struct ath9k_htc_priv *priv) 348fb9987d0SSujith { 349fb9987d0SSujith struct ath_common *common = ath9k_hw_common(priv->ah); 350fb9987d0SSujith int i = 0; 351fb9987d0SSujith 352fb9987d0SSujith /* Get the hardware key cache size. */ 353fb9987d0SSujith common->keymax = priv->ah->caps.keycache_size; 354fb9987d0SSujith if (common->keymax > ATH_KEYMAX) { 355fb9987d0SSujith ath_print(common, ATH_DBG_ANY, 356fb9987d0SSujith "Warning, using only %u entries in %u key cache\n", 357fb9987d0SSujith ATH_KEYMAX, common->keymax); 358fb9987d0SSujith common->keymax = ATH_KEYMAX; 359fb9987d0SSujith } 360fb9987d0SSujith 361fb9987d0SSujith /* 362fb9987d0SSujith * Reset the key cache since some parts do not 363fb9987d0SSujith * reset the contents on initial power up. 364fb9987d0SSujith */ 365fb9987d0SSujith for (i = 0; i < common->keymax; i++) 366fb9987d0SSujith ath9k_hw_keyreset(priv->ah, (u16) i); 367fb9987d0SSujith 368fb9987d0SSujith if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER, 369fb9987d0SSujith ATH9K_CIPHER_TKIP, NULL)) { 370fb9987d0SSujith /* 371fb9987d0SSujith * Whether we should enable h/w TKIP MIC. 372fb9987d0SSujith * XXX: if we don't support WME TKIP MIC, then we wouldn't 373fb9987d0SSujith * report WMM capable, so it's always safe to turn on 374fb9987d0SSujith * TKIP MIC in this case. 375fb9987d0SSujith */ 376fb9987d0SSujith ath9k_hw_setcapability(priv->ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL); 377fb9987d0SSujith } 378fb9987d0SSujith 379fb9987d0SSujith /* 380fb9987d0SSujith * Check whether the separate key cache entries 381fb9987d0SSujith * are required to handle both tx+rx MIC keys. 382fb9987d0SSujith * With split mic keys the number of stations is limited 383fb9987d0SSujith * to 27 otherwise 59. 384fb9987d0SSujith */ 385fb9987d0SSujith if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER, 386fb9987d0SSujith ATH9K_CIPHER_TKIP, NULL) 387fb9987d0SSujith && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER, 388fb9987d0SSujith ATH9K_CIPHER_MIC, NULL) 389fb9987d0SSujith && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_TKIP_SPLIT, 390fb9987d0SSujith 0, NULL)) 391fb9987d0SSujith common->splitmic = 1; 392fb9987d0SSujith 393fb9987d0SSujith /* turn on mcast key search if possible */ 394fb9987d0SSujith if (!ath9k_hw_getcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) 395fb9987d0SSujith (void)ath9k_hw_setcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 396fb9987d0SSujith 1, 1, NULL); 397fb9987d0SSujith } 398fb9987d0SSujith 399fb9987d0SSujith static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) 400fb9987d0SSujith { 401fb9987d0SSujith if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) { 402fb9987d0SSujith priv->sbands[IEEE80211_BAND_2GHZ].channels = 403fb9987d0SSujith ath9k_2ghz_channels; 404fb9987d0SSujith priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 405fb9987d0SSujith priv->sbands[IEEE80211_BAND_2GHZ].n_channels = 406fb9987d0SSujith ARRAY_SIZE(ath9k_2ghz_channels); 407fb9987d0SSujith priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 408fb9987d0SSujith priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 409fb9987d0SSujith ARRAY_SIZE(ath9k_legacy_rates); 410fb9987d0SSujith } 411fb9987d0SSujith } 412fb9987d0SSujith 413fb9987d0SSujith static void ath9k_init_misc(struct ath9k_htc_priv *priv) 414fb9987d0SSujith { 415fb9987d0SSujith struct ath_common *common = ath9k_hw_common(priv->ah); 416fb9987d0SSujith 417fb9987d0SSujith common->tx_chainmask = priv->ah->caps.tx_chainmask; 418fb9987d0SSujith common->rx_chainmask = priv->ah->caps.rx_chainmask; 419fb9987d0SSujith 420fb9987d0SSujith if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 421fb9987d0SSujith memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 422fb9987d0SSujith 423fb9987d0SSujith priv->op_flags |= OP_TXAGGR; 4249f01a84eSSujith priv->ah->opmode = NL80211_IFTYPE_STATION; 425fb9987d0SSujith } 426fb9987d0SSujith 427fb9987d0SSujith static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid) 428fb9987d0SSujith { 429fb9987d0SSujith struct ath_hw *ah = NULL; 430fb9987d0SSujith struct ath_common *common; 431fb9987d0SSujith int ret = 0, csz = 0; 432fb9987d0SSujith 433fb9987d0SSujith priv->op_flags |= OP_INVALID; 434fb9987d0SSujith 435fb9987d0SSujith ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 436fb9987d0SSujith if (!ah) 437fb9987d0SSujith return -ENOMEM; 438fb9987d0SSujith 439fb9987d0SSujith ah->hw_version.devid = devid; 440fb9987d0SSujith ah->hw_version.subsysid = 0; /* FIXME */ 441fb9987d0SSujith priv->ah = ah; 442fb9987d0SSujith 443fb9987d0SSujith common = ath9k_hw_common(ah); 444fb9987d0SSujith common->ops = &ath9k_common_ops; 445fb9987d0SSujith common->bus_ops = &ath9k_usb_bus_ops; 446fb9987d0SSujith common->ah = ah; 447fb9987d0SSujith common->hw = priv->hw; 448fb9987d0SSujith common->priv = priv; 449fb9987d0SSujith common->debug_mask = ath9k_debug; 450fb9987d0SSujith 451fb9987d0SSujith spin_lock_init(&priv->wmi->wmi_lock); 452fb9987d0SSujith spin_lock_init(&priv->beacon_lock); 4537757dfedSSujith spin_lock_init(&priv->tx_lock); 454fb9987d0SSujith mutex_init(&priv->mutex); 455fb9987d0SSujith mutex_init(&priv->aggr_work.mutex); 456fb9987d0SSujith tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet, 457fb9987d0SSujith (unsigned long)priv); 458fb9987d0SSujith tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, 459fb9987d0SSujith (unsigned long)priv); 460fb9987d0SSujith tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv); 461fb9987d0SSujith INIT_DELAYED_WORK(&priv->ath9k_aggr_work, ath9k_htc_aggr_work); 462fb9987d0SSujith INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work); 463fb9987d0SSujith 464fb9987d0SSujith /* 465fb9987d0SSujith * Cache line size is used to size and align various 466fb9987d0SSujith * structures used to communicate with the hardware. 467fb9987d0SSujith */ 468fb9987d0SSujith ath_read_cachesize(common, &csz); 469fb9987d0SSujith common->cachelsz = csz << 2; /* convert to bytes */ 470fb9987d0SSujith 471fb9987d0SSujith ret = ath9k_hw_init(ah); 472fb9987d0SSujith if (ret) { 473fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 474fb9987d0SSujith "Unable to initialize hardware; " 475fb9987d0SSujith "initialization status: %d\n", ret); 476fb9987d0SSujith goto err_hw; 477fb9987d0SSujith } 478fb9987d0SSujith 479e1572c5eSSujith ret = ath9k_htc_init_debug(ah); 480fb9987d0SSujith if (ret) { 481fb9987d0SSujith ath_print(common, ATH_DBG_FATAL, 482fb9987d0SSujith "Unable to create debugfs files\n"); 483fb9987d0SSujith goto err_debug; 484fb9987d0SSujith } 485fb9987d0SSujith 486fb9987d0SSujith ret = ath9k_init_queues(priv); 487fb9987d0SSujith if (ret) 488fb9987d0SSujith goto err_queues; 489fb9987d0SSujith 490fb9987d0SSujith ath9k_init_crypto(priv); 491fb9987d0SSujith ath9k_init_channels_rates(priv); 492fb9987d0SSujith ath9k_init_misc(priv); 493fb9987d0SSujith 494fb9987d0SSujith return 0; 495fb9987d0SSujith 496fb9987d0SSujith err_queues: 497e1572c5eSSujith ath9k_htc_exit_debug(ah); 498fb9987d0SSujith err_debug: 499fb9987d0SSujith ath9k_hw_deinit(ah); 500fb9987d0SSujith err_hw: 501fb9987d0SSujith 502fb9987d0SSujith kfree(ah); 503fb9987d0SSujith priv->ah = NULL; 504fb9987d0SSujith 505fb9987d0SSujith return ret; 506fb9987d0SSujith } 507fb9987d0SSujith 508fb9987d0SSujith static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, 509fb9987d0SSujith struct ieee80211_hw *hw) 510fb9987d0SSujith { 511fb9987d0SSujith struct ath_common *common = ath9k_hw_common(priv->ah); 512fb9987d0SSujith 513fb9987d0SSujith hw->flags = IEEE80211_HW_SIGNAL_DBM | 514fb9987d0SSujith IEEE80211_HW_AMPDU_AGGREGATION | 515fb9987d0SSujith IEEE80211_HW_SPECTRUM_MGMT | 51632fbccafSSujith IEEE80211_HW_HAS_RATE_CONTROL | 51732fbccafSSujith IEEE80211_HW_RX_INCLUDES_FCS; 518fb9987d0SSujith 519fb9987d0SSujith hw->wiphy->interface_modes = 520fb9987d0SSujith BIT(NL80211_IFTYPE_STATION) | 521fb9987d0SSujith BIT(NL80211_IFTYPE_ADHOC); 522fb9987d0SSujith 523fb9987d0SSujith hw->queues = 4; 524fb9987d0SSujith hw->channel_change_time = 5000; 525fb9987d0SSujith hw->max_listen_interval = 10; 526fb9987d0SSujith hw->vif_data_size = sizeof(struct ath9k_htc_vif); 527fb9987d0SSujith hw->sta_data_size = sizeof(struct ath9k_htc_sta); 528fb9987d0SSujith 529fb9987d0SSujith /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ 530fb9987d0SSujith hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + 531fb9987d0SSujith sizeof(struct htc_frame_hdr) + 4; 532fb9987d0SSujith 533fb9987d0SSujith if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 534fb9987d0SSujith hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 535fb9987d0SSujith &priv->sbands[IEEE80211_BAND_2GHZ]; 536fb9987d0SSujith 537fb9987d0SSujith if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 538fb9987d0SSujith if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 539fb9987d0SSujith setup_ht_cap(priv, 540fb9987d0SSujith &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); 541fb9987d0SSujith } 542fb9987d0SSujith 543fb9987d0SSujith SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 544fb9987d0SSujith } 545fb9987d0SSujith 546fb9987d0SSujith static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid) 547fb9987d0SSujith { 548fb9987d0SSujith struct ieee80211_hw *hw = priv->hw; 549fb9987d0SSujith struct ath_common *common; 550fb9987d0SSujith struct ath_hw *ah; 551fb9987d0SSujith int error = 0; 552fb9987d0SSujith struct ath_regulatory *reg; 553fb9987d0SSujith 554fb9987d0SSujith /* Bring up device */ 555fb9987d0SSujith error = ath9k_init_priv(priv, devid); 556fb9987d0SSujith if (error != 0) 557fb9987d0SSujith goto err_init; 558fb9987d0SSujith 559fb9987d0SSujith ah = priv->ah; 560fb9987d0SSujith common = ath9k_hw_common(ah); 561fb9987d0SSujith ath9k_set_hw_capab(priv, hw); 562fb9987d0SSujith 563fb9987d0SSujith /* Initialize regulatory */ 564fb9987d0SSujith error = ath_regd_init(&common->regulatory, priv->hw->wiphy, 565fb9987d0SSujith ath9k_reg_notifier); 566fb9987d0SSujith if (error) 567fb9987d0SSujith goto err_regd; 568fb9987d0SSujith 569fb9987d0SSujith reg = &common->regulatory; 570fb9987d0SSujith 571fb9987d0SSujith /* Setup TX */ 572fb9987d0SSujith error = ath9k_tx_init(priv); 573fb9987d0SSujith if (error != 0) 574fb9987d0SSujith goto err_tx; 575fb9987d0SSujith 576fb9987d0SSujith /* Setup RX */ 577fb9987d0SSujith error = ath9k_rx_init(priv); 578fb9987d0SSujith if (error != 0) 579fb9987d0SSujith goto err_rx; 580fb9987d0SSujith 581fb9987d0SSujith /* Register with mac80211 */ 582fb9987d0SSujith error = ieee80211_register_hw(hw); 583fb9987d0SSujith if (error) 584fb9987d0SSujith goto err_register; 585fb9987d0SSujith 586fb9987d0SSujith /* Handle world regulatory */ 587fb9987d0SSujith if (!ath_is_world_regd(reg)) { 588fb9987d0SSujith error = regulatory_hint(hw->wiphy, reg->alpha2); 589fb9987d0SSujith if (error) 590fb9987d0SSujith goto err_world; 591fb9987d0SSujith } 592fb9987d0SSujith 593fb9987d0SSujith ath9k_init_leds(priv); 594fb9987d0SSujith ath9k_start_rfkill_poll(priv); 595fb9987d0SSujith 596fb9987d0SSujith return 0; 597fb9987d0SSujith 598fb9987d0SSujith err_world: 599fb9987d0SSujith ieee80211_unregister_hw(hw); 600fb9987d0SSujith err_register: 601fb9987d0SSujith ath9k_rx_cleanup(priv); 602fb9987d0SSujith err_rx: 603fb9987d0SSujith ath9k_tx_cleanup(priv); 604fb9987d0SSujith err_tx: 605fb9987d0SSujith /* Nothing */ 606fb9987d0SSujith err_regd: 607fb9987d0SSujith ath9k_deinit_priv(priv); 608fb9987d0SSujith err_init: 609fb9987d0SSujith return error; 610fb9987d0SSujith } 611fb9987d0SSujith 612fb9987d0SSujith int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 613fb9987d0SSujith u16 devid) 614fb9987d0SSujith { 615fb9987d0SSujith struct ieee80211_hw *hw; 616fb9987d0SSujith struct ath9k_htc_priv *priv; 617fb9987d0SSujith int ret; 618fb9987d0SSujith 619fb9987d0SSujith hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); 620fb9987d0SSujith if (!hw) 621fb9987d0SSujith return -ENOMEM; 622fb9987d0SSujith 623fb9987d0SSujith priv = hw->priv; 624fb9987d0SSujith priv->hw = hw; 625fb9987d0SSujith priv->htc = htc_handle; 626fb9987d0SSujith priv->dev = dev; 627fb9987d0SSujith htc_handle->drv_priv = priv; 628fb9987d0SSujith SET_IEEE80211_DEV(hw, priv->dev); 629fb9987d0SSujith 630fb9987d0SSujith ret = ath9k_htc_wait_for_target(priv); 631fb9987d0SSujith if (ret) 632fb9987d0SSujith goto err_free; 633fb9987d0SSujith 634fb9987d0SSujith priv->wmi = ath9k_init_wmi(priv); 635fb9987d0SSujith if (!priv->wmi) { 636fb9987d0SSujith ret = -EINVAL; 637fb9987d0SSujith goto err_free; 638fb9987d0SSujith } 639fb9987d0SSujith 640fb9987d0SSujith ret = ath9k_init_htc_services(priv); 641fb9987d0SSujith if (ret) 642fb9987d0SSujith goto err_init; 643fb9987d0SSujith 644fb9987d0SSujith ret = ath9k_init_device(priv, devid); 645fb9987d0SSujith if (ret) 646fb9987d0SSujith goto err_init; 647fb9987d0SSujith 648fb9987d0SSujith return 0; 649fb9987d0SSujith 650fb9987d0SSujith err_init: 651fb9987d0SSujith ath9k_deinit_wmi(priv); 652fb9987d0SSujith err_free: 653fb9987d0SSujith ieee80211_free_hw(hw); 654fb9987d0SSujith return ret; 655fb9987d0SSujith } 656fb9987d0SSujith 657fb9987d0SSujith void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 658fb9987d0SSujith { 659fb9987d0SSujith if (htc_handle->drv_priv) { 660fb9987d0SSujith ath9k_deinit_device(htc_handle->drv_priv); 661fb9987d0SSujith ath9k_deinit_wmi(htc_handle->drv_priv); 662fb9987d0SSujith ieee80211_free_hw(htc_handle->drv_priv->hw); 663fb9987d0SSujith } 664fb9987d0SSujith } 665fb9987d0SSujith 666fb9987d0SSujith #ifdef CONFIG_PM 667fb9987d0SSujith int ath9k_htc_resume(struct htc_target *htc_handle) 668fb9987d0SSujith { 669fb9987d0SSujith int ret; 670fb9987d0SSujith 671fb9987d0SSujith ret = ath9k_htc_wait_for_target(htc_handle->drv_priv); 672fb9987d0SSujith if (ret) 673fb9987d0SSujith return ret; 674fb9987d0SSujith 675fb9987d0SSujith ret = ath9k_init_htc_services(htc_handle->drv_priv); 676fb9987d0SSujith return ret; 677fb9987d0SSujith } 678fb9987d0SSujith #endif 679fb9987d0SSujith 680fb9987d0SSujith static int __init ath9k_htc_init(void) 681fb9987d0SSujith { 682fb9987d0SSujith int error; 683fb9987d0SSujith 684e1572c5eSSujith error = ath9k_htc_debug_create_root(); 685fb9987d0SSujith if (error < 0) { 686fb9987d0SSujith printk(KERN_ERR 687fb9987d0SSujith "ath9k_htc: Unable to create debugfs root: %d\n", 688fb9987d0SSujith error); 689fb9987d0SSujith goto err_dbg; 690fb9987d0SSujith } 691fb9987d0SSujith 692fb9987d0SSujith error = ath9k_hif_usb_init(); 693fb9987d0SSujith if (error < 0) { 694fb9987d0SSujith printk(KERN_ERR 695fb9987d0SSujith "ath9k_htc: No USB devices found," 696fb9987d0SSujith " driver not installed.\n"); 697fb9987d0SSujith error = -ENODEV; 698fb9987d0SSujith goto err_usb; 699fb9987d0SSujith } 700fb9987d0SSujith 701fb9987d0SSujith return 0; 702fb9987d0SSujith 703fb9987d0SSujith err_usb: 704e1572c5eSSujith ath9k_htc_debug_remove_root(); 705fb9987d0SSujith err_dbg: 706fb9987d0SSujith return error; 707fb9987d0SSujith } 708fb9987d0SSujith module_init(ath9k_htc_init); 709fb9987d0SSujith 710fb9987d0SSujith static void __exit ath9k_htc_exit(void) 711fb9987d0SSujith { 712fb9987d0SSujith ath9k_hif_usb_exit(); 713e1572c5eSSujith ath9k_htc_debug_remove_root(); 714fb9987d0SSujith printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); 715fb9987d0SSujith } 716fb9987d0SSujith module_exit(ath9k_htc_exit); 717