1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9002_phy.h" 19 20 static void ath9k_get_txgain_index(struct ath_hw *ah, 21 struct ath9k_channel *chan, 22 struct calDataPerFreqOpLoop *rawDatasetOpLoop, 23 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx) 24 { 25 u8 pcdac, i = 0; 26 u16 idxL = 0, idxR = 0, numPiers; 27 bool match; 28 struct chan_centers centers; 29 30 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 31 32 for (numPiers = 0; numPiers < availPiers; numPiers++) 33 if (calChans[numPiers] == AR5416_BCHAN_UNUSED) 34 break; 35 36 match = ath9k_hw_get_lower_upper_index( 37 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), 38 calChans, numPiers, &idxL, &idxR); 39 if (match) { 40 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0]; 41 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0]; 42 } else { 43 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0]; 44 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] + 45 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2; 46 } 47 48 while (pcdac > ah->originalGain[i] && 49 i < (AR9280_TX_GAIN_TABLE_SIZE - 1)) 50 i++; 51 52 *pcdacIdx = i; 53 } 54 55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah, 56 u32 initTxGain, 57 int txPower, 58 u8 *pPDADCValues) 59 { 60 u32 i; 61 u32 offset; 62 63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, 64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, 66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 67 68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, 69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain); 70 71 offset = txPower; 72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++) 73 if (i < offset) 74 pPDADCValues[i] = 0x0; 75 else 76 pPDADCValues[i] = 0xFF; 77 } 78 79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) 80 { 81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF); 82 } 83 84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) 85 { 86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF); 87 } 88 89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) 90 { 91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 92 struct ath_common *common = ath9k_hw_common(ah); 93 u16 *eep_data = (u16 *)&ah->eeprom.def; 94 int addr, ar5416_eep_start_loc = 0x100; 95 96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc, 98 eep_data)) { 99 ath_err(ath9k_hw_common(ah), 100 "Unable to read eeprom region\n"); 101 return false; 102 } 103 eep_data++; 104 } 105 return true; 106 #undef SIZE_EEPROM_DEF 107 } 108 109 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) 110 { 111 struct ar5416_eeprom_def *eep = 112 (struct ar5416_eeprom_def *) &ah->eeprom.def; 113 struct ath_common *common = ath9k_hw_common(ah); 114 u16 *eepdata, temp, magic, magic2; 115 u32 sum = 0, el; 116 bool need_swap = false; 117 int i, addr, size; 118 119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 120 ath_err(common, "Reading Magic # failed\n"); 121 return false; 122 } 123 124 if (!ath9k_hw_use_flash(ah)) { 125 ath_dbg(common, ATH_DBG_EEPROM, 126 "Read Magic = 0x%04X\n", magic); 127 128 if (magic != AR5416_EEPROM_MAGIC) { 129 magic2 = swab16(magic); 130 131 if (magic2 == AR5416_EEPROM_MAGIC) { 132 size = sizeof(struct ar5416_eeprom_def); 133 need_swap = true; 134 eepdata = (u16 *) (&ah->eeprom); 135 136 for (addr = 0; addr < size / sizeof(u16); addr++) { 137 temp = swab16(*eepdata); 138 *eepdata = temp; 139 eepdata++; 140 } 141 } else { 142 ath_err(common, 143 "Invalid EEPROM Magic. Endianness mismatch.\n"); 144 return -EINVAL; 145 } 146 } 147 } 148 149 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 150 need_swap ? "True" : "False"); 151 152 if (need_swap) 153 el = swab16(ah->eeprom.def.baseEepHeader.length); 154 else 155 el = ah->eeprom.def.baseEepHeader.length; 156 157 if (el > sizeof(struct ar5416_eeprom_def)) 158 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); 159 else 160 el = el / sizeof(u16); 161 162 eepdata = (u16 *)(&ah->eeprom); 163 164 for (i = 0; i < el; i++) 165 sum ^= *eepdata++; 166 167 if (need_swap) { 168 u32 integer, j; 169 u16 word; 170 171 ath_dbg(common, ATH_DBG_EEPROM, 172 "EEPROM Endianness is not native.. Changing.\n"); 173 174 word = swab16(eep->baseEepHeader.length); 175 eep->baseEepHeader.length = word; 176 177 word = swab16(eep->baseEepHeader.checksum); 178 eep->baseEepHeader.checksum = word; 179 180 word = swab16(eep->baseEepHeader.version); 181 eep->baseEepHeader.version = word; 182 183 word = swab16(eep->baseEepHeader.regDmn[0]); 184 eep->baseEepHeader.regDmn[0] = word; 185 186 word = swab16(eep->baseEepHeader.regDmn[1]); 187 eep->baseEepHeader.regDmn[1] = word; 188 189 word = swab16(eep->baseEepHeader.rfSilent); 190 eep->baseEepHeader.rfSilent = word; 191 192 word = swab16(eep->baseEepHeader.blueToothOptions); 193 eep->baseEepHeader.blueToothOptions = word; 194 195 word = swab16(eep->baseEepHeader.deviceCap); 196 eep->baseEepHeader.deviceCap = word; 197 198 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { 199 struct modal_eep_header *pModal = 200 &eep->modalHeader[j]; 201 integer = swab32(pModal->antCtrlCommon); 202 pModal->antCtrlCommon = integer; 203 204 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 205 integer = swab32(pModal->antCtrlChain[i]); 206 pModal->antCtrlChain[i] = integer; 207 } 208 209 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 210 word = swab16(pModal->spurChans[i].spurChan); 211 pModal->spurChans[i].spurChan = word; 212 } 213 } 214 } 215 216 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 217 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 218 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 219 sum, ah->eep_ops->get_eeprom_ver(ah)); 220 return -EINVAL; 221 } 222 223 /* Enable fixup for AR_AN_TOP2 if necessary */ 224 if (AR_SREV_9280_20_OR_LATER(ah) && 225 (eep->baseEepHeader.version & 0xff) > 0x0a && 226 eep->baseEepHeader.pwdclkind == 0) 227 ah->need_an_top2_fixup = 1; 228 229 if ((common->bus_ops->ath_bus_type == ATH_USB) && 230 (AR_SREV_9280(ah))) 231 eep->modalHeader[0].xpaBiasLvl = 0; 232 233 return 0; 234 } 235 236 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, 237 enum eeprom_param param) 238 { 239 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 240 struct modal_eep_header *pModal = eep->modalHeader; 241 struct base_eep_header *pBase = &eep->baseEepHeader; 242 243 switch (param) { 244 case EEP_NFTHRESH_5: 245 return pModal[0].noiseFloorThreshCh[0]; 246 case EEP_NFTHRESH_2: 247 return pModal[1].noiseFloorThreshCh[0]; 248 case EEP_MAC_LSW: 249 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 250 case EEP_MAC_MID: 251 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 252 case EEP_MAC_MSW: 253 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 254 case EEP_REG_0: 255 return pBase->regDmn[0]; 256 case EEP_REG_1: 257 return pBase->regDmn[1]; 258 case EEP_OP_CAP: 259 return pBase->deviceCap; 260 case EEP_OP_MODE: 261 return pBase->opCapFlags; 262 case EEP_RF_SILENT: 263 return pBase->rfSilent; 264 case EEP_OB_5: 265 return pModal[0].ob; 266 case EEP_DB_5: 267 return pModal[0].db; 268 case EEP_OB_2: 269 return pModal[1].ob; 270 case EEP_DB_2: 271 return pModal[1].db; 272 case EEP_MINOR_REV: 273 return AR5416_VER_MASK; 274 case EEP_TX_MASK: 275 return pBase->txMask; 276 case EEP_RX_MASK: 277 return pBase->rxMask; 278 case EEP_FSTCLK_5G: 279 return pBase->fastClk5g; 280 case EEP_RXGAIN_TYPE: 281 return pBase->rxGainType; 282 case EEP_TXGAIN_TYPE: 283 return pBase->txGainType; 284 case EEP_OL_PWRCTRL: 285 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) 286 return pBase->openLoopPwrCntl ? true : false; 287 else 288 return false; 289 case EEP_RC_CHAIN_MASK: 290 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) 291 return pBase->rcChainMask; 292 else 293 return 0; 294 case EEP_DAC_HPWR_5G: 295 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) 296 return pBase->dacHiPwrMode_5G; 297 else 298 return 0; 299 case EEP_FRAC_N_5G: 300 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22) 301 return pBase->frac_n_5g; 302 else 303 return 0; 304 case EEP_PWR_TABLE_OFFSET: 305 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21) 306 return pBase->pwr_table_offset; 307 else 308 return AR5416_PWR_TABLE_OFFSET_DB; 309 default: 310 return 0; 311 } 312 } 313 314 static void ath9k_hw_def_set_gain(struct ath_hw *ah, 315 struct modal_eep_header *pModal, 316 struct ar5416_eeprom_def *eep, 317 u8 txRxAttenLocal, int regChainOffset, int i) 318 { 319 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { 320 txRxAttenLocal = pModal->txRxAttenCh[i]; 321 322 if (AR_SREV_9280_20_OR_LATER(ah)) { 323 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 324 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 325 pModal->bswMargin[i]); 326 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 327 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 328 pModal->bswAtten[i]); 329 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 330 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 331 pModal->xatten2Margin[i]); 332 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 333 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 334 pModal->xatten2Db[i]); 335 } else { 336 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 337 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 338 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) 339 | SM(pModal-> bswMargin[i], 340 AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 341 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 342 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 343 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) 344 | SM(pModal->bswAtten[i], 345 AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 346 } 347 } 348 349 if (AR_SREV_9280_20_OR_LATER(ah)) { 350 REG_RMW_FIELD(ah, 351 AR_PHY_RXGAIN + regChainOffset, 352 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 353 REG_RMW_FIELD(ah, 354 AR_PHY_RXGAIN + regChainOffset, 355 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); 356 } else { 357 REG_WRITE(ah, 358 AR_PHY_RXGAIN + regChainOffset, 359 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & 360 ~AR_PHY_RXGAIN_TXRX_ATTEN) 361 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN)); 362 REG_WRITE(ah, 363 AR_PHY_GAIN_2GHZ + regChainOffset, 364 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & 365 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | 366 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); 367 } 368 } 369 370 static void ath9k_hw_def_set_board_values(struct ath_hw *ah, 371 struct ath9k_channel *chan) 372 { 373 struct modal_eep_header *pModal; 374 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 375 int i, regChainOffset; 376 u8 txRxAttenLocal; 377 378 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 379 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 380 381 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff); 382 383 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 384 if (AR_SREV_9280(ah)) { 385 if (i >= 2) 386 break; 387 } 388 389 if (AR_SREV_5416_20_OR_LATER(ah) && 390 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) 391 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 392 else 393 regChainOffset = i * 0x1000; 394 395 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 396 pModal->antCtrlChain[i]); 397 398 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 399 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & 400 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 401 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 402 SM(pModal->iqCalICh[i], 403 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 404 SM(pModal->iqCalQCh[i], 405 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 406 407 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) 408 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal, 409 regChainOffset, i); 410 } 411 412 if (AR_SREV_9280_20_OR_LATER(ah)) { 413 if (IS_CHAN_2GHZ(chan)) { 414 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, 415 AR_AN_RF2G1_CH0_OB, 416 AR_AN_RF2G1_CH0_OB_S, 417 pModal->ob); 418 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, 419 AR_AN_RF2G1_CH0_DB, 420 AR_AN_RF2G1_CH0_DB_S, 421 pModal->db); 422 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, 423 AR_AN_RF2G1_CH1_OB, 424 AR_AN_RF2G1_CH1_OB_S, 425 pModal->ob_ch1); 426 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, 427 AR_AN_RF2G1_CH1_DB, 428 AR_AN_RF2G1_CH1_DB_S, 429 pModal->db_ch1); 430 } else { 431 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, 432 AR_AN_RF5G1_CH0_OB5, 433 AR_AN_RF5G1_CH0_OB5_S, 434 pModal->ob); 435 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, 436 AR_AN_RF5G1_CH0_DB5, 437 AR_AN_RF5G1_CH0_DB5_S, 438 pModal->db); 439 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, 440 AR_AN_RF5G1_CH1_OB5, 441 AR_AN_RF5G1_CH1_OB5_S, 442 pModal->ob_ch1); 443 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, 444 AR_AN_RF5G1_CH1_DB5, 445 AR_AN_RF5G1_CH1_DB5_S, 446 pModal->db_ch1); 447 } 448 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, 449 AR_AN_TOP2_XPABIAS_LVL, 450 AR_AN_TOP2_XPABIAS_LVL_S, 451 pModal->xpaBiasLvl); 452 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, 453 AR_AN_TOP2_LOCALBIAS, 454 AR_AN_TOP2_LOCALBIAS_S, 455 !!(pModal->lna_ctl & 456 LNA_CTL_LOCAL_BIAS)); 457 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, 458 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA)); 459 } 460 461 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 462 pModal->switchSettling); 463 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 464 pModal->adcDesiredSize); 465 466 if (!AR_SREV_9280_20_OR_LATER(ah)) 467 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 468 AR_PHY_DESIRED_SZ_PGA, 469 pModal->pgaDesiredSize); 470 471 REG_WRITE(ah, AR_PHY_RF_CTL4, 472 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 473 | SM(pModal->txEndToXpaOff, 474 AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 475 | SM(pModal->txFrameToXpaOn, 476 AR_PHY_RF_CTL4_FRAME_XPAA_ON) 477 | SM(pModal->txFrameToXpaOn, 478 AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 479 480 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 481 pModal->txEndToRxOn); 482 483 if (AR_SREV_9280_20_OR_LATER(ah)) { 484 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 485 pModal->thresh62); 486 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, 487 AR_PHY_EXT_CCA0_THRESH62, 488 pModal->thresh62); 489 } else { 490 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 491 pModal->thresh62); 492 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 493 AR_PHY_EXT_CCA_THRESH62, 494 pModal->thresh62); 495 } 496 497 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { 498 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 499 AR_PHY_TX_END_DATA_START, 500 pModal->txFrameToDataStart); 501 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, 502 pModal->txFrameToPaOn); 503 } 504 505 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { 506 if (IS_CHAN_HT40(chan)) 507 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 508 AR_PHY_SETTLING_SWITCH, 509 pModal->swSettleHt40); 510 } 511 512 if (AR_SREV_9280_20_OR_LATER(ah) && 513 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) 514 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, 515 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, 516 pModal->miscBits); 517 518 519 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { 520 if (IS_CHAN_2GHZ(chan)) 521 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 522 eep->baseEepHeader.dacLpMode); 523 else if (eep->baseEepHeader.dacHiPwrMode_5G) 524 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 525 else 526 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 527 eep->baseEepHeader.dacLpMode); 528 529 udelay(100); 530 531 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, 532 pModal->miscBits >> 2); 533 534 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, 535 AR_PHY_TX_DESIRED_SCALE_CCK, 536 eep->baseEepHeader.desiredScaleCCK); 537 } 538 } 539 540 static void ath9k_hw_def_set_addac(struct ath_hw *ah, 541 struct ath9k_channel *chan) 542 { 543 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 544 struct modal_eep_header *pModal; 545 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 546 u8 biaslevel; 547 548 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) 549 return; 550 551 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) 552 return; 553 554 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 555 556 if (pModal->xpaBiasLvl != 0xff) { 557 biaslevel = pModal->xpaBiasLvl; 558 } else { 559 u16 resetFreqBin, freqBin, freqCount = 0; 560 struct chan_centers centers; 561 562 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 563 564 resetFreqBin = FREQ2FBIN(centers.synth_center, 565 IS_CHAN_2GHZ(chan)); 566 freqBin = XPA_LVL_FREQ(0) & 0xff; 567 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14); 568 569 freqCount++; 570 571 while (freqCount < 3) { 572 if (XPA_LVL_FREQ(freqCount) == 0x0) 573 break; 574 575 freqBin = XPA_LVL_FREQ(freqCount) & 0xff; 576 if (resetFreqBin >= freqBin) 577 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); 578 else 579 break; 580 freqCount++; 581 } 582 } 583 584 if (IS_CHAN_2GHZ(chan)) { 585 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac, 586 7, 1) & (~0x18)) | biaslevel << 3; 587 } else { 588 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac, 589 6, 1) & (~0xc0)) | biaslevel << 6; 590 } 591 #undef XPA_LVL_FREQ 592 } 593 594 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, 595 u16 *gb, 596 u16 numXpdGain, 597 u16 pdGainOverlap_t2, 598 int8_t pwr_table_offset, 599 int16_t *diff) 600 601 { 602 u16 k; 603 604 /* Prior to writing the boundaries or the pdadc vs. power table 605 * into the chip registers the default starting point on the pdadc 606 * vs. power table needs to be checked and the curve boundaries 607 * adjusted accordingly 608 */ 609 if (AR_SREV_9280_20_OR_LATER(ah)) { 610 u16 gb_limit; 611 612 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) { 613 /* get the difference in dB */ 614 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB); 615 /* get the number of half dB steps */ 616 *diff *= 2; 617 /* change the original gain boundary settings 618 * by the number of half dB steps 619 */ 620 for (k = 0; k < numXpdGain; k++) 621 gb[k] = (u16)(gb[k] - *diff); 622 } 623 /* Because of a hardware limitation, ensure the gain boundary 624 * is not larger than (63 - overlap) 625 */ 626 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2); 627 628 for (k = 0; k < numXpdGain; k++) 629 gb[k] = (u16)min(gb_limit, gb[k]); 630 } 631 632 return *diff; 633 } 634 635 static void ath9k_adjust_pdadc_values(struct ath_hw *ah, 636 int8_t pwr_table_offset, 637 int16_t diff, 638 u8 *pdadcValues) 639 { 640 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff) 641 u16 k; 642 643 /* If this is a board that has a pwrTableOffset that differs from 644 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the 645 * pdadc vs pwr table needs to be adjusted prior to writing to the 646 * chip. 647 */ 648 if (AR_SREV_9280_20_OR_LATER(ah)) { 649 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) { 650 /* shift the table to start at the new offset */ 651 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) { 652 pdadcValues[k] = pdadcValues[k + diff]; 653 } 654 655 /* fill the back of the table */ 656 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) { 657 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)]; 658 } 659 } 660 } 661 #undef NUM_PDADC 662 } 663 664 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 665 struct ath9k_channel *chan, 666 int16_t *pTxPowerIndexOffset) 667 { 668 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) 669 #define SM_PDGAIN_B(x, y) \ 670 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) 671 struct ath_common *common = ath9k_hw_common(ah); 672 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 673 struct cal_data_per_freq *pRawDataset; 674 u8 *pCalBChans = NULL; 675 u16 pdGainOverlap_t2; 676 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 677 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 678 u16 numPiers, i, j; 679 int16_t diff = 0; 680 u16 numXpdGain, xpdMask; 681 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; 682 u32 reg32, regOffset, regChainOffset; 683 int16_t modalIdx; 684 int8_t pwr_table_offset; 685 686 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 687 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 688 689 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET); 690 691 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 692 AR5416_EEP_MINOR_VER_2) { 693 pdGainOverlap_t2 = 694 pEepData->modalHeader[modalIdx].pdGainOverlap; 695 } else { 696 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 697 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 698 } 699 700 if (IS_CHAN_2GHZ(chan)) { 701 pCalBChans = pEepData->calFreqPier2G; 702 numPiers = AR5416_NUM_2G_CAL_PIERS; 703 } else { 704 pCalBChans = pEepData->calFreqPier5G; 705 numPiers = AR5416_NUM_5G_CAL_PIERS; 706 } 707 708 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) { 709 pRawDataset = pEepData->calPierData2G[0]; 710 ah->initPDADC = ((struct calDataPerFreqOpLoop *) 711 pRawDataset)->vpdPdg[0][0]; 712 } 713 714 numXpdGain = 0; 715 716 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 717 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 718 if (numXpdGain >= AR5416_NUM_PD_GAINS) 719 break; 720 xpdGainValues[numXpdGain] = 721 (u16)(AR5416_PD_GAINS_IN_MASK - i); 722 numXpdGain++; 723 } 724 } 725 726 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 727 (numXpdGain - 1) & 0x3); 728 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 729 xpdGainValues[0]); 730 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 731 xpdGainValues[1]); 732 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 733 xpdGainValues[2]); 734 735 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 736 if (AR_SREV_5416_20_OR_LATER(ah) && 737 (ah->rxchainmask == 5 || ah->txchainmask == 5) && 738 (i != 0)) { 739 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 740 } else 741 regChainOffset = i * 0x1000; 742 743 if (pEepData->baseEepHeader.txMask & (1 << i)) { 744 if (IS_CHAN_2GHZ(chan)) 745 pRawDataset = pEepData->calPierData2G[i]; 746 else 747 pRawDataset = pEepData->calPierData5G[i]; 748 749 750 if (OLC_FOR_AR9280_20_LATER) { 751 u8 pcdacIdx; 752 u8 txPower; 753 754 ath9k_get_txgain_index(ah, chan, 755 (struct calDataPerFreqOpLoop *)pRawDataset, 756 pCalBChans, numPiers, &txPower, &pcdacIdx); 757 ath9k_olc_get_pdadcs(ah, pcdacIdx, 758 txPower/2, pdadcValues); 759 } else { 760 ath9k_hw_get_gain_boundaries_pdadcs(ah, 761 chan, pRawDataset, 762 pCalBChans, numPiers, 763 pdGainOverlap_t2, 764 gainBoundaries, 765 pdadcValues, 766 numXpdGain); 767 } 768 769 diff = ath9k_change_gain_boundary_setting(ah, 770 gainBoundaries, 771 numXpdGain, 772 pdGainOverlap_t2, 773 pwr_table_offset, 774 &diff); 775 776 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 777 if (OLC_FOR_AR9280_20_LATER) { 778 REG_WRITE(ah, 779 AR_PHY_TPCRG5 + regChainOffset, 780 SM(0x6, 781 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 782 SM_PD_GAIN(1) | SM_PD_GAIN(2) | 783 SM_PD_GAIN(3) | SM_PD_GAIN(4)); 784 } else { 785 REG_WRITE(ah, 786 AR_PHY_TPCRG5 + regChainOffset, 787 SM(pdGainOverlap_t2, 788 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)| 789 SM_PDGAIN_B(0, 1) | 790 SM_PDGAIN_B(1, 2) | 791 SM_PDGAIN_B(2, 3) | 792 SM_PDGAIN_B(3, 4)); 793 } 794 } 795 796 797 ath9k_adjust_pdadc_values(ah, pwr_table_offset, 798 diff, pdadcValues); 799 800 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 801 for (j = 0; j < 32; j++) { 802 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 803 ((pdadcValues[4 * j + 1] & 0xFF) << 8) | 804 ((pdadcValues[4 * j + 2] & 0xFF) << 16)| 805 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 806 REG_WRITE(ah, regOffset, reg32); 807 808 ath_dbg(common, ATH_DBG_EEPROM, 809 "PDADC (%d,%4x): %4.4x %8.8x\n", 810 i, regChainOffset, regOffset, 811 reg32); 812 ath_dbg(common, ATH_DBG_EEPROM, 813 "PDADC: Chain %d | PDADC %3d " 814 "Value %3d | PDADC %3d Value %3d | " 815 "PDADC %3d Value %3d | PDADC %3d " 816 "Value %3d |\n", 817 i, 4 * j, pdadcValues[4 * j], 818 4 * j + 1, pdadcValues[4 * j + 1], 819 4 * j + 2, pdadcValues[4 * j + 2], 820 4 * j + 3, pdadcValues[4 * j + 3]); 821 822 regOffset += 4; 823 } 824 } 825 } 826 827 *pTxPowerIndexOffset = 0; 828 #undef SM_PD_GAIN 829 #undef SM_PDGAIN_B 830 } 831 832 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, 833 struct ath9k_channel *chan, 834 int16_t *ratesArray, 835 u16 cfgCtl, 836 u16 AntennaReduction, 837 u16 twiceMaxRegulatoryPower, 838 u16 powerLimit) 839 { 840 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 841 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ 842 843 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 844 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 845 u16 twiceMaxEdgePower = MAX_RATE_POWER; 846 static const u16 tpScaleReductionTable[5] = 847 { 0, 3, 6, 9, MAX_RATE_POWER }; 848 849 int i; 850 int16_t twiceLargestAntenna; 851 struct cal_ctl_data *rep; 852 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 853 0, { 0, 0, 0, 0} 854 }; 855 struct cal_target_power_leg targetPowerOfdmExt = { 856 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 857 0, { 0, 0, 0, 0 } 858 }; 859 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 860 0, {0, 0, 0, 0} 861 }; 862 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 863 static const u16 ctlModesFor11a[] = { 864 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 865 }; 866 static const u16 ctlModesFor11g[] = { 867 CTL_11B, CTL_11G, CTL_2GHT20, 868 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 869 }; 870 u16 numCtlModes; 871 const u16 *pCtlMode; 872 u16 ctlMode, freq; 873 struct chan_centers centers; 874 int tx_chainmask; 875 u16 twiceMinEdgePower; 876 877 tx_chainmask = ah->txchainmask; 878 879 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 880 881 twiceLargestAntenna = max( 882 pEepData->modalHeader 883 [IS_CHAN_2GHZ(chan)].antennaGainCh[0], 884 pEepData->modalHeader 885 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 886 887 twiceLargestAntenna = max((u8)twiceLargestAntenna, 888 pEepData->modalHeader 889 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 890 891 twiceLargestAntenna = (int16_t)min(AntennaReduction - 892 twiceLargestAntenna, 0); 893 894 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 895 896 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) { 897 maxRegAllowedPower -= 898 (tpScaleReductionTable[(regulatory->tp_scale)] * 2); 899 } 900 901 scaledPower = min(powerLimit, maxRegAllowedPower); 902 903 switch (ar5416_get_ntxchains(tx_chainmask)) { 904 case 1: 905 break; 906 case 2: 907 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN) 908 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; 909 else 910 scaledPower = 0; 911 break; 912 case 3: 913 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN) 914 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; 915 else 916 scaledPower = 0; 917 break; 918 } 919 920 if (IS_CHAN_2GHZ(chan)) { 921 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - 922 SUB_NUM_CTL_MODES_AT_2G_40; 923 pCtlMode = ctlModesFor11g; 924 925 ath9k_hw_get_legacy_target_powers(ah, chan, 926 pEepData->calTargetPowerCck, 927 AR5416_NUM_2G_CCK_TARGET_POWERS, 928 &targetPowerCck, 4, false); 929 ath9k_hw_get_legacy_target_powers(ah, chan, 930 pEepData->calTargetPower2G, 931 AR5416_NUM_2G_20_TARGET_POWERS, 932 &targetPowerOfdm, 4, false); 933 ath9k_hw_get_target_powers(ah, chan, 934 pEepData->calTargetPower2GHT20, 935 AR5416_NUM_2G_20_TARGET_POWERS, 936 &targetPowerHt20, 8, false); 937 938 if (IS_CHAN_HT40(chan)) { 939 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 940 ath9k_hw_get_target_powers(ah, chan, 941 pEepData->calTargetPower2GHT40, 942 AR5416_NUM_2G_40_TARGET_POWERS, 943 &targetPowerHt40, 8, true); 944 ath9k_hw_get_legacy_target_powers(ah, chan, 945 pEepData->calTargetPowerCck, 946 AR5416_NUM_2G_CCK_TARGET_POWERS, 947 &targetPowerCckExt, 4, true); 948 ath9k_hw_get_legacy_target_powers(ah, chan, 949 pEepData->calTargetPower2G, 950 AR5416_NUM_2G_20_TARGET_POWERS, 951 &targetPowerOfdmExt, 4, true); 952 } 953 } else { 954 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - 955 SUB_NUM_CTL_MODES_AT_5G_40; 956 pCtlMode = ctlModesFor11a; 957 958 ath9k_hw_get_legacy_target_powers(ah, chan, 959 pEepData->calTargetPower5G, 960 AR5416_NUM_5G_20_TARGET_POWERS, 961 &targetPowerOfdm, 4, false); 962 ath9k_hw_get_target_powers(ah, chan, 963 pEepData->calTargetPower5GHT20, 964 AR5416_NUM_5G_20_TARGET_POWERS, 965 &targetPowerHt20, 8, false); 966 967 if (IS_CHAN_HT40(chan)) { 968 numCtlModes = ARRAY_SIZE(ctlModesFor11a); 969 ath9k_hw_get_target_powers(ah, chan, 970 pEepData->calTargetPower5GHT40, 971 AR5416_NUM_5G_40_TARGET_POWERS, 972 &targetPowerHt40, 8, true); 973 ath9k_hw_get_legacy_target_powers(ah, chan, 974 pEepData->calTargetPower5G, 975 AR5416_NUM_5G_20_TARGET_POWERS, 976 &targetPowerOfdmExt, 4, true); 977 } 978 } 979 980 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 981 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 982 (pCtlMode[ctlMode] == CTL_2GHT40); 983 if (isHt40CtlMode) 984 freq = centers.synth_center; 985 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 986 freq = centers.ext_center; 987 else 988 freq = centers.ctl_center; 989 990 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 991 ah->eep_ops->get_eeprom_rev(ah) <= 2) 992 twiceMaxEdgePower = MAX_RATE_POWER; 993 994 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 995 if ((((cfgCtl & ~CTL_MODE_M) | 996 (pCtlMode[ctlMode] & CTL_MODE_M)) == 997 pEepData->ctlIndex[i]) || 998 (((cfgCtl & ~CTL_MODE_M) | 999 (pCtlMode[ctlMode] & CTL_MODE_M)) == 1000 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1001 rep = &(pEepData->ctlData[i]); 1002 1003 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, 1004 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], 1005 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); 1006 1007 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1008 twiceMaxEdgePower = min(twiceMaxEdgePower, 1009 twiceMinEdgePower); 1010 } else { 1011 twiceMaxEdgePower = twiceMinEdgePower; 1012 break; 1013 } 1014 } 1015 } 1016 1017 minCtlPower = min(twiceMaxEdgePower, scaledPower); 1018 1019 switch (pCtlMode[ctlMode]) { 1020 case CTL_11B: 1021 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 1022 targetPowerCck.tPow2x[i] = 1023 min((u16)targetPowerCck.tPow2x[i], 1024 minCtlPower); 1025 } 1026 break; 1027 case CTL_11A: 1028 case CTL_11G: 1029 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 1030 targetPowerOfdm.tPow2x[i] = 1031 min((u16)targetPowerOfdm.tPow2x[i], 1032 minCtlPower); 1033 } 1034 break; 1035 case CTL_5GHT20: 1036 case CTL_2GHT20: 1037 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 1038 targetPowerHt20.tPow2x[i] = 1039 min((u16)targetPowerHt20.tPow2x[i], 1040 minCtlPower); 1041 } 1042 break; 1043 case CTL_11B_EXT: 1044 targetPowerCckExt.tPow2x[0] = min((u16) 1045 targetPowerCckExt.tPow2x[0], 1046 minCtlPower); 1047 break; 1048 case CTL_11A_EXT: 1049 case CTL_11G_EXT: 1050 targetPowerOfdmExt.tPow2x[0] = min((u16) 1051 targetPowerOfdmExt.tPow2x[0], 1052 minCtlPower); 1053 break; 1054 case CTL_5GHT40: 1055 case CTL_2GHT40: 1056 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 1057 targetPowerHt40.tPow2x[i] = 1058 min((u16)targetPowerHt40.tPow2x[i], 1059 minCtlPower); 1060 } 1061 break; 1062 default: 1063 break; 1064 } 1065 } 1066 1067 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1068 ratesArray[rate18mb] = ratesArray[rate24mb] = 1069 targetPowerOfdm.tPow2x[0]; 1070 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 1071 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 1072 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 1073 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 1074 1075 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 1076 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 1077 1078 if (IS_CHAN_2GHZ(chan)) { 1079 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 1080 ratesArray[rate2s] = ratesArray[rate2l] = 1081 targetPowerCck.tPow2x[1]; 1082 ratesArray[rate5_5s] = ratesArray[rate5_5l] = 1083 targetPowerCck.tPow2x[2]; 1084 ratesArray[rate11s] = ratesArray[rate11l] = 1085 targetPowerCck.tPow2x[3]; 1086 } 1087 if (IS_CHAN_HT40(chan)) { 1088 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 1089 ratesArray[rateHt40_0 + i] = 1090 targetPowerHt40.tPow2x[i]; 1091 } 1092 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 1093 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 1094 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 1095 if (IS_CHAN_2GHZ(chan)) { 1096 ratesArray[rateExtCck] = 1097 targetPowerCckExt.tPow2x[0]; 1098 } 1099 } 1100 } 1101 1102 static void ath9k_hw_def_set_txpower(struct ath_hw *ah, 1103 struct ath9k_channel *chan, 1104 u16 cfgCtl, 1105 u8 twiceAntennaReduction, 1106 u8 twiceMaxRegulatoryPower, 1107 u8 powerLimit, bool test) 1108 { 1109 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) 1110 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1111 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 1112 struct modal_eep_header *pModal = 1113 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); 1114 int16_t ratesArray[Ar5416RateSize]; 1115 int16_t txPowerIndexOffset = 0; 1116 u8 ht40PowerIncForPdadc = 2; 1117 int i, cck_ofdm_delta = 0; 1118 1119 memset(ratesArray, 0, sizeof(ratesArray)); 1120 1121 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1122 AR5416_EEP_MINOR_VER_2) { 1123 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1124 } 1125 1126 ath9k_hw_set_def_power_per_rate_table(ah, chan, 1127 &ratesArray[0], cfgCtl, 1128 twiceAntennaReduction, 1129 twiceMaxRegulatoryPower, 1130 powerLimit); 1131 1132 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset); 1133 1134 regulatory->max_power_level = 0; 1135 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1136 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1137 if (ratesArray[i] > MAX_RATE_POWER) 1138 ratesArray[i] = MAX_RATE_POWER; 1139 if (ratesArray[i] > regulatory->max_power_level) 1140 regulatory->max_power_level = ratesArray[i]; 1141 } 1142 1143 if (!test) { 1144 i = rate6mb; 1145 1146 if (IS_CHAN_HT40(chan)) 1147 i = rateHt40_0; 1148 else if (IS_CHAN_HT20(chan)) 1149 i = rateHt20_0; 1150 1151 regulatory->max_power_level = ratesArray[i]; 1152 } 1153 1154 switch(ar5416_get_ntxchains(ah->txchainmask)) { 1155 case 1: 1156 break; 1157 case 2: 1158 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; 1159 break; 1160 case 3: 1161 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1162 break; 1163 default: 1164 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM, 1165 "Invalid chainmask configuration\n"); 1166 break; 1167 } 1168 1169 if (test) 1170 return; 1171 1172 if (AR_SREV_9280_20_OR_LATER(ah)) { 1173 for (i = 0; i < Ar5416RateSize; i++) { 1174 int8_t pwr_table_offset; 1175 1176 pwr_table_offset = ah->eep_ops->get_eeprom(ah, 1177 EEP_PWR_TABLE_OFFSET); 1178 ratesArray[i] -= pwr_table_offset * 2; 1179 } 1180 } 1181 1182 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1183 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1184 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 1185 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 1186 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 1187 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1188 ATH9K_POW_SM(ratesArray[rate54mb], 24) 1189 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 1190 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 1191 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 1192 1193 if (IS_CHAN_2GHZ(chan)) { 1194 if (OLC_FOR_AR9280_20_LATER) { 1195 cck_ofdm_delta = 2; 1196 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1197 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24) 1198 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16) 1199 | ATH9K_POW_SM(ratesArray[rateXr], 8) 1200 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0)); 1201 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 1202 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24) 1203 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16) 1204 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8) 1205 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0)); 1206 } else { 1207 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1208 ATH9K_POW_SM(ratesArray[rate2s], 24) 1209 | ATH9K_POW_SM(ratesArray[rate2l], 16) 1210 | ATH9K_POW_SM(ratesArray[rateXr], 8) 1211 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 1212 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 1213 ATH9K_POW_SM(ratesArray[rate11s], 24) 1214 | ATH9K_POW_SM(ratesArray[rate11l], 16) 1215 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 1216 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 1217 } 1218 } 1219 1220 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1221 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 1222 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 1223 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 1224 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 1225 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 1226 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 1227 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 1228 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 1229 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 1230 1231 if (IS_CHAN_HT40(chan)) { 1232 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1233 ATH9K_POW_SM(ratesArray[rateHt40_3] + 1234 ht40PowerIncForPdadc, 24) 1235 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 1236 ht40PowerIncForPdadc, 16) 1237 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 1238 ht40PowerIncForPdadc, 8) 1239 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 1240 ht40PowerIncForPdadc, 0)); 1241 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 1242 ATH9K_POW_SM(ratesArray[rateHt40_7] + 1243 ht40PowerIncForPdadc, 24) 1244 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 1245 ht40PowerIncForPdadc, 16) 1246 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 1247 ht40PowerIncForPdadc, 8) 1248 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 1249 ht40PowerIncForPdadc, 0)); 1250 if (OLC_FOR_AR9280_20_LATER) { 1251 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 1252 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 1253 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16) 1254 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 1255 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0)); 1256 } else { 1257 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 1258 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 1259 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 1260 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 1261 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 1262 } 1263 } 1264 1265 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1266 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1267 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); 1268 } 1269 1270 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1271 { 1272 #define EEP_DEF_SPURCHAN \ 1273 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 1274 struct ath_common *common = ath9k_hw_common(ah); 1275 1276 u16 spur_val = AR_NO_SPUR; 1277 1278 ath_dbg(common, ATH_DBG_ANI, 1279 "Getting spur idx:%d is2Ghz:%d val:%x\n", 1280 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1281 1282 switch (ah->config.spurmode) { 1283 case SPUR_DISABLE: 1284 break; 1285 case SPUR_ENABLE_IOCTL: 1286 spur_val = ah->config.spurchans[i][is2GHz]; 1287 ath_dbg(common, ATH_DBG_ANI, 1288 "Getting spur val from new loc. %d\n", spur_val); 1289 break; 1290 case SPUR_ENABLE_EEPROM: 1291 spur_val = EEP_DEF_SPURCHAN; 1292 break; 1293 } 1294 1295 return spur_val; 1296 1297 #undef EEP_DEF_SPURCHAN 1298 } 1299 1300 const struct eeprom_ops eep_def_ops = { 1301 .check_eeprom = ath9k_hw_def_check_eeprom, 1302 .get_eeprom = ath9k_hw_def_get_eeprom, 1303 .fill_eeprom = ath9k_hw_def_fill_eeprom, 1304 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver, 1305 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev, 1306 .set_board_values = ath9k_hw_def_set_board_values, 1307 .set_addac = ath9k_hw_def_set_addac, 1308 .set_txpower = ath9k_hw_def_set_txpower, 1309 .get_spur_channel = ath9k_hw_def_get_spur_channel 1310 }; 1311