1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <asm/unaligned.h> 18 #include "hw.h" 19 #include "ar9002_phy.h" 20 21 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16)) 22 23 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah) 24 { 25 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF; 26 } 27 28 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah) 29 { 30 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF; 31 } 32 33 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) 34 { 35 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 36 struct ath_common *common = ath9k_hw_common(ah); 37 u16 *eep_data; 38 int addr, eep_start_loc = AR9287_EEP_START_LOC; 39 eep_data = (u16 *)eep; 40 41 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { 42 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, 43 eep_data)) { 44 ath_dbg(common, EEPROM, 45 "Unable to read eeprom region\n"); 46 return false; 47 } 48 eep_data++; 49 } 50 51 return true; 52 } 53 54 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah) 55 { 56 u16 *eep_data = (u16 *)&ah->eeprom.map9287; 57 58 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 59 AR9287_HTC_EEP_START_LOC, 60 SIZE_EEPROM_AR9287); 61 return true; 62 } 63 64 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) 65 { 66 struct ath_common *common = ath9k_hw_common(ah); 67 68 if (!ath9k_hw_use_flash(ah)) { 69 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n"); 70 } 71 72 if (common->bus_ops->ath_bus_type == ATH_USB) 73 return __ath9k_hw_usb_ar9287_fill_eeprom(ah); 74 else 75 return __ath9k_hw_ar9287_fill_eeprom(ah); 76 } 77 78 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) 79 static u32 ar9287_dump_modal_eeprom(char *buf, u32 len, u32 size, 80 struct modal_eep_ar9287_header *modal_hdr) 81 { 82 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]); 83 PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]); 84 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon); 85 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); 86 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]); 87 PR_EEP("Switch Settle", modal_hdr->switchSettling); 88 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); 89 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]); 90 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); 91 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]); 92 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); 93 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); 94 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); 95 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); 96 PR_EEP("CCA Threshold)", modal_hdr->thresh62); 97 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); 98 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); 99 PR_EEP("xpdGain", modal_hdr->xpdGain); 100 PR_EEP("External PD", modal_hdr->xpd); 101 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); 102 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]); 103 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); 104 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]); 105 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); 106 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); 107 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); 108 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); 109 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); 110 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); 111 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]); 112 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); 113 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]); 114 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); 115 PR_EEP("AR92x7 Version", modal_hdr->version); 116 PR_EEP("DriverBias1", modal_hdr->db1); 117 PR_EEP("DriverBias2", modal_hdr->db1); 118 PR_EEP("CCK OutputBias", modal_hdr->ob_cck); 119 PR_EEP("PSK OutputBias", modal_hdr->ob_psk); 120 PR_EEP("QAM OutputBias", modal_hdr->ob_qam); 121 PR_EEP("PAL_OFF OutputBias", modal_hdr->ob_pal_off); 122 123 return len; 124 } 125 126 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 127 u8 *buf, u32 len, u32 size) 128 { 129 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 130 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader; 131 132 if (!dump_base_hdr) { 133 len += snprintf(buf + len, size - len, 134 "%20s :\n", "2GHz modal Header"); 135 len = ar9287_dump_modal_eeprom(buf, len, size, 136 &eep->modalHeader); 137 goto out; 138 } 139 140 PR_EEP("Major Version", pBase->version >> 12); 141 PR_EEP("Minor Version", pBase->version & 0xFFF); 142 PR_EEP("Checksum", pBase->checksum); 143 PR_EEP("Length", pBase->length); 144 PR_EEP("RegDomain1", pBase->regDmn[0]); 145 PR_EEP("RegDomain2", pBase->regDmn[1]); 146 PR_EEP("TX Mask", pBase->txMask); 147 PR_EEP("RX Mask", pBase->rxMask); 148 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); 149 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); 150 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & 151 AR5416_OPFLAGS_N_2G_HT20)); 152 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & 153 AR5416_OPFLAGS_N_2G_HT40)); 154 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & 155 AR5416_OPFLAGS_N_5G_HT20)); 156 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & 157 AR5416_OPFLAGS_N_5G_HT40)); 158 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01)); 159 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF); 160 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF); 161 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF); 162 PR_EEP("Power Table Offset", pBase->pwrTableOffset); 163 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl); 164 165 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", 166 pBase->macAddr); 167 168 out: 169 if (len > size) 170 len = size; 171 172 return len; 173 } 174 #else 175 static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 176 u8 *buf, u32 len, u32 size) 177 { 178 return 0; 179 } 180 #endif 181 182 183 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) 184 { 185 u32 sum = 0, el, integer; 186 u16 temp, word, magic, magic2, *eepdata; 187 int i, addr; 188 bool need_swap = false; 189 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 190 struct ath_common *common = ath9k_hw_common(ah); 191 192 if (!ath9k_hw_use_flash(ah)) { 193 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 194 &magic)) { 195 ath_err(common, "Reading Magic # failed\n"); 196 return false; 197 } 198 199 ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic); 200 201 if (magic != AR5416_EEPROM_MAGIC) { 202 magic2 = swab16(magic); 203 204 if (magic2 == AR5416_EEPROM_MAGIC) { 205 need_swap = true; 206 eepdata = (u16 *)(&ah->eeprom); 207 208 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { 209 temp = swab16(*eepdata); 210 *eepdata = temp; 211 eepdata++; 212 } 213 } else { 214 ath_err(common, 215 "Invalid EEPROM Magic. Endianness mismatch.\n"); 216 return -EINVAL; 217 } 218 } 219 } 220 221 ath_dbg(common, EEPROM, "need_swap = %s\n", 222 need_swap ? "True" : "False"); 223 224 if (need_swap) 225 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 226 else 227 el = ah->eeprom.map9287.baseEepHeader.length; 228 229 if (el > sizeof(struct ar9287_eeprom)) 230 el = sizeof(struct ar9287_eeprom) / sizeof(u16); 231 else 232 el = el / sizeof(u16); 233 234 eepdata = (u16 *)(&ah->eeprom); 235 236 for (i = 0; i < el; i++) 237 sum ^= *eepdata++; 238 239 if (need_swap) { 240 word = swab16(eep->baseEepHeader.length); 241 eep->baseEepHeader.length = word; 242 243 word = swab16(eep->baseEepHeader.checksum); 244 eep->baseEepHeader.checksum = word; 245 246 word = swab16(eep->baseEepHeader.version); 247 eep->baseEepHeader.version = word; 248 249 word = swab16(eep->baseEepHeader.regDmn[0]); 250 eep->baseEepHeader.regDmn[0] = word; 251 252 word = swab16(eep->baseEepHeader.regDmn[1]); 253 eep->baseEepHeader.regDmn[1] = word; 254 255 word = swab16(eep->baseEepHeader.rfSilent); 256 eep->baseEepHeader.rfSilent = word; 257 258 word = swab16(eep->baseEepHeader.blueToothOptions); 259 eep->baseEepHeader.blueToothOptions = word; 260 261 word = swab16(eep->baseEepHeader.deviceCap); 262 eep->baseEepHeader.deviceCap = word; 263 264 integer = swab32(eep->modalHeader.antCtrlCommon); 265 eep->modalHeader.antCtrlCommon = integer; 266 267 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 268 integer = swab32(eep->modalHeader.antCtrlChain[i]); 269 eep->modalHeader.antCtrlChain[i] = integer; 270 } 271 272 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 273 word = swab16(eep->modalHeader.spurChans[i].spurChan); 274 eep->modalHeader.spurChans[i].spurChan = word; 275 } 276 } 277 278 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 279 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 280 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 281 sum, ah->eep_ops->get_eeprom_ver(ah)); 282 return -EINVAL; 283 } 284 285 return 0; 286 } 287 288 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah, 289 enum eeprom_param param) 290 { 291 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 292 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 293 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader; 294 u16 ver_minor; 295 296 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK; 297 298 switch (param) { 299 case EEP_NFTHRESH_2: 300 return pModal->noiseFloorThreshCh[0]; 301 case EEP_MAC_LSW: 302 return get_unaligned_be16(pBase->macAddr); 303 case EEP_MAC_MID: 304 return get_unaligned_be16(pBase->macAddr + 2); 305 case EEP_MAC_MSW: 306 return get_unaligned_be16(pBase->macAddr + 4); 307 case EEP_REG_0: 308 return pBase->regDmn[0]; 309 case EEP_OP_CAP: 310 return pBase->deviceCap; 311 case EEP_OP_MODE: 312 return pBase->opCapFlags; 313 case EEP_RF_SILENT: 314 return pBase->rfSilent; 315 case EEP_MINOR_REV: 316 return ver_minor; 317 case EEP_TX_MASK: 318 return pBase->txMask; 319 case EEP_RX_MASK: 320 return pBase->rxMask; 321 case EEP_DEV_TYPE: 322 return pBase->deviceType; 323 case EEP_OL_PWRCTRL: 324 return pBase->openLoopPwrCntl; 325 case EEP_TEMPSENSE_SLOPE: 326 if (ver_minor >= AR9287_EEP_MINOR_VER_2) 327 return pBase->tempSensSlope; 328 else 329 return 0; 330 case EEP_TEMPSENSE_SLOPE_PAL_ON: 331 if (ver_minor >= AR9287_EEP_MINOR_VER_3) 332 return pBase->tempSensSlopePalOn; 333 else 334 return 0; 335 case EEP_ANTENNA_GAIN_2G: 336 return max_t(u8, pModal->antennaGainCh[0], 337 pModal->antennaGainCh[1]); 338 default: 339 return 0; 340 } 341 } 342 343 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, 344 struct ath9k_channel *chan, 345 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, 346 u8 *pCalChans, u16 availPiers, int8_t *pPwr) 347 { 348 u16 idxL = 0, idxR = 0, numPiers; 349 bool match; 350 struct chan_centers centers; 351 352 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 353 354 for (numPiers = 0; numPiers < availPiers; numPiers++) { 355 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED) 356 break; 357 } 358 359 match = ath9k_hw_get_lower_upper_index( 360 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), 361 pCalChans, numPiers, &idxL, &idxR); 362 363 if (match) { 364 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0]; 365 } else { 366 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] + 367 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2; 368 } 369 370 } 371 372 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah, 373 int32_t txPower, u16 chain) 374 { 375 u32 tmpVal; 376 u32 a; 377 378 /* Enable OLPC for chain 0 */ 379 380 tmpVal = REG_READ(ah, 0xa270); 381 tmpVal = tmpVal & 0xFCFFFFFF; 382 tmpVal = tmpVal | (0x3 << 24); 383 REG_WRITE(ah, 0xa270, tmpVal); 384 385 /* Enable OLPC for chain 1 */ 386 387 tmpVal = REG_READ(ah, 0xb270); 388 tmpVal = tmpVal & 0xFCFFFFFF; 389 tmpVal = tmpVal | (0x3 << 24); 390 REG_WRITE(ah, 0xb270, tmpVal); 391 392 /* Write the OLPC ref power for chain 0 */ 393 394 if (chain == 0) { 395 tmpVal = REG_READ(ah, 0xa398); 396 tmpVal = tmpVal & 0xff00ffff; 397 a = (txPower)&0xff; 398 tmpVal = tmpVal | (a << 16); 399 REG_WRITE(ah, 0xa398, tmpVal); 400 } 401 402 /* Write the OLPC ref power for chain 1 */ 403 404 if (chain == 1) { 405 tmpVal = REG_READ(ah, 0xb398); 406 tmpVal = tmpVal & 0xff00ffff; 407 a = (txPower)&0xff; 408 tmpVal = tmpVal | (a << 16); 409 REG_WRITE(ah, 0xb398, tmpVal); 410 } 411 } 412 413 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, 414 struct ath9k_channel *chan) 415 { 416 struct cal_data_per_freq_ar9287 *pRawDataset; 417 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 418 u8 *pCalBChans = NULL; 419 u16 pdGainOverlap_t2; 420 u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 421 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 422 u16 numPiers = 0, i, j; 423 u16 numXpdGain, xpdMask; 424 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0}; 425 u32 reg32, regOffset, regChainOffset, regval; 426 int16_t diff = 0; 427 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 428 429 xpdMask = pEepData->modalHeader.xpdGain; 430 431 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 432 AR9287_EEP_MINOR_VER_2) 433 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 434 else 435 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 436 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 437 438 if (IS_CHAN_2GHZ(chan)) { 439 pCalBChans = pEepData->calFreqPier2G; 440 numPiers = AR9287_NUM_2G_CAL_PIERS; 441 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 442 pRawDatasetOpenLoop = 443 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0]; 444 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0]; 445 } 446 } 447 448 numXpdGain = 0; 449 450 /* Calculate the value of xpdgains from the xpdGain Mask */ 451 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 452 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 453 if (numXpdGain >= AR5416_NUM_PD_GAINS) 454 break; 455 xpdGainValues[numXpdGain] = 456 (u16)(AR5416_PD_GAINS_IN_MASK-i); 457 numXpdGain++; 458 } 459 } 460 461 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 462 (numXpdGain - 1) & 0x3); 463 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 464 xpdGainValues[0]); 465 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 466 xpdGainValues[1]); 467 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 468 xpdGainValues[2]); 469 470 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 471 regChainOffset = i * 0x1000; 472 473 if (pEepData->baseEepHeader.txMask & (1 << i)) { 474 pRawDatasetOpenLoop = 475 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i]; 476 477 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 478 int8_t txPower; 479 ar9287_eeprom_get_tx_gain_index(ah, chan, 480 pRawDatasetOpenLoop, 481 pCalBChans, numPiers, 482 &txPower); 483 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i); 484 } else { 485 pRawDataset = 486 (struct cal_data_per_freq_ar9287 *) 487 pEepData->calPierData2G[i]; 488 489 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, 490 pRawDataset, 491 pCalBChans, numPiers, 492 pdGainOverlap_t2, 493 gainBoundaries, 494 pdadcValues, 495 numXpdGain); 496 } 497 498 ENABLE_REGWRITE_BUFFER(ah); 499 500 if (i == 0) { 501 if (!ath9k_hw_ar9287_get_eeprom(ah, 502 EEP_OL_PWRCTRL)) { 503 504 regval = SM(pdGainOverlap_t2, 505 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 506 | SM(gainBoundaries[0], 507 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 508 | SM(gainBoundaries[1], 509 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 510 | SM(gainBoundaries[2], 511 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 512 | SM(gainBoundaries[3], 513 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4); 514 515 REG_WRITE(ah, 516 AR_PHY_TPCRG5 + regChainOffset, 517 regval); 518 } 519 } 520 521 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB != 522 pEepData->baseEepHeader.pwrTableOffset) { 523 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset - 524 (int32_t)AR9287_PWR_TABLE_OFFSET_DB); 525 diff *= 2; 526 527 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++) 528 pdadcValues[j] = pdadcValues[j+diff]; 529 530 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff); 531 j < AR5416_NUM_PDADC_VALUES; j++) 532 pdadcValues[j] = 533 pdadcValues[AR5416_NUM_PDADC_VALUES-diff]; 534 } 535 536 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 537 regOffset = AR_PHY_BASE + 538 (672 << 2) + regChainOffset; 539 540 for (j = 0; j < 32; j++) { 541 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); 542 543 REG_WRITE(ah, regOffset, reg32); 544 regOffset += 4; 545 } 546 } 547 REGWRITE_BUFFER_FLUSH(ah); 548 } 549 } 550 } 551 552 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, 553 struct ath9k_channel *chan, 554 int16_t *ratesArray, 555 u16 cfgCtl, 556 u16 antenna_reduction, 557 u16 powerLimit) 558 { 559 #define CMP_CTL \ 560 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 561 pEepData->ctlIndex[i]) 562 563 #define CMP_NO_CTL \ 564 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 565 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 566 567 u16 twiceMaxEdgePower; 568 int i; 569 struct cal_ctl_data_ar9287 *rep; 570 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, 571 targetPowerCck = {0, {0, 0, 0, 0} }; 572 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} }, 573 targetPowerCckExt = {0, {0, 0, 0, 0} }; 574 struct cal_target_power_ht targetPowerHt20, 575 targetPowerHt40 = {0, {0, 0, 0, 0} }; 576 u16 scaledPower = 0, minCtlPower; 577 static const u16 ctlModesFor11g[] = { 578 CTL_11B, CTL_11G, CTL_2GHT20, 579 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 580 }; 581 u16 numCtlModes = 0; 582 const u16 *pCtlMode = NULL; 583 u16 ctlMode, freq; 584 struct chan_centers centers; 585 int tx_chainmask; 586 u16 twiceMinEdgePower; 587 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 588 tx_chainmask = ah->txchainmask; 589 590 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 591 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, 592 antenna_reduction); 593 594 /* 595 * Get TX power from EEPROM. 596 */ 597 if (IS_CHAN_2GHZ(chan)) { 598 /* CTL_11B, CTL_11G, CTL_2GHT20 */ 599 numCtlModes = 600 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 601 602 pCtlMode = ctlModesFor11g; 603 604 ath9k_hw_get_legacy_target_powers(ah, chan, 605 pEepData->calTargetPowerCck, 606 AR9287_NUM_2G_CCK_TARGET_POWERS, 607 &targetPowerCck, 4, false); 608 ath9k_hw_get_legacy_target_powers(ah, chan, 609 pEepData->calTargetPower2G, 610 AR9287_NUM_2G_20_TARGET_POWERS, 611 &targetPowerOfdm, 4, false); 612 ath9k_hw_get_target_powers(ah, chan, 613 pEepData->calTargetPower2GHT20, 614 AR9287_NUM_2G_20_TARGET_POWERS, 615 &targetPowerHt20, 8, false); 616 617 if (IS_CHAN_HT40(chan)) { 618 /* All 2G CTLs */ 619 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 620 ath9k_hw_get_target_powers(ah, chan, 621 pEepData->calTargetPower2GHT40, 622 AR9287_NUM_2G_40_TARGET_POWERS, 623 &targetPowerHt40, 8, true); 624 ath9k_hw_get_legacy_target_powers(ah, chan, 625 pEepData->calTargetPowerCck, 626 AR9287_NUM_2G_CCK_TARGET_POWERS, 627 &targetPowerCckExt, 4, true); 628 ath9k_hw_get_legacy_target_powers(ah, chan, 629 pEepData->calTargetPower2G, 630 AR9287_NUM_2G_20_TARGET_POWERS, 631 &targetPowerOfdmExt, 4, true); 632 } 633 } 634 635 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 636 bool isHt40CtlMode = 637 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false; 638 639 if (isHt40CtlMode) 640 freq = centers.synth_center; 641 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 642 freq = centers.ext_center; 643 else 644 freq = centers.ctl_center; 645 646 twiceMaxEdgePower = MAX_RATE_POWER; 647 /* Walk through the CTL indices stored in EEPROM */ 648 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 649 struct cal_ctl_edges *pRdEdgesPower; 650 651 /* 652 * Compare test group from regulatory channel list 653 * with test mode from pCtlMode list 654 */ 655 if (CMP_CTL || CMP_NO_CTL) { 656 rep = &(pEepData->ctlData[i]); 657 pRdEdgesPower = 658 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1]; 659 660 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, 661 pRdEdgesPower, 662 IS_CHAN_2GHZ(chan), 663 AR5416_NUM_BAND_EDGES); 664 665 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 666 twiceMaxEdgePower = min(twiceMaxEdgePower, 667 twiceMinEdgePower); 668 } else { 669 twiceMaxEdgePower = twiceMinEdgePower; 670 break; 671 } 672 } 673 } 674 675 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 676 677 /* Apply ctl mode to correct target power set */ 678 switch (pCtlMode[ctlMode]) { 679 case CTL_11B: 680 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 681 targetPowerCck.tPow2x[i] = 682 (u8)min((u16)targetPowerCck.tPow2x[i], 683 minCtlPower); 684 } 685 break; 686 case CTL_11A: 687 case CTL_11G: 688 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 689 targetPowerOfdm.tPow2x[i] = 690 (u8)min((u16)targetPowerOfdm.tPow2x[i], 691 minCtlPower); 692 } 693 break; 694 case CTL_5GHT20: 695 case CTL_2GHT20: 696 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 697 targetPowerHt20.tPow2x[i] = 698 (u8)min((u16)targetPowerHt20.tPow2x[i], 699 minCtlPower); 700 } 701 break; 702 case CTL_11B_EXT: 703 targetPowerCckExt.tPow2x[0] = 704 (u8)min((u16)targetPowerCckExt.tPow2x[0], 705 minCtlPower); 706 break; 707 case CTL_11A_EXT: 708 case CTL_11G_EXT: 709 targetPowerOfdmExt.tPow2x[0] = 710 (u8)min((u16)targetPowerOfdmExt.tPow2x[0], 711 minCtlPower); 712 break; 713 case CTL_5GHT40: 714 case CTL_2GHT40: 715 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 716 targetPowerHt40.tPow2x[i] = 717 (u8)min((u16)targetPowerHt40.tPow2x[i], 718 minCtlPower); 719 } 720 break; 721 default: 722 break; 723 } 724 } 725 726 /* Now set the rates array */ 727 728 ratesArray[rate6mb] = 729 ratesArray[rate9mb] = 730 ratesArray[rate12mb] = 731 ratesArray[rate18mb] = 732 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 733 734 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 735 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 736 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 737 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 738 739 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 740 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 741 742 if (IS_CHAN_2GHZ(chan)) { 743 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 744 ratesArray[rate2s] = 745 ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 746 ratesArray[rate5_5s] = 747 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 748 ratesArray[rate11s] = 749 ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 750 } 751 if (IS_CHAN_HT40(chan)) { 752 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) 753 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 754 755 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 756 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 757 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 758 759 if (IS_CHAN_2GHZ(chan)) 760 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 761 } 762 763 #undef CMP_CTL 764 #undef CMP_NO_CTL 765 } 766 767 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, 768 struct ath9k_channel *chan, u16 cfgCtl, 769 u8 twiceAntennaReduction, 770 u8 powerLimit, bool test) 771 { 772 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 773 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 774 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 775 int16_t ratesArray[Ar5416RateSize]; 776 u8 ht40PowerIncForPdadc = 2; 777 int i; 778 779 memset(ratesArray, 0, sizeof(ratesArray)); 780 781 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 782 AR9287_EEP_MINOR_VER_2) 783 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 784 785 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan, 786 &ratesArray[0], cfgCtl, 787 twiceAntennaReduction, 788 powerLimit); 789 790 ath9k_hw_set_ar9287_power_cal_table(ah, chan); 791 792 regulatory->max_power_level = 0; 793 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 794 if (ratesArray[i] > MAX_RATE_POWER) 795 ratesArray[i] = MAX_RATE_POWER; 796 797 if (ratesArray[i] > regulatory->max_power_level) 798 regulatory->max_power_level = ratesArray[i]; 799 } 800 801 ath9k_hw_update_regulatory_maxpower(ah); 802 803 if (test) 804 return; 805 806 for (i = 0; i < Ar5416RateSize; i++) 807 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; 808 809 ENABLE_REGWRITE_BUFFER(ah); 810 811 /* OFDM power per rate */ 812 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 813 ATH9K_POW_SM(ratesArray[rate18mb], 24) 814 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 815 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 816 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 817 818 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 819 ATH9K_POW_SM(ratesArray[rate54mb], 24) 820 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 821 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 822 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 823 824 /* CCK power per rate */ 825 if (IS_CHAN_2GHZ(chan)) { 826 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 827 ATH9K_POW_SM(ratesArray[rate2s], 24) 828 | ATH9K_POW_SM(ratesArray[rate2l], 16) 829 | ATH9K_POW_SM(ratesArray[rateXr], 8) 830 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 831 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 832 ATH9K_POW_SM(ratesArray[rate11s], 24) 833 | ATH9K_POW_SM(ratesArray[rate11l], 16) 834 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 835 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 836 } 837 838 /* HT20 power per rate */ 839 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 840 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 841 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 842 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 843 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 844 845 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 846 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 847 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 848 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 849 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 850 851 /* HT40 power per rate */ 852 if (IS_CHAN_HT40(chan)) { 853 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 854 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 855 ATH9K_POW_SM(ratesArray[rateHt40_3], 24) 856 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) 857 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8) 858 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0)); 859 860 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 861 ATH9K_POW_SM(ratesArray[rateHt40_7], 24) 862 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16) 863 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8) 864 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0)); 865 } else { 866 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 867 ATH9K_POW_SM(ratesArray[rateHt40_3] + 868 ht40PowerIncForPdadc, 24) 869 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 870 ht40PowerIncForPdadc, 16) 871 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 872 ht40PowerIncForPdadc, 8) 873 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 874 ht40PowerIncForPdadc, 0)); 875 876 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 877 ATH9K_POW_SM(ratesArray[rateHt40_7] + 878 ht40PowerIncForPdadc, 24) 879 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 880 ht40PowerIncForPdadc, 16) 881 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 882 ht40PowerIncForPdadc, 8) 883 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 884 ht40PowerIncForPdadc, 0)); 885 } 886 887 /* Dup/Ext power per rate */ 888 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 889 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 890 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 891 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 892 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 893 } 894 REGWRITE_BUFFER_FLUSH(ah); 895 } 896 897 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah, 898 struct ath9k_channel *chan) 899 { 900 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 901 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 902 u32 regChainOffset, regval; 903 u8 txRxAttenLocal; 904 int i; 905 906 pModal = &eep->modalHeader; 907 908 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 909 910 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 911 regChainOffset = i * 0x1000; 912 913 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 914 pModal->antCtrlChain[i]); 915 916 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 917 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) 918 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 919 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 920 SM(pModal->iqCalICh[i], 921 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 922 SM(pModal->iqCalQCh[i], 923 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 924 925 txRxAttenLocal = pModal->txRxAttenCh[i]; 926 927 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 928 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 929 pModal->bswMargin[i]); 930 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 931 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 932 pModal->bswAtten[i]); 933 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 934 AR9280_PHY_RXGAIN_TXRX_ATTEN, 935 txRxAttenLocal); 936 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 937 AR9280_PHY_RXGAIN_TXRX_MARGIN, 938 pModal->rxTxMarginCh[i]); 939 } 940 941 942 if (IS_CHAN_HT40(chan)) 943 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 944 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 945 else 946 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 947 AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 948 949 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 950 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 951 952 REG_WRITE(ah, AR_PHY_RF_CTL4, 953 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 954 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 955 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 956 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 957 958 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, 959 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 960 961 REG_RMW_FIELD(ah, AR_PHY_CCA, 962 AR9280_PHY_CCA_THRESH62, pModal->thresh62); 963 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, 964 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); 965 966 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); 967 regval &= ~(AR9287_AN_RF2G3_DB1 | 968 AR9287_AN_RF2G3_DB2 | 969 AR9287_AN_RF2G3_OB_CCK | 970 AR9287_AN_RF2G3_OB_PSK | 971 AR9287_AN_RF2G3_OB_QAM | 972 AR9287_AN_RF2G3_OB_PAL_OFF); 973 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 974 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 975 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 976 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 977 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 978 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 979 980 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval); 981 982 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); 983 regval &= ~(AR9287_AN_RF2G3_DB1 | 984 AR9287_AN_RF2G3_DB2 | 985 AR9287_AN_RF2G3_OB_CCK | 986 AR9287_AN_RF2G3_OB_PSK | 987 AR9287_AN_RF2G3_OB_QAM | 988 AR9287_AN_RF2G3_OB_PAL_OFF); 989 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 990 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 991 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 992 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 993 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 994 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 995 996 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval); 997 998 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 999 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart); 1000 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 1001 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn); 1002 1003 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2, 1004 AR9287_AN_TOP2_XPABIAS_LVL, 1005 AR9287_AN_TOP2_XPABIAS_LVL_S, 1006 pModal->xpaBiasLvl); 1007 } 1008 1009 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, 1010 u16 i, bool is2GHz) 1011 { 1012 #define EEP_MAP9287_SPURCHAN \ 1013 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1014 1015 struct ath_common *common = ath9k_hw_common(ah); 1016 u16 spur_val = AR_NO_SPUR; 1017 1018 ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", 1019 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1020 1021 switch (ah->config.spurmode) { 1022 case SPUR_DISABLE: 1023 break; 1024 case SPUR_ENABLE_IOCTL: 1025 spur_val = ah->config.spurchans[i][is2GHz]; 1026 ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", 1027 spur_val); 1028 break; 1029 case SPUR_ENABLE_EEPROM: 1030 spur_val = EEP_MAP9287_SPURCHAN; 1031 break; 1032 } 1033 1034 return spur_val; 1035 1036 #undef EEP_MAP9287_SPURCHAN 1037 } 1038 1039 const struct eeprom_ops eep_ar9287_ops = { 1040 .check_eeprom = ath9k_hw_ar9287_check_eeprom, 1041 .get_eeprom = ath9k_hw_ar9287_get_eeprom, 1042 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom, 1043 .dump_eeprom = ath9k_hw_ar9287_dump_eeprom, 1044 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver, 1045 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev, 1046 .set_board_values = ath9k_hw_ar9287_set_board_values, 1047 .set_txpower = ath9k_hw_ar9287_set_txpower, 1048 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel 1049 }; 1050