1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9002_phy.h" 19 20 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16)) 21 22 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah) 23 { 24 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF; 25 } 26 27 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah) 28 { 29 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF; 30 } 31 32 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) 33 { 34 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 35 struct ath_common *common = ath9k_hw_common(ah); 36 u16 *eep_data; 37 int addr, eep_start_loc = AR9287_EEP_START_LOC; 38 eep_data = (u16 *)eep; 39 40 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { 41 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, 42 eep_data)) { 43 ath_dbg(common, ATH_DBG_EEPROM, 44 "Unable to read eeprom region\n"); 45 return false; 46 } 47 eep_data++; 48 } 49 50 return true; 51 } 52 53 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah) 54 { 55 u16 *eep_data = (u16 *)&ah->eeprom.map9287; 56 57 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 58 AR9287_HTC_EEP_START_LOC, 59 SIZE_EEPROM_AR9287); 60 return true; 61 } 62 63 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) 64 { 65 struct ath_common *common = ath9k_hw_common(ah); 66 67 if (!ath9k_hw_use_flash(ah)) { 68 ath_dbg(common, ATH_DBG_EEPROM, 69 "Reading from EEPROM, not flash\n"); 70 } 71 72 if (common->bus_ops->ath_bus_type == ATH_USB) 73 return __ath9k_hw_usb_ar9287_fill_eeprom(ah); 74 else 75 return __ath9k_hw_ar9287_fill_eeprom(ah); 76 } 77 78 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) 79 { 80 u32 sum = 0, el, integer; 81 u16 temp, word, magic, magic2, *eepdata; 82 int i, addr; 83 bool need_swap = false; 84 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 85 struct ath_common *common = ath9k_hw_common(ah); 86 87 if (!ath9k_hw_use_flash(ah)) { 88 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 89 &magic)) { 90 ath_err(common, "Reading Magic # failed\n"); 91 return false; 92 } 93 94 ath_dbg(common, ATH_DBG_EEPROM, 95 "Read Magic = 0x%04X\n", magic); 96 97 if (magic != AR5416_EEPROM_MAGIC) { 98 magic2 = swab16(magic); 99 100 if (magic2 == AR5416_EEPROM_MAGIC) { 101 need_swap = true; 102 eepdata = (u16 *)(&ah->eeprom); 103 104 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { 105 temp = swab16(*eepdata); 106 *eepdata = temp; 107 eepdata++; 108 } 109 } else { 110 ath_err(common, 111 "Invalid EEPROM Magic. Endianness mismatch.\n"); 112 return -EINVAL; 113 } 114 } 115 } 116 117 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 118 need_swap ? "True" : "False"); 119 120 if (need_swap) 121 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 122 else 123 el = ah->eeprom.map9287.baseEepHeader.length; 124 125 if (el > sizeof(struct ar9287_eeprom)) 126 el = sizeof(struct ar9287_eeprom) / sizeof(u16); 127 else 128 el = el / sizeof(u16); 129 130 eepdata = (u16 *)(&ah->eeprom); 131 132 for (i = 0; i < el; i++) 133 sum ^= *eepdata++; 134 135 if (need_swap) { 136 word = swab16(eep->baseEepHeader.length); 137 eep->baseEepHeader.length = word; 138 139 word = swab16(eep->baseEepHeader.checksum); 140 eep->baseEepHeader.checksum = word; 141 142 word = swab16(eep->baseEepHeader.version); 143 eep->baseEepHeader.version = word; 144 145 word = swab16(eep->baseEepHeader.regDmn[0]); 146 eep->baseEepHeader.regDmn[0] = word; 147 148 word = swab16(eep->baseEepHeader.regDmn[1]); 149 eep->baseEepHeader.regDmn[1] = word; 150 151 word = swab16(eep->baseEepHeader.rfSilent); 152 eep->baseEepHeader.rfSilent = word; 153 154 word = swab16(eep->baseEepHeader.blueToothOptions); 155 eep->baseEepHeader.blueToothOptions = word; 156 157 word = swab16(eep->baseEepHeader.deviceCap); 158 eep->baseEepHeader.deviceCap = word; 159 160 integer = swab32(eep->modalHeader.antCtrlCommon); 161 eep->modalHeader.antCtrlCommon = integer; 162 163 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 164 integer = swab32(eep->modalHeader.antCtrlChain[i]); 165 eep->modalHeader.antCtrlChain[i] = integer; 166 } 167 168 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 169 word = swab16(eep->modalHeader.spurChans[i].spurChan); 170 eep->modalHeader.spurChans[i].spurChan = word; 171 } 172 } 173 174 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 175 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 176 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 177 sum, ah->eep_ops->get_eeprom_ver(ah)); 178 return -EINVAL; 179 } 180 181 return 0; 182 } 183 184 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah, 185 enum eeprom_param param) 186 { 187 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 188 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 189 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader; 190 u16 ver_minor; 191 192 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK; 193 194 switch (param) { 195 case EEP_NFTHRESH_2: 196 return pModal->noiseFloorThreshCh[0]; 197 case EEP_MAC_LSW: 198 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 199 case EEP_MAC_MID: 200 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 201 case EEP_MAC_MSW: 202 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 203 case EEP_REG_0: 204 return pBase->regDmn[0]; 205 case EEP_REG_1: 206 return pBase->regDmn[1]; 207 case EEP_OP_CAP: 208 return pBase->deviceCap; 209 case EEP_OP_MODE: 210 return pBase->opCapFlags; 211 case EEP_RF_SILENT: 212 return pBase->rfSilent; 213 case EEP_MINOR_REV: 214 return ver_minor; 215 case EEP_TX_MASK: 216 return pBase->txMask; 217 case EEP_RX_MASK: 218 return pBase->rxMask; 219 case EEP_DEV_TYPE: 220 return pBase->deviceType; 221 case EEP_OL_PWRCTRL: 222 return pBase->openLoopPwrCntl; 223 case EEP_TEMPSENSE_SLOPE: 224 if (ver_minor >= AR9287_EEP_MINOR_VER_2) 225 return pBase->tempSensSlope; 226 else 227 return 0; 228 case EEP_TEMPSENSE_SLOPE_PAL_ON: 229 if (ver_minor >= AR9287_EEP_MINOR_VER_3) 230 return pBase->tempSensSlopePalOn; 231 else 232 return 0; 233 default: 234 return 0; 235 } 236 } 237 238 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, 239 struct ath9k_channel *chan, 240 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, 241 u8 *pCalChans, u16 availPiers, int8_t *pPwr) 242 { 243 u16 idxL = 0, idxR = 0, numPiers; 244 bool match; 245 struct chan_centers centers; 246 247 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 248 249 for (numPiers = 0; numPiers < availPiers; numPiers++) { 250 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED) 251 break; 252 } 253 254 match = ath9k_hw_get_lower_upper_index( 255 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), 256 pCalChans, numPiers, &idxL, &idxR); 257 258 if (match) { 259 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0]; 260 } else { 261 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] + 262 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2; 263 } 264 265 } 266 267 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah, 268 int32_t txPower, u16 chain) 269 { 270 u32 tmpVal; 271 u32 a; 272 273 /* Enable OLPC for chain 0 */ 274 275 tmpVal = REG_READ(ah, 0xa270); 276 tmpVal = tmpVal & 0xFCFFFFFF; 277 tmpVal = tmpVal | (0x3 << 24); 278 REG_WRITE(ah, 0xa270, tmpVal); 279 280 /* Enable OLPC for chain 1 */ 281 282 tmpVal = REG_READ(ah, 0xb270); 283 tmpVal = tmpVal & 0xFCFFFFFF; 284 tmpVal = tmpVal | (0x3 << 24); 285 REG_WRITE(ah, 0xb270, tmpVal); 286 287 /* Write the OLPC ref power for chain 0 */ 288 289 if (chain == 0) { 290 tmpVal = REG_READ(ah, 0xa398); 291 tmpVal = tmpVal & 0xff00ffff; 292 a = (txPower)&0xff; 293 tmpVal = tmpVal | (a << 16); 294 REG_WRITE(ah, 0xa398, tmpVal); 295 } 296 297 /* Write the OLPC ref power for chain 1 */ 298 299 if (chain == 1) { 300 tmpVal = REG_READ(ah, 0xb398); 301 tmpVal = tmpVal & 0xff00ffff; 302 a = (txPower)&0xff; 303 tmpVal = tmpVal | (a << 16); 304 REG_WRITE(ah, 0xb398, tmpVal); 305 } 306 } 307 308 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah, 309 struct ath9k_channel *chan, 310 int16_t *pTxPowerIndexOffset) 311 { 312 struct cal_data_per_freq_ar9287 *pRawDataset; 313 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 314 u8 *pCalBChans = NULL; 315 u16 pdGainOverlap_t2; 316 u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 317 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 318 u16 numPiers = 0, i, j; 319 u16 numXpdGain, xpdMask; 320 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0}; 321 u32 reg32, regOffset, regChainOffset, regval; 322 int16_t modalIdx, diff = 0; 323 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 324 325 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 326 xpdMask = pEepData->modalHeader.xpdGain; 327 328 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 329 AR9287_EEP_MINOR_VER_2) 330 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 331 else 332 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 333 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 334 335 if (IS_CHAN_2GHZ(chan)) { 336 pCalBChans = pEepData->calFreqPier2G; 337 numPiers = AR9287_NUM_2G_CAL_PIERS; 338 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 339 pRawDatasetOpenLoop = 340 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0]; 341 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0]; 342 } 343 } 344 345 numXpdGain = 0; 346 347 /* Calculate the value of xpdgains from the xpdGain Mask */ 348 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 349 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 350 if (numXpdGain >= AR5416_NUM_PD_GAINS) 351 break; 352 xpdGainValues[numXpdGain] = 353 (u16)(AR5416_PD_GAINS_IN_MASK-i); 354 numXpdGain++; 355 } 356 } 357 358 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 359 (numXpdGain - 1) & 0x3); 360 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 361 xpdGainValues[0]); 362 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 363 xpdGainValues[1]); 364 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 365 xpdGainValues[2]); 366 367 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 368 regChainOffset = i * 0x1000; 369 370 if (pEepData->baseEepHeader.txMask & (1 << i)) { 371 pRawDatasetOpenLoop = 372 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i]; 373 374 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 375 int8_t txPower; 376 ar9287_eeprom_get_tx_gain_index(ah, chan, 377 pRawDatasetOpenLoop, 378 pCalBChans, numPiers, 379 &txPower); 380 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i); 381 } else { 382 pRawDataset = 383 (struct cal_data_per_freq_ar9287 *) 384 pEepData->calPierData2G[i]; 385 386 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, 387 pRawDataset, 388 pCalBChans, numPiers, 389 pdGainOverlap_t2, 390 gainBoundaries, 391 pdadcValues, 392 numXpdGain); 393 } 394 395 if (i == 0) { 396 if (!ath9k_hw_ar9287_get_eeprom(ah, 397 EEP_OL_PWRCTRL)) { 398 399 regval = SM(pdGainOverlap_t2, 400 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 401 | SM(gainBoundaries[0], 402 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 403 | SM(gainBoundaries[1], 404 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 405 | SM(gainBoundaries[2], 406 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 407 | SM(gainBoundaries[3], 408 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4); 409 410 REG_WRITE(ah, 411 AR_PHY_TPCRG5 + regChainOffset, 412 regval); 413 } 414 } 415 416 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB != 417 pEepData->baseEepHeader.pwrTableOffset) { 418 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset - 419 (int32_t)AR9287_PWR_TABLE_OFFSET_DB); 420 diff *= 2; 421 422 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++) 423 pdadcValues[j] = pdadcValues[j+diff]; 424 425 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff); 426 j < AR5416_NUM_PDADC_VALUES; j++) 427 pdadcValues[j] = 428 pdadcValues[AR5416_NUM_PDADC_VALUES-diff]; 429 } 430 431 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 432 regOffset = AR_PHY_BASE + 433 (672 << 2) + regChainOffset; 434 435 for (j = 0; j < 32; j++) { 436 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) 437 | ((pdadcValues[4*j + 1] & 0xFF) << 8) 438 | ((pdadcValues[4*j + 2] & 0xFF) << 16) 439 | ((pdadcValues[4*j + 3] & 0xFF) << 24); 440 441 REG_WRITE(ah, regOffset, reg32); 442 regOffset += 4; 443 } 444 } 445 } 446 } 447 448 *pTxPowerIndexOffset = 0; 449 } 450 451 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, 452 struct ath9k_channel *chan, 453 int16_t *ratesArray, 454 u16 cfgCtl, 455 u16 AntennaReduction, 456 u16 twiceMaxRegulatoryPower, 457 u16 powerLimit) 458 { 459 #define CMP_CTL \ 460 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 461 pEepData->ctlIndex[i]) 462 463 #define CMP_NO_CTL \ 464 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 465 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 466 467 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 468 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 469 470 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 471 u16 twiceMaxEdgePower = MAX_RATE_POWER; 472 static const u16 tpScaleReductionTable[5] = 473 { 0, 3, 6, 9, MAX_RATE_POWER }; 474 int i; 475 int16_t twiceLargestAntenna; 476 struct cal_ctl_data_ar9287 *rep; 477 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, 478 targetPowerCck = {0, {0, 0, 0, 0} }; 479 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} }, 480 targetPowerCckExt = {0, {0, 0, 0, 0} }; 481 struct cal_target_power_ht targetPowerHt20, 482 targetPowerHt40 = {0, {0, 0, 0, 0} }; 483 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 484 static const u16 ctlModesFor11g[] = { 485 CTL_11B, CTL_11G, CTL_2GHT20, 486 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 487 }; 488 u16 numCtlModes = 0; 489 const u16 *pCtlMode = NULL; 490 u16 ctlMode, freq; 491 struct chan_centers centers; 492 int tx_chainmask; 493 u16 twiceMinEdgePower; 494 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 495 tx_chainmask = ah->txchainmask; 496 497 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 498 499 /* Compute TxPower reduction due to Antenna Gain */ 500 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0], 501 pEepData->modalHeader.antennaGainCh[1]); 502 twiceLargestAntenna = (int16_t)min((AntennaReduction) - 503 twiceLargestAntenna, 0); 504 505 /* 506 * scaledPower is the minimum of the user input power level 507 * and the regulatory allowed power level. 508 */ 509 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 510 511 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) 512 maxRegAllowedPower -= 513 (tpScaleReductionTable[(regulatory->tp_scale)] * 2); 514 515 scaledPower = min(powerLimit, maxRegAllowedPower); 516 517 /* 518 * Reduce scaled Power by number of chains active 519 * to get the per chain tx power level. 520 */ 521 switch (ar5416_get_ntxchains(tx_chainmask)) { 522 case 1: 523 break; 524 case 2: 525 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; 526 break; 527 case 3: 528 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; 529 break; 530 } 531 scaledPower = max((u16)0, scaledPower); 532 533 /* 534 * Get TX power from EEPROM. 535 */ 536 if (IS_CHAN_2GHZ(chan)) { 537 /* CTL_11B, CTL_11G, CTL_2GHT20 */ 538 numCtlModes = 539 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 540 541 pCtlMode = ctlModesFor11g; 542 543 ath9k_hw_get_legacy_target_powers(ah, chan, 544 pEepData->calTargetPowerCck, 545 AR9287_NUM_2G_CCK_TARGET_POWERS, 546 &targetPowerCck, 4, false); 547 ath9k_hw_get_legacy_target_powers(ah, chan, 548 pEepData->calTargetPower2G, 549 AR9287_NUM_2G_20_TARGET_POWERS, 550 &targetPowerOfdm, 4, false); 551 ath9k_hw_get_target_powers(ah, chan, 552 pEepData->calTargetPower2GHT20, 553 AR9287_NUM_2G_20_TARGET_POWERS, 554 &targetPowerHt20, 8, false); 555 556 if (IS_CHAN_HT40(chan)) { 557 /* All 2G CTLs */ 558 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 559 ath9k_hw_get_target_powers(ah, chan, 560 pEepData->calTargetPower2GHT40, 561 AR9287_NUM_2G_40_TARGET_POWERS, 562 &targetPowerHt40, 8, true); 563 ath9k_hw_get_legacy_target_powers(ah, chan, 564 pEepData->calTargetPowerCck, 565 AR9287_NUM_2G_CCK_TARGET_POWERS, 566 &targetPowerCckExt, 4, true); 567 ath9k_hw_get_legacy_target_powers(ah, chan, 568 pEepData->calTargetPower2G, 569 AR9287_NUM_2G_20_TARGET_POWERS, 570 &targetPowerOfdmExt, 4, true); 571 } 572 } 573 574 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 575 bool isHt40CtlMode = 576 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false; 577 578 if (isHt40CtlMode) 579 freq = centers.synth_center; 580 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 581 freq = centers.ext_center; 582 else 583 freq = centers.ctl_center; 584 585 /* Walk through the CTL indices stored in EEPROM */ 586 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 587 struct cal_ctl_edges *pRdEdgesPower; 588 589 /* 590 * Compare test group from regulatory channel list 591 * with test mode from pCtlMode list 592 */ 593 if (CMP_CTL || CMP_NO_CTL) { 594 rep = &(pEepData->ctlData[i]); 595 pRdEdgesPower = 596 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1]; 597 598 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, 599 pRdEdgesPower, 600 IS_CHAN_2GHZ(chan), 601 AR5416_NUM_BAND_EDGES); 602 603 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 604 twiceMaxEdgePower = min(twiceMaxEdgePower, 605 twiceMinEdgePower); 606 } else { 607 twiceMaxEdgePower = twiceMinEdgePower; 608 break; 609 } 610 } 611 } 612 613 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 614 615 /* Apply ctl mode to correct target power set */ 616 switch (pCtlMode[ctlMode]) { 617 case CTL_11B: 618 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 619 targetPowerCck.tPow2x[i] = 620 (u8)min((u16)targetPowerCck.tPow2x[i], 621 minCtlPower); 622 } 623 break; 624 case CTL_11A: 625 case CTL_11G: 626 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 627 targetPowerOfdm.tPow2x[i] = 628 (u8)min((u16)targetPowerOfdm.tPow2x[i], 629 minCtlPower); 630 } 631 break; 632 case CTL_5GHT20: 633 case CTL_2GHT20: 634 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 635 targetPowerHt20.tPow2x[i] = 636 (u8)min((u16)targetPowerHt20.tPow2x[i], 637 minCtlPower); 638 } 639 break; 640 case CTL_11B_EXT: 641 targetPowerCckExt.tPow2x[0] = 642 (u8)min((u16)targetPowerCckExt.tPow2x[0], 643 minCtlPower); 644 break; 645 case CTL_11A_EXT: 646 case CTL_11G_EXT: 647 targetPowerOfdmExt.tPow2x[0] = 648 (u8)min((u16)targetPowerOfdmExt.tPow2x[0], 649 minCtlPower); 650 break; 651 case CTL_5GHT40: 652 case CTL_2GHT40: 653 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 654 targetPowerHt40.tPow2x[i] = 655 (u8)min((u16)targetPowerHt40.tPow2x[i], 656 minCtlPower); 657 } 658 break; 659 default: 660 break; 661 } 662 } 663 664 /* Now set the rates array */ 665 666 ratesArray[rate6mb] = 667 ratesArray[rate9mb] = 668 ratesArray[rate12mb] = 669 ratesArray[rate18mb] = 670 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 671 672 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 673 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 674 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 675 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 676 677 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 678 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 679 680 if (IS_CHAN_2GHZ(chan)) { 681 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 682 ratesArray[rate2s] = 683 ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 684 ratesArray[rate5_5s] = 685 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 686 ratesArray[rate11s] = 687 ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 688 } 689 if (IS_CHAN_HT40(chan)) { 690 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) 691 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 692 693 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 694 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 695 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 696 697 if (IS_CHAN_2GHZ(chan)) 698 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 699 } 700 701 #undef CMP_CTL 702 #undef CMP_NO_CTL 703 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN 704 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN 705 } 706 707 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah, 708 struct ath9k_channel *chan, u16 cfgCtl, 709 u8 twiceAntennaReduction, 710 u8 twiceMaxRegulatoryPower, 711 u8 powerLimit, bool test) 712 { 713 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 714 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 715 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 716 int16_t ratesArray[Ar5416RateSize]; 717 int16_t txPowerIndexOffset = 0; 718 u8 ht40PowerIncForPdadc = 2; 719 int i; 720 721 memset(ratesArray, 0, sizeof(ratesArray)); 722 723 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 724 AR9287_EEP_MINOR_VER_2) 725 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 726 727 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan, 728 &ratesArray[0], cfgCtl, 729 twiceAntennaReduction, 730 twiceMaxRegulatoryPower, 731 powerLimit); 732 733 ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset); 734 735 regulatory->max_power_level = 0; 736 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 737 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 738 if (ratesArray[i] > MAX_RATE_POWER) 739 ratesArray[i] = MAX_RATE_POWER; 740 741 if (ratesArray[i] > regulatory->max_power_level) 742 regulatory->max_power_level = ratesArray[i]; 743 } 744 745 if (test) 746 return; 747 748 if (IS_CHAN_2GHZ(chan)) 749 i = rate1l; 750 else 751 i = rate6mb; 752 753 regulatory->max_power_level = ratesArray[i]; 754 755 if (AR_SREV_9280_20_OR_LATER(ah)) { 756 for (i = 0; i < Ar5416RateSize; i++) 757 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; 758 } 759 760 /* OFDM power per rate */ 761 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 762 ATH9K_POW_SM(ratesArray[rate18mb], 24) 763 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 764 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 765 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 766 767 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 768 ATH9K_POW_SM(ratesArray[rate54mb], 24) 769 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 770 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 771 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 772 773 /* CCK power per rate */ 774 if (IS_CHAN_2GHZ(chan)) { 775 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 776 ATH9K_POW_SM(ratesArray[rate2s], 24) 777 | ATH9K_POW_SM(ratesArray[rate2l], 16) 778 | ATH9K_POW_SM(ratesArray[rateXr], 8) 779 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 780 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 781 ATH9K_POW_SM(ratesArray[rate11s], 24) 782 | ATH9K_POW_SM(ratesArray[rate11l], 16) 783 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 784 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 785 } 786 787 /* HT20 power per rate */ 788 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 789 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 790 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 791 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 792 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 793 794 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 795 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 796 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 797 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 798 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 799 800 /* HT40 power per rate */ 801 if (IS_CHAN_HT40(chan)) { 802 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 803 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 804 ATH9K_POW_SM(ratesArray[rateHt40_3], 24) 805 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) 806 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8) 807 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0)); 808 809 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 810 ATH9K_POW_SM(ratesArray[rateHt40_7], 24) 811 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16) 812 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8) 813 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0)); 814 } else { 815 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 816 ATH9K_POW_SM(ratesArray[rateHt40_3] + 817 ht40PowerIncForPdadc, 24) 818 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 819 ht40PowerIncForPdadc, 16) 820 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 821 ht40PowerIncForPdadc, 8) 822 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 823 ht40PowerIncForPdadc, 0)); 824 825 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 826 ATH9K_POW_SM(ratesArray[rateHt40_7] + 827 ht40PowerIncForPdadc, 24) 828 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 829 ht40PowerIncForPdadc, 16) 830 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 831 ht40PowerIncForPdadc, 8) 832 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 833 ht40PowerIncForPdadc, 0)); 834 } 835 836 /* Dup/Ext power per rate */ 837 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 838 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 839 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 840 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 841 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 842 } 843 } 844 845 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah, 846 struct ath9k_channel *chan) 847 { 848 } 849 850 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah, 851 struct ath9k_channel *chan) 852 { 853 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 854 struct modal_eep_ar9287_header *pModal = &eep->modalHeader; 855 u16 antWrites[AR9287_ANT_16S]; 856 u32 regChainOffset, regval; 857 u8 txRxAttenLocal; 858 int i, j, offset_num; 859 860 pModal = &eep->modalHeader; 861 862 antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF); 863 antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF); 864 antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF); 865 antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF); 866 antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF); 867 antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF); 868 antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF); 869 antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF); 870 871 offset_num = 8; 872 873 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) { 874 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf); 875 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3); 876 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3); 877 antWrites[j++] = 0; 878 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3); 879 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3); 880 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3); 881 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3); 882 } 883 884 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 885 886 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 887 regChainOffset = i * 0x1000; 888 889 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 890 pModal->antCtrlChain[i]); 891 892 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 893 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) 894 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 895 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 896 SM(pModal->iqCalICh[i], 897 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 898 SM(pModal->iqCalQCh[i], 899 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 900 901 txRxAttenLocal = pModal->txRxAttenCh[i]; 902 903 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 904 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 905 pModal->bswMargin[i]); 906 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 907 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 908 pModal->bswAtten[i]); 909 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 910 AR9280_PHY_RXGAIN_TXRX_ATTEN, 911 txRxAttenLocal); 912 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 913 AR9280_PHY_RXGAIN_TXRX_MARGIN, 914 pModal->rxTxMarginCh[i]); 915 } 916 917 918 if (IS_CHAN_HT40(chan)) 919 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 920 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 921 else 922 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 923 AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 924 925 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 926 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 927 928 REG_WRITE(ah, AR_PHY_RF_CTL4, 929 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 930 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 931 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 932 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 933 934 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, 935 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 936 937 REG_RMW_FIELD(ah, AR_PHY_CCA, 938 AR9280_PHY_CCA_THRESH62, pModal->thresh62); 939 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, 940 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); 941 942 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); 943 regval &= ~(AR9287_AN_RF2G3_DB1 | 944 AR9287_AN_RF2G3_DB2 | 945 AR9287_AN_RF2G3_OB_CCK | 946 AR9287_AN_RF2G3_OB_PSK | 947 AR9287_AN_RF2G3_OB_QAM | 948 AR9287_AN_RF2G3_OB_PAL_OFF); 949 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 950 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 951 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 952 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 953 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 954 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 955 956 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval); 957 958 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); 959 regval &= ~(AR9287_AN_RF2G3_DB1 | 960 AR9287_AN_RF2G3_DB2 | 961 AR9287_AN_RF2G3_OB_CCK | 962 AR9287_AN_RF2G3_OB_PSK | 963 AR9287_AN_RF2G3_OB_QAM | 964 AR9287_AN_RF2G3_OB_PAL_OFF); 965 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | 966 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | 967 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | 968 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | 969 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) | 970 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF)); 971 972 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval); 973 974 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 975 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart); 976 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, 977 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn); 978 979 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2, 980 AR9287_AN_TOP2_XPABIAS_LVL, 981 AR9287_AN_TOP2_XPABIAS_LVL_S, 982 pModal->xpaBiasLvl); 983 } 984 985 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, 986 u16 i, bool is2GHz) 987 { 988 #define EEP_MAP9287_SPURCHAN \ 989 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 990 991 struct ath_common *common = ath9k_hw_common(ah); 992 u16 spur_val = AR_NO_SPUR; 993 994 ath_dbg(common, ATH_DBG_ANI, 995 "Getting spur idx:%d is2Ghz:%d val:%x\n", 996 i, is2GHz, ah->config.spurchans[i][is2GHz]); 997 998 switch (ah->config.spurmode) { 999 case SPUR_DISABLE: 1000 break; 1001 case SPUR_ENABLE_IOCTL: 1002 spur_val = ah->config.spurchans[i][is2GHz]; 1003 ath_dbg(common, ATH_DBG_ANI, 1004 "Getting spur val from new loc. %d\n", spur_val); 1005 break; 1006 case SPUR_ENABLE_EEPROM: 1007 spur_val = EEP_MAP9287_SPURCHAN; 1008 break; 1009 } 1010 1011 return spur_val; 1012 1013 #undef EEP_MAP9287_SPURCHAN 1014 } 1015 1016 const struct eeprom_ops eep_ar9287_ops = { 1017 .check_eeprom = ath9k_hw_ar9287_check_eeprom, 1018 .get_eeprom = ath9k_hw_ar9287_get_eeprom, 1019 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom, 1020 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver, 1021 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev, 1022 .set_board_values = ath9k_hw_ar9287_set_board_values, 1023 .set_addac = ath9k_hw_ar9287_set_addac, 1024 .set_txpower = ath9k_hw_ar9287_set_txpower, 1025 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel 1026 }; 1027