1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef EEPROM_H 18 #define EEPROM_H 19 20 #define AR_EEPROM_MODAL_SPURS 5 21 22 #include "../ath.h" 23 #include <net/cfg80211.h> 24 #include "ar9003_eeprom.h" 25 26 #ifdef __BIG_ENDIAN 27 #define AR5416_EEPROM_MAGIC 0x5aa5 28 #else 29 #define AR5416_EEPROM_MAGIC 0xa55a 30 #endif 31 32 #define CTRY_DEBUG 0x1ff 33 #define CTRY_DEFAULT 0 34 35 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 36 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 37 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 38 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 39 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 40 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 41 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 42 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 43 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 44 45 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 46 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 47 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 48 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 49 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 50 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 51 52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 53 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 54 55 #define AR5416_EEPROM_MAGIC_OFFSET 0x0 56 #define AR5416_EEPROM_S 2 57 #define AR5416_EEPROM_OFFSET 0x2000 58 #define AR5416_EEPROM_MAX 0xae0 59 60 #define AR5416_EEPROM_START_ADDR \ 61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 62 63 #define SD_NO_CTL 0xE0 64 #define NO_CTL 0xff 65 #define CTL_MODE_M 0xf 66 #define CTL_11A 0 67 #define CTL_11B 1 68 #define CTL_11G 2 69 #define CTL_2GHT20 5 70 #define CTL_5GHT20 6 71 #define CTL_2GHT40 7 72 #define CTL_5GHT40 8 73 74 #define EXT_ADDITIVE (0x8000) 75 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 76 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 77 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 78 79 #define SUB_NUM_CTL_MODES_AT_5G_40 2 80 #define SUB_NUM_CTL_MODES_AT_2G_40 3 81 82 #define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */ 83 #define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */ 84 85 /* 86 * For AR9285 and later chipsets, the following bits are not being programmed 87 * in EEPROM and so need to be enabled always. 88 * 89 * Bit 0: en_fcc_mid 90 * Bit 1: en_jap_mid 91 * Bit 2: en_fcc_dfs_ht40 92 * Bit 3: en_jap_ht40 93 * Bit 4: en_jap_dfs_ht40 94 */ 95 #define AR9285_RDEXT_DEFAULT 0x1F 96 97 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 98 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 99 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) 100 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 101 102 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 103 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 104 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 105 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ 106 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 107 108 #define EEP_RFSILENT_ENABLED 0x0001 109 #define EEP_RFSILENT_ENABLED_S 0 110 #define EEP_RFSILENT_POLARITY 0x0002 111 #define EEP_RFSILENT_POLARITY_S 1 112 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) 113 #define EEP_RFSILENT_GPIO_SEL_S 2 114 115 #define AR5416_OPFLAGS_11A 0x01 116 #define AR5416_OPFLAGS_11G 0x02 117 #define AR5416_OPFLAGS_N_5G_HT40 0x04 118 #define AR5416_OPFLAGS_N_2G_HT40 0x08 119 #define AR5416_OPFLAGS_N_5G_HT20 0x10 120 #define AR5416_OPFLAGS_N_2G_HT20 0x20 121 122 #define AR5416_EEP_NO_BACK_VER 0x1 123 #define AR5416_EEP_VER 0xE 124 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF 125 #define AR5416_EEP_MINOR_VER_2 0x2 126 #define AR5416_EEP_MINOR_VER_3 0x3 127 #define AR5416_EEP_MINOR_VER_7 0x7 128 #define AR5416_EEP_MINOR_VER_9 0x9 129 #define AR5416_EEP_MINOR_VER_16 0x10 130 #define AR5416_EEP_MINOR_VER_17 0x11 131 #define AR5416_EEP_MINOR_VER_19 0x13 132 #define AR5416_EEP_MINOR_VER_20 0x14 133 #define AR5416_EEP_MINOR_VER_21 0x15 134 #define AR5416_EEP_MINOR_VER_22 0x16 135 136 #define AR5416_NUM_5G_CAL_PIERS 8 137 #define AR5416_NUM_2G_CAL_PIERS 4 138 #define AR5416_NUM_5G_20_TARGET_POWERS 8 139 #define AR5416_NUM_5G_40_TARGET_POWERS 8 140 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 141 #define AR5416_NUM_2G_20_TARGET_POWERS 4 142 #define AR5416_NUM_2G_40_TARGET_POWERS 4 143 #define AR5416_NUM_CTLS 24 144 #define AR5416_NUM_BAND_EDGES 8 145 #define AR5416_NUM_PD_GAINS 4 146 #define AR5416_PD_GAINS_IN_MASK 4 147 #define AR5416_PD_GAIN_ICEPTS 5 148 #define AR5416_NUM_PDADC_VALUES 128 149 #define AR5416_BCHAN_UNUSED 0xFF 150 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 151 #define AR5416_MAX_CHAINS 3 152 #define AR9300_MAX_CHAINS 3 153 #define AR5416_PWR_TABLE_OFFSET_DB -5 154 155 /* Rx gain type values */ 156 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 157 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 158 #define AR5416_EEP_RXGAIN_ORIG 2 159 160 /* Tx gain type values */ 161 #define AR5416_EEP_TXGAIN_ORIGINAL 0 162 #define AR5416_EEP_TXGAIN_HIGH_POWER 1 163 164 #define AR5416_EEP4K_START_LOC 64 165 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 166 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 167 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 168 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 169 #define AR5416_EEP4K_NUM_CTLS 12 170 #define AR5416_EEP4K_NUM_BAND_EDGES 4 171 #define AR5416_EEP4K_NUM_PD_GAINS 2 172 #define AR5416_EEP4K_MAX_CHAINS 1 173 174 #define AR9280_TX_GAIN_TABLE_SIZE 22 175 176 #define AR9287_EEP_VER 0xE 177 #define AR9287_EEP_VER_MINOR_MASK 0xFFF 178 #define AR9287_EEP_MINOR_VER_1 0x1 179 #define AR9287_EEP_MINOR_VER_2 0x2 180 #define AR9287_EEP_MINOR_VER_3 0x3 181 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 182 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 183 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 184 185 #define AR9287_EEP_START_LOC 128 186 #define AR9287_HTC_EEP_START_LOC 256 187 #define AR9287_NUM_2G_CAL_PIERS 3 188 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 189 #define AR9287_NUM_2G_20_TARGET_POWERS 3 190 #define AR9287_NUM_2G_40_TARGET_POWERS 3 191 #define AR9287_NUM_CTLS 12 192 #define AR9287_NUM_BAND_EDGES 4 193 #define AR9287_PD_GAIN_ICEPTS 1 194 #define AR9287_EEPMISC_BIG_ENDIAN 0x01 195 #define AR9287_EEPMISC_WOW 0x02 196 #define AR9287_MAX_CHAINS 2 197 #define AR9287_ANT_16S 32 198 199 #define AR9287_DATA_SZ 32 200 201 #define AR9287_PWR_TABLE_OFFSET_DB -5 202 203 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 204 205 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 206 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 207 208 #define LNA_CTL_BUF_MODE BIT(0) 209 #define LNA_CTL_ISEL_LO BIT(1) 210 #define LNA_CTL_ISEL_HI BIT(2) 211 #define LNA_CTL_BUF_IN BIT(3) 212 #define LNA_CTL_FEM_BAND BIT(4) 213 #define LNA_CTL_LOCAL_BIAS BIT(5) 214 #define LNA_CTL_FORCE_XPA BIT(6) 215 #define LNA_CTL_USE_ANT1 BIT(7) 216 217 enum eeprom_param { 218 EEP_NFTHRESH_5, 219 EEP_NFTHRESH_2, 220 EEP_MAC_MSW, 221 EEP_MAC_MID, 222 EEP_MAC_LSW, 223 EEP_REG_0, 224 EEP_OP_CAP, 225 EEP_OP_MODE, 226 EEP_RF_SILENT, 227 EEP_OB_5, 228 EEP_DB_5, 229 EEP_OB_2, 230 EEP_DB_2, 231 EEP_MINOR_REV, 232 EEP_TX_MASK, 233 EEP_RX_MASK, 234 EEP_FSTCLK_5G, 235 EEP_RXGAIN_TYPE, 236 EEP_OL_PWRCTRL, 237 EEP_TXGAIN_TYPE, 238 EEP_RC_CHAIN_MASK, 239 EEP_DAC_HPWR_5G, 240 EEP_FRAC_N_5G, 241 EEP_DEV_TYPE, 242 EEP_TEMPSENSE_SLOPE, 243 EEP_TEMPSENSE_SLOPE_PAL_ON, 244 EEP_PWR_TABLE_OFFSET, 245 EEP_PAPRD, 246 EEP_MODAL_VER, 247 EEP_ANT_DIV_CTL1, 248 EEP_CHAIN_MASK_REDUCE, 249 EEP_ANTENNA_GAIN_2G, 250 EEP_ANTENNA_GAIN_5G, 251 }; 252 253 enum ar5416_rates { 254 rate6mb, rate9mb, rate12mb, rate18mb, 255 rate24mb, rate36mb, rate48mb, rate54mb, 256 rate1l, rate2l, rate2s, rate5_5l, 257 rate5_5s, rate11l, rate11s, rateXr, 258 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 259 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 260 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 261 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 262 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 263 Ar5416RateSize 264 }; 265 266 enum ath9k_hal_freq_band { 267 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 268 ATH9K_HAL_FREQ_BAND_2GHZ = 1 269 }; 270 271 struct base_eep_header { 272 u16 length; 273 u16 checksum; 274 u16 version; 275 u8 opCapFlags; 276 u8 eepMisc; 277 u16 regDmn[2]; 278 u8 macAddr[6]; 279 u8 rxMask; 280 u8 txMask; 281 u16 rfSilent; 282 u16 blueToothOptions; 283 u16 deviceCap; 284 u32 binBuildNumber; 285 u8 deviceType; 286 u8 pwdclkind; 287 u8 fastClk5g; 288 u8 divChain; 289 u8 rxGainType; 290 u8 dacHiPwrMode_5G; 291 u8 openLoopPwrCntl; 292 u8 dacLpMode; 293 u8 txGainType; 294 u8 rcChainMask; 295 u8 desiredScaleCCK; 296 u8 pwr_table_offset; 297 u8 frac_n_5g; 298 u8 futureBase_3[21]; 299 } __packed; 300 301 struct base_eep_header_4k { 302 u16 length; 303 u16 checksum; 304 u16 version; 305 u8 opCapFlags; 306 u8 eepMisc; 307 u16 regDmn[2]; 308 u8 macAddr[6]; 309 u8 rxMask; 310 u8 txMask; 311 u16 rfSilent; 312 u16 blueToothOptions; 313 u16 deviceCap; 314 u32 binBuildNumber; 315 u8 deviceType; 316 u8 txGainType; 317 } __packed; 318 319 320 struct spur_chan { 321 u16 spurChan; 322 u8 spurRangeLow; 323 u8 spurRangeHigh; 324 } __packed; 325 326 struct modal_eep_header { 327 u32 antCtrlChain[AR5416_MAX_CHAINS]; 328 u32 antCtrlCommon; 329 u8 antennaGainCh[AR5416_MAX_CHAINS]; 330 u8 switchSettling; 331 u8 txRxAttenCh[AR5416_MAX_CHAINS]; 332 u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 333 u8 adcDesiredSize; 334 u8 pgaDesiredSize; 335 u8 xlnaGainCh[AR5416_MAX_CHAINS]; 336 u8 txEndToXpaOff; 337 u8 txEndToRxOn; 338 u8 txFrameToXpaOn; 339 u8 thresh62; 340 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 341 u8 xpdGain; 342 u8 xpd; 343 u8 iqCalICh[AR5416_MAX_CHAINS]; 344 u8 iqCalQCh[AR5416_MAX_CHAINS]; 345 u8 pdGainOverlap; 346 u8 ob; 347 u8 db; 348 u8 xpaBiasLvl; 349 u8 pwrDecreaseFor2Chain; 350 u8 pwrDecreaseFor3Chain; 351 u8 txFrameToDataStart; 352 u8 txFrameToPaOn; 353 u8 ht40PowerIncForPdadc; 354 u8 bswAtten[AR5416_MAX_CHAINS]; 355 u8 bswMargin[AR5416_MAX_CHAINS]; 356 u8 swSettleHt40; 357 u8 xatten2Db[AR5416_MAX_CHAINS]; 358 u8 xatten2Margin[AR5416_MAX_CHAINS]; 359 u8 ob_ch1; 360 u8 db_ch1; 361 u8 lna_ctl; 362 u8 miscBits; 363 u16 xpaBiasLvlFreq[3]; 364 u8 futureModal[6]; 365 366 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 367 } __packed; 368 369 struct calDataPerFreqOpLoop { 370 u8 pwrPdg[2][5]; 371 u8 vpdPdg[2][5]; 372 u8 pcdac[2][5]; 373 u8 empty[2][5]; 374 } __packed; 375 376 struct modal_eep_4k_header { 377 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 378 u32 antCtrlCommon; 379 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 380 u8 switchSettling; 381 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 382 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 383 u8 adcDesiredSize; 384 u8 pgaDesiredSize; 385 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 386 u8 txEndToXpaOff; 387 u8 txEndToRxOn; 388 u8 txFrameToXpaOn; 389 u8 thresh62; 390 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 391 u8 xpdGain; 392 u8 xpd; 393 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 394 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 395 u8 pdGainOverlap; 396 #ifdef __BIG_ENDIAN_BITFIELD 397 u8 ob_1:4, ob_0:4; 398 u8 db1_1:4, db1_0:4; 399 #else 400 u8 ob_0:4, ob_1:4; 401 u8 db1_0:4, db1_1:4; 402 #endif 403 u8 xpaBiasLvl; 404 u8 txFrameToDataStart; 405 u8 txFrameToPaOn; 406 u8 ht40PowerIncForPdadc; 407 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 408 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 409 u8 swSettleHt40; 410 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 411 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 412 #ifdef __BIG_ENDIAN_BITFIELD 413 u8 db2_1:4, db2_0:4; 414 #else 415 u8 db2_0:4, db2_1:4; 416 #endif 417 u8 version; 418 #ifdef __BIG_ENDIAN_BITFIELD 419 u8 ob_3:4, ob_2:4; 420 u8 antdiv_ctl1:4, ob_4:4; 421 u8 db1_3:4, db1_2:4; 422 u8 antdiv_ctl2:4, db1_4:4; 423 u8 db2_2:4, db2_3:4; 424 u8 reserved:4, db2_4:4; 425 #else 426 u8 ob_2:4, ob_3:4; 427 u8 ob_4:4, antdiv_ctl1:4; 428 u8 db1_2:4, db1_3:4; 429 u8 db1_4:4, antdiv_ctl2:4; 430 u8 db2_2:4, db2_3:4; 431 u8 db2_4:4, reserved:4; 432 #endif 433 u8 tx_diversity; 434 u8 flc_pwr_thresh; 435 u8 bb_scale_smrt_antenna; 436 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 437 u8 futureModal[1]; 438 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 439 } __packed; 440 441 struct base_eep_ar9287_header { 442 u16 length; 443 u16 checksum; 444 u16 version; 445 u8 opCapFlags; 446 u8 eepMisc; 447 u16 regDmn[2]; 448 u8 macAddr[6]; 449 u8 rxMask; 450 u8 txMask; 451 u16 rfSilent; 452 u16 blueToothOptions; 453 u16 deviceCap; 454 u32 binBuildNumber; 455 u8 deviceType; 456 u8 openLoopPwrCntl; 457 int8_t pwrTableOffset; 458 int8_t tempSensSlope; 459 int8_t tempSensSlopePalOn; 460 u8 futureBase[29]; 461 } __packed; 462 463 struct modal_eep_ar9287_header { 464 u32 antCtrlChain[AR9287_MAX_CHAINS]; 465 u32 antCtrlCommon; 466 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 467 u8 switchSettling; 468 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 469 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 470 int8_t adcDesiredSize; 471 u8 txEndToXpaOff; 472 u8 txEndToRxOn; 473 u8 txFrameToXpaOn; 474 u8 thresh62; 475 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 476 u8 xpdGain; 477 u8 xpd; 478 int8_t iqCalICh[AR9287_MAX_CHAINS]; 479 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 480 u8 pdGainOverlap; 481 u8 xpaBiasLvl; 482 u8 txFrameToDataStart; 483 u8 txFrameToPaOn; 484 u8 ht40PowerIncForPdadc; 485 u8 bswAtten[AR9287_MAX_CHAINS]; 486 u8 bswMargin[AR9287_MAX_CHAINS]; 487 u8 swSettleHt40; 488 u8 version; 489 u8 db1; 490 u8 db2; 491 u8 ob_cck; 492 u8 ob_psk; 493 u8 ob_qam; 494 u8 ob_pal_off; 495 u8 futureModal[30]; 496 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 497 } __packed; 498 499 struct cal_data_per_freq { 500 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 501 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 502 } __packed; 503 504 struct cal_data_per_freq_4k { 505 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 506 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 507 } __packed; 508 509 struct cal_target_power_leg { 510 u8 bChannel; 511 u8 tPow2x[4]; 512 } __packed; 513 514 struct cal_target_power_ht { 515 u8 bChannel; 516 u8 tPow2x[8]; 517 } __packed; 518 519 struct cal_ctl_edges { 520 u8 bChannel; 521 u8 ctl; 522 } __packed; 523 524 struct cal_data_op_loop_ar9287 { 525 u8 pwrPdg[2][5]; 526 u8 vpdPdg[2][5]; 527 u8 pcdac[2][5]; 528 u8 empty[2][5]; 529 } __packed; 530 531 struct cal_data_per_freq_ar9287 { 532 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 533 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 534 } __packed; 535 536 union cal_data_per_freq_ar9287_u { 537 struct cal_data_op_loop_ar9287 calDataOpen; 538 struct cal_data_per_freq_ar9287 calDataClose; 539 } __packed; 540 541 struct cal_ctl_data_ar9287 { 542 struct cal_ctl_edges 543 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 544 } __packed; 545 546 struct cal_ctl_data { 547 struct cal_ctl_edges 548 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 549 } __packed; 550 551 struct cal_ctl_data_4k { 552 struct cal_ctl_edges 553 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 554 } __packed; 555 556 struct ar5416_eeprom_def { 557 struct base_eep_header baseEepHeader; 558 u8 custData[64]; 559 struct modal_eep_header modalHeader[2]; 560 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 561 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 562 struct cal_data_per_freq 563 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 564 struct cal_data_per_freq 565 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 566 struct cal_target_power_leg 567 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 568 struct cal_target_power_ht 569 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 570 struct cal_target_power_ht 571 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 572 struct cal_target_power_leg 573 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 574 struct cal_target_power_leg 575 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 576 struct cal_target_power_ht 577 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 578 struct cal_target_power_ht 579 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 580 u8 ctlIndex[AR5416_NUM_CTLS]; 581 struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 582 u8 padding; 583 } __packed; 584 585 struct ar5416_eeprom_4k { 586 struct base_eep_header_4k baseEepHeader; 587 u8 custData[20]; 588 struct modal_eep_4k_header modalHeader; 589 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 590 struct cal_data_per_freq_4k 591 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 592 struct cal_target_power_leg 593 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 594 struct cal_target_power_leg 595 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 596 struct cal_target_power_ht 597 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 598 struct cal_target_power_ht 599 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 600 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 601 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 602 u8 padding; 603 } __packed; 604 605 struct ar9287_eeprom { 606 struct base_eep_ar9287_header baseEepHeader; 607 u8 custData[AR9287_DATA_SZ]; 608 struct modal_eep_ar9287_header modalHeader; 609 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 610 union cal_data_per_freq_ar9287_u 611 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 612 struct cal_target_power_leg 613 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 614 struct cal_target_power_leg 615 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 616 struct cal_target_power_ht 617 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 618 struct cal_target_power_ht 619 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 620 u8 ctlIndex[AR9287_NUM_CTLS]; 621 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 622 u8 padding; 623 } __packed; 624 625 enum reg_ext_bitmap { 626 REG_EXT_FCC_MIDBAND = 0, 627 REG_EXT_JAPAN_MIDBAND = 1, 628 REG_EXT_FCC_DFS_HT40 = 2, 629 REG_EXT_JAPAN_NONDFS_HT40 = 3, 630 REG_EXT_JAPAN_DFS_HT40 = 4 631 }; 632 633 struct ath9k_country_entry { 634 u16 countryCode; 635 u16 regDmnEnum; 636 u16 regDmn5G; 637 u16 regDmn2G; 638 u8 isMultidomain; 639 u8 iso[3]; 640 }; 641 642 struct eeprom_ops { 643 int (*check_eeprom)(struct ath_hw *hw); 644 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 645 bool (*fill_eeprom)(struct ath_hw *hw); 646 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, 647 u32 len, u32 size); 648 int (*get_eeprom_ver)(struct ath_hw *hw); 649 int (*get_eeprom_rev)(struct ath_hw *hw); 650 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 651 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 652 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 653 u16 cfgCtl, u8 twiceAntennaReduction, 654 u8 powerLimit, bool test); 655 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 656 }; 657 658 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 659 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 660 u32 shift, u32 val); 661 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 662 int16_t targetLeft, 663 int16_t targetRight); 664 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 665 u16 *indexL, u16 *indexR); 666 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 667 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, 668 int eep_start_loc, int size); 669 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 670 u8 *pVpdList, u16 numIntercepts, 671 u8 *pRetVpdList); 672 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 673 struct ath9k_channel *chan, 674 struct cal_target_power_leg *powInfo, 675 u16 numChannels, 676 struct cal_target_power_leg *pNewPower, 677 u16 numRates, bool isExtTarget); 678 void ath9k_hw_get_target_powers(struct ath_hw *ah, 679 struct ath9k_channel *chan, 680 struct cal_target_power_ht *powInfo, 681 u16 numChannels, 682 struct cal_target_power_ht *pNewPower, 683 u16 numRates, bool isHt40Target); 684 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 685 bool is2GHz, int num_band_edges); 686 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, 687 u8 antenna_reduction); 688 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 689 int ath9k_hw_eeprom_init(struct ath_hw *ah); 690 691 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 692 struct ath9k_channel *chan, 693 void *pRawDataSet, 694 u8 *bChans, u16 availPiers, 695 u16 tPdGainOverlap, 696 u16 *pPdGainBoundaries, u8 *pPDADCValues, 697 u16 numXpdGains); 698 699 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 700 { 701 if (fbin == AR5416_BCHAN_UNUSED) 702 return fbin; 703 704 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 705 } 706 707 #define ar5416_get_ntxchains(_txchainmask) \ 708 (((_txchainmask >> 2) & 1) + \ 709 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 710 711 extern const struct eeprom_ops eep_def_ops; 712 extern const struct eeprom_ops eep_4k_ops; 713 extern const struct eeprom_ops eep_ar9287_ops; 714 extern const struct eeprom_ops eep_ar9287_ops; 715 extern const struct eeprom_ops eep_ar9300_ops; 716 717 #endif /* EEPROM_H */ 718