1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef EEPROM_H 18 #define EEPROM_H 19 20 #include "../ath.h" 21 #include <net/cfg80211.h> 22 23 #define AH_USE_EEPROM 0x1 24 25 #ifdef __BIG_ENDIAN 26 #define AR5416_EEPROM_MAGIC 0x5aa5 27 #else 28 #define AR5416_EEPROM_MAGIC 0xa55a 29 #endif 30 31 #define CTRY_DEBUG 0x1ff 32 #define CTRY_DEFAULT 0 33 34 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 35 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 36 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 37 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 38 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 39 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 40 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 41 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 42 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 43 44 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 46 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 47 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 50 51 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 52 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 53 54 #define AR5416_EEPROM_MAGIC_OFFSET 0x0 55 #define AR5416_EEPROM_S 2 56 #define AR5416_EEPROM_OFFSET 0x2000 57 #define AR5416_EEPROM_MAX 0xae0 58 59 #define AR5416_EEPROM_START_ADDR \ 60 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 61 62 #define SD_NO_CTL 0xE0 63 #define NO_CTL 0xff 64 #define CTL_MODE_M 7 65 #define CTL_11A 0 66 #define CTL_11B 1 67 #define CTL_11G 2 68 #define CTL_2GHT20 5 69 #define CTL_5GHT20 6 70 #define CTL_2GHT40 7 71 #define CTL_5GHT40 8 72 73 #define EXT_ADDITIVE (0x8000) 74 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 75 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 76 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 77 78 #define SUB_NUM_CTL_MODES_AT_5G_40 2 79 #define SUB_NUM_CTL_MODES_AT_2G_40 3 80 81 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 82 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ 83 84 /* 85 * For AR9285 and later chipsets, the following bits are not being programmed 86 * in EEPROM and so need to be enabled always. 87 * 88 * Bit 0: en_fcc_mid 89 * Bit 1: en_jap_mid 90 * Bit 2: en_fcc_dfs_ht40 91 * Bit 3: en_jap_ht40 92 * Bit 4: en_jap_dfs_ht40 93 */ 94 #define AR9285_RDEXT_DEFAULT 0x1F 95 96 #define AR_EEPROM_MAC(i) (0x1d+(i)) 97 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 98 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 99 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 100 101 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 102 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 104 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \ 105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 106 107 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 108 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 109 #define AR_EEPROM_RFSILENT_POLARITY 0x0002 110 #define AR_EEPROM_RFSILENT_POLARITY_S 1 111 112 #define EEP_RFSILENT_ENABLED 0x0001 113 #define EEP_RFSILENT_ENABLED_S 0 114 #define EEP_RFSILENT_POLARITY 0x0002 115 #define EEP_RFSILENT_POLARITY_S 1 116 #define EEP_RFSILENT_GPIO_SEL 0x001c 117 #define EEP_RFSILENT_GPIO_SEL_S 2 118 119 #define AR5416_OPFLAGS_11A 0x01 120 #define AR5416_OPFLAGS_11G 0x02 121 #define AR5416_OPFLAGS_N_5G_HT40 0x04 122 #define AR5416_OPFLAGS_N_2G_HT40 0x08 123 #define AR5416_OPFLAGS_N_5G_HT20 0x10 124 #define AR5416_OPFLAGS_N_2G_HT20 0x20 125 126 #define AR5416_EEP_NO_BACK_VER 0x1 127 #define AR5416_EEP_VER 0xE 128 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF 129 #define AR5416_EEP_MINOR_VER_2 0x2 130 #define AR5416_EEP_MINOR_VER_3 0x3 131 #define AR5416_EEP_MINOR_VER_7 0x7 132 #define AR5416_EEP_MINOR_VER_9 0x9 133 #define AR5416_EEP_MINOR_VER_16 0x10 134 #define AR5416_EEP_MINOR_VER_17 0x11 135 #define AR5416_EEP_MINOR_VER_19 0x13 136 #define AR5416_EEP_MINOR_VER_20 0x14 137 #define AR5416_EEP_MINOR_VER_21 0x15 138 #define AR5416_EEP_MINOR_VER_22 0x16 139 140 #define AR5416_NUM_5G_CAL_PIERS 8 141 #define AR5416_NUM_2G_CAL_PIERS 4 142 #define AR5416_NUM_5G_20_TARGET_POWERS 8 143 #define AR5416_NUM_5G_40_TARGET_POWERS 8 144 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 145 #define AR5416_NUM_2G_20_TARGET_POWERS 4 146 #define AR5416_NUM_2G_40_TARGET_POWERS 4 147 #define AR5416_NUM_CTLS 24 148 #define AR5416_NUM_BAND_EDGES 8 149 #define AR5416_NUM_PD_GAINS 4 150 #define AR5416_PD_GAINS_IN_MASK 4 151 #define AR5416_PD_GAIN_ICEPTS 5 152 #define AR5416_EEPROM_MODAL_SPURS 5 153 #define AR5416_MAX_RATE_POWER 63 154 #define AR5416_NUM_PDADC_VALUES 128 155 #define AR5416_BCHAN_UNUSED 0xFF 156 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 157 #define AR5416_MAX_CHAINS 3 158 #define AR5416_PWR_TABLE_OFFSET_DB -5 159 160 /* Rx gain type values */ 161 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 162 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 163 #define AR5416_EEP_RXGAIN_ORIG 2 164 165 /* Tx gain type values */ 166 #define AR5416_EEP_TXGAIN_ORIGINAL 0 167 #define AR5416_EEP_TXGAIN_HIGH_POWER 1 168 169 #define AR5416_EEP4K_START_LOC 64 170 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 171 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 172 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 173 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 174 #define AR5416_EEP4K_NUM_CTLS 12 175 #define AR5416_EEP4K_NUM_BAND_EDGES 4 176 #define AR5416_EEP4K_NUM_PD_GAINS 2 177 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4 178 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5 179 #define AR5416_EEP4K_MAX_CHAINS 1 180 181 #define AR9280_TX_GAIN_TABLE_SIZE 22 182 183 #define AR9287_EEP_VER 0xE 184 #define AR9287_EEP_VER_MINOR_MASK 0xFFF 185 #define AR9287_EEP_MINOR_VER_1 0x1 186 #define AR9287_EEP_MINOR_VER_2 0x2 187 #define AR9287_EEP_MINOR_VER_3 0x3 188 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 189 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 190 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 191 192 #define AR9287_EEP_START_LOC 128 193 #define AR9287_NUM_2G_CAL_PIERS 3 194 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 195 #define AR9287_NUM_2G_20_TARGET_POWERS 3 196 #define AR9287_NUM_2G_40_TARGET_POWERS 3 197 #define AR9287_NUM_CTLS 12 198 #define AR9287_NUM_BAND_EDGES 4 199 #define AR9287_NUM_PD_GAINS 4 200 #define AR9287_PD_GAINS_IN_MASK 4 201 #define AR9287_PD_GAIN_ICEPTS 1 202 #define AR9287_EEPROM_MODAL_SPURS 5 203 #define AR9287_MAX_RATE_POWER 63 204 #define AR9287_NUM_PDADC_VALUES 128 205 #define AR9287_NUM_RATES 16 206 #define AR9287_BCHAN_UNUSED 0xFF 207 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64 208 #define AR9287_OPFLAGS_11A 0x01 209 #define AR9287_OPFLAGS_11G 0x02 210 #define AR9287_OPFLAGS_2G_HT40 0x08 211 #define AR9287_OPFLAGS_2G_HT20 0x20 212 #define AR9287_OPFLAGS_5G_HT40 0x04 213 #define AR9287_OPFLAGS_5G_HT20 0x10 214 #define AR9287_EEPMISC_BIG_ENDIAN 0x01 215 #define AR9287_EEPMISC_WOW 0x02 216 #define AR9287_MAX_CHAINS 2 217 #define AR9287_ANT_16S 32 218 #define AR9287_custdatasize 20 219 220 #define AR9287_NUM_ANT_CHAIN_FIELDS 6 221 #define AR9287_NUM_ANT_COMMON_FIELDS 4 222 #define AR9287_SIZE_ANT_CHAIN_FIELD 2 223 #define AR9287_SIZE_ANT_COMMON_FIELD 4 224 #define AR9287_ANT_CHAIN_MASK 0x3 225 #define AR9287_ANT_COMMON_MASK 0xf 226 #define AR9287_CHAIN_0_IDX 0 227 #define AR9287_CHAIN_1_IDX 1 228 #define AR9287_DATA_SZ 32 229 230 #define AR9287_PWR_TABLE_OFFSET_DB -5 231 232 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 233 234 enum eeprom_param { 235 EEP_NFTHRESH_5, 236 EEP_NFTHRESH_2, 237 EEP_MAC_MSW, 238 EEP_MAC_MID, 239 EEP_MAC_LSW, 240 EEP_REG_0, 241 EEP_REG_1, 242 EEP_OP_CAP, 243 EEP_OP_MODE, 244 EEP_RF_SILENT, 245 EEP_OB_5, 246 EEP_DB_5, 247 EEP_OB_2, 248 EEP_DB_2, 249 EEP_MINOR_REV, 250 EEP_TX_MASK, 251 EEP_RX_MASK, 252 EEP_RXGAIN_TYPE, 253 EEP_TXGAIN_TYPE, 254 EEP_OL_PWRCTRL, 255 EEP_RC_CHAIN_MASK, 256 EEP_DAC_HPWR_5G, 257 EEP_FRAC_N_5G, 258 EEP_DEV_TYPE, 259 EEP_TEMPSENSE_SLOPE, 260 EEP_TEMPSENSE_SLOPE_PAL_ON, 261 EEP_PWR_TABLE_OFFSET 262 }; 263 264 enum ar5416_rates { 265 rate6mb, rate9mb, rate12mb, rate18mb, 266 rate24mb, rate36mb, rate48mb, rate54mb, 267 rate1l, rate2l, rate2s, rate5_5l, 268 rate5_5s, rate11l, rate11s, rateXr, 269 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 270 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 271 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 272 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 273 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 274 Ar5416RateSize 275 }; 276 277 enum ath9k_hal_freq_band { 278 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 279 ATH9K_HAL_FREQ_BAND_2GHZ = 1 280 }; 281 282 struct base_eep_header { 283 u16 length; 284 u16 checksum; 285 u16 version; 286 u8 opCapFlags; 287 u8 eepMisc; 288 u16 regDmn[2]; 289 u8 macAddr[6]; 290 u8 rxMask; 291 u8 txMask; 292 u16 rfSilent; 293 u16 blueToothOptions; 294 u16 deviceCap; 295 u32 binBuildNumber; 296 u8 deviceType; 297 u8 pwdclkind; 298 u8 futureBase_1[2]; 299 u8 rxGainType; 300 u8 dacHiPwrMode_5G; 301 u8 openLoopPwrCntl; 302 u8 dacLpMode; 303 u8 txGainType; 304 u8 rcChainMask; 305 u8 desiredScaleCCK; 306 u8 pwr_table_offset; 307 u8 frac_n_5g; 308 u8 futureBase_3[21]; 309 } __packed; 310 311 struct base_eep_header_4k { 312 u16 length; 313 u16 checksum; 314 u16 version; 315 u8 opCapFlags; 316 u8 eepMisc; 317 u16 regDmn[2]; 318 u8 macAddr[6]; 319 u8 rxMask; 320 u8 txMask; 321 u16 rfSilent; 322 u16 blueToothOptions; 323 u16 deviceCap; 324 u32 binBuildNumber; 325 u8 deviceType; 326 u8 txGainType; 327 } __packed; 328 329 330 struct spur_chan { 331 u16 spurChan; 332 u8 spurRangeLow; 333 u8 spurRangeHigh; 334 } __packed; 335 336 struct modal_eep_header { 337 u32 antCtrlChain[AR5416_MAX_CHAINS]; 338 u32 antCtrlCommon; 339 u8 antennaGainCh[AR5416_MAX_CHAINS]; 340 u8 switchSettling; 341 u8 txRxAttenCh[AR5416_MAX_CHAINS]; 342 u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 343 u8 adcDesiredSize; 344 u8 pgaDesiredSize; 345 u8 xlnaGainCh[AR5416_MAX_CHAINS]; 346 u8 txEndToXpaOff; 347 u8 txEndToRxOn; 348 u8 txFrameToXpaOn; 349 u8 thresh62; 350 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 351 u8 xpdGain; 352 u8 xpd; 353 u8 iqCalICh[AR5416_MAX_CHAINS]; 354 u8 iqCalQCh[AR5416_MAX_CHAINS]; 355 u8 pdGainOverlap; 356 u8 ob; 357 u8 db; 358 u8 xpaBiasLvl; 359 u8 pwrDecreaseFor2Chain; 360 u8 pwrDecreaseFor3Chain; 361 u8 txFrameToDataStart; 362 u8 txFrameToPaOn; 363 u8 ht40PowerIncForPdadc; 364 u8 bswAtten[AR5416_MAX_CHAINS]; 365 u8 bswMargin[AR5416_MAX_CHAINS]; 366 u8 swSettleHt40; 367 u8 xatten2Db[AR5416_MAX_CHAINS]; 368 u8 xatten2Margin[AR5416_MAX_CHAINS]; 369 u8 ob_ch1; 370 u8 db_ch1; 371 u8 useAnt1:1, 372 force_xpaon:1, 373 local_bias:1, 374 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; 375 u8 miscBits; 376 u16 xpaBiasLvlFreq[3]; 377 u8 futureModal[6]; 378 379 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 380 } __packed; 381 382 struct calDataPerFreqOpLoop { 383 u8 pwrPdg[2][5]; 384 u8 vpdPdg[2][5]; 385 u8 pcdac[2][5]; 386 u8 empty[2][5]; 387 } __packed; 388 389 struct modal_eep_4k_header { 390 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 391 u32 antCtrlCommon; 392 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 393 u8 switchSettling; 394 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 395 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 396 u8 adcDesiredSize; 397 u8 pgaDesiredSize; 398 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 399 u8 txEndToXpaOff; 400 u8 txEndToRxOn; 401 u8 txFrameToXpaOn; 402 u8 thresh62; 403 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 404 u8 xpdGain; 405 u8 xpd; 406 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 407 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 408 u8 pdGainOverlap; 409 #ifdef __BIG_ENDIAN_BITFIELD 410 u8 ob_1:4, ob_0:4; 411 u8 db1_1:4, db1_0:4; 412 #else 413 u8 ob_0:4, ob_1:4; 414 u8 db1_0:4, db1_1:4; 415 #endif 416 u8 xpaBiasLvl; 417 u8 txFrameToDataStart; 418 u8 txFrameToPaOn; 419 u8 ht40PowerIncForPdadc; 420 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 421 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 422 u8 swSettleHt40; 423 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 424 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 425 #ifdef __BIG_ENDIAN_BITFIELD 426 u8 db2_1:4, db2_0:4; 427 #else 428 u8 db2_0:4, db2_1:4; 429 #endif 430 u8 version; 431 #ifdef __BIG_ENDIAN_BITFIELD 432 u8 ob_3:4, ob_2:4; 433 u8 antdiv_ctl1:4, ob_4:4; 434 u8 db1_3:4, db1_2:4; 435 u8 antdiv_ctl2:4, db1_4:4; 436 u8 db2_2:4, db2_3:4; 437 u8 reserved:4, db2_4:4; 438 #else 439 u8 ob_2:4, ob_3:4; 440 u8 ob_4:4, antdiv_ctl1:4; 441 u8 db1_2:4, db1_3:4; 442 u8 db1_4:4, antdiv_ctl2:4; 443 u8 db2_2:4, db2_3:4; 444 u8 db2_4:4, reserved:4; 445 #endif 446 u8 futureModal[4]; 447 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 448 } __packed; 449 450 struct base_eep_ar9287_header { 451 u16 length; 452 u16 checksum; 453 u16 version; 454 u8 opCapFlags; 455 u8 eepMisc; 456 u16 regDmn[2]; 457 u8 macAddr[6]; 458 u8 rxMask; 459 u8 txMask; 460 u16 rfSilent; 461 u16 blueToothOptions; 462 u16 deviceCap; 463 u32 binBuildNumber; 464 u8 deviceType; 465 u8 openLoopPwrCntl; 466 int8_t pwrTableOffset; 467 int8_t tempSensSlope; 468 int8_t tempSensSlopePalOn; 469 u8 futureBase[29]; 470 } __packed; 471 472 struct modal_eep_ar9287_header { 473 u32 antCtrlChain[AR9287_MAX_CHAINS]; 474 u32 antCtrlCommon; 475 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 476 u8 switchSettling; 477 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 478 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 479 int8_t adcDesiredSize; 480 u8 txEndToXpaOff; 481 u8 txEndToRxOn; 482 u8 txFrameToXpaOn; 483 u8 thresh62; 484 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 485 u8 xpdGain; 486 u8 xpd; 487 int8_t iqCalICh[AR9287_MAX_CHAINS]; 488 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 489 u8 pdGainOverlap; 490 u8 xpaBiasLvl; 491 u8 txFrameToDataStart; 492 u8 txFrameToPaOn; 493 u8 ht40PowerIncForPdadc; 494 u8 bswAtten[AR9287_MAX_CHAINS]; 495 u8 bswMargin[AR9287_MAX_CHAINS]; 496 u8 swSettleHt40; 497 u8 version; 498 u8 db1; 499 u8 db2; 500 u8 ob_cck; 501 u8 ob_psk; 502 u8 ob_qam; 503 u8 ob_pal_off; 504 u8 futureModal[30]; 505 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; 506 } __packed; 507 508 struct cal_data_per_freq { 509 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 510 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 511 } __packed; 512 513 struct cal_data_per_freq_4k { 514 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 515 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 516 } __packed; 517 518 struct cal_target_power_leg { 519 u8 bChannel; 520 u8 tPow2x[4]; 521 } __packed; 522 523 struct cal_target_power_ht { 524 u8 bChannel; 525 u8 tPow2x[8]; 526 } __packed; 527 528 529 #ifdef __BIG_ENDIAN_BITFIELD 530 struct cal_ctl_edges { 531 u8 bChannel; 532 u8 flag:2, tPower:6; 533 } __packed; 534 #else 535 struct cal_ctl_edges { 536 u8 bChannel; 537 u8 tPower:6, flag:2; 538 } __packed; 539 #endif 540 541 struct cal_data_op_loop_ar9287 { 542 u8 pwrPdg[2][5]; 543 u8 vpdPdg[2][5]; 544 u8 pcdac[2][5]; 545 u8 empty[2][5]; 546 } __packed; 547 548 struct cal_data_per_freq_ar9287 { 549 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 550 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 551 } __packed; 552 553 union cal_data_per_freq_ar9287_u { 554 struct cal_data_op_loop_ar9287 calDataOpen; 555 struct cal_data_per_freq_ar9287 calDataClose; 556 } __packed; 557 558 struct cal_ctl_data_ar9287 { 559 struct cal_ctl_edges 560 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 561 } __packed; 562 563 struct cal_ctl_data { 564 struct cal_ctl_edges 565 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 566 } __packed; 567 568 struct cal_ctl_data_4k { 569 struct cal_ctl_edges 570 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 571 } __packed; 572 573 struct ar5416_eeprom_def { 574 struct base_eep_header baseEepHeader; 575 u8 custData[64]; 576 struct modal_eep_header modalHeader[2]; 577 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 578 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 579 struct cal_data_per_freq 580 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 581 struct cal_data_per_freq 582 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 583 struct cal_target_power_leg 584 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 585 struct cal_target_power_ht 586 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 587 struct cal_target_power_ht 588 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 589 struct cal_target_power_leg 590 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 591 struct cal_target_power_leg 592 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 593 struct cal_target_power_ht 594 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 595 struct cal_target_power_ht 596 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 597 u8 ctlIndex[AR5416_NUM_CTLS]; 598 struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 599 u8 padding; 600 } __packed; 601 602 struct ar5416_eeprom_4k { 603 struct base_eep_header_4k baseEepHeader; 604 u8 custData[20]; 605 struct modal_eep_4k_header modalHeader; 606 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 607 struct cal_data_per_freq_4k 608 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 609 struct cal_target_power_leg 610 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 611 struct cal_target_power_leg 612 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 613 struct cal_target_power_ht 614 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 615 struct cal_target_power_ht 616 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 617 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 618 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 619 u8 padding; 620 } __packed; 621 622 struct ar9287_eeprom { 623 struct base_eep_ar9287_header baseEepHeader; 624 u8 custData[AR9287_DATA_SZ]; 625 struct modal_eep_ar9287_header modalHeader; 626 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 627 union cal_data_per_freq_ar9287_u 628 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 629 struct cal_target_power_leg 630 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 631 struct cal_target_power_leg 632 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 633 struct cal_target_power_ht 634 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 635 struct cal_target_power_ht 636 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 637 u8 ctlIndex[AR9287_NUM_CTLS]; 638 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 639 u8 padding; 640 } __packed; 641 642 enum reg_ext_bitmap { 643 REG_EXT_FCC_MIDBAND = 0, 644 REG_EXT_JAPAN_MIDBAND = 1, 645 REG_EXT_FCC_DFS_HT40 = 2, 646 REG_EXT_JAPAN_NONDFS_HT40 = 3, 647 REG_EXT_JAPAN_DFS_HT40 = 4 648 }; 649 650 struct ath9k_country_entry { 651 u16 countryCode; 652 u16 regDmnEnum; 653 u16 regDmn5G; 654 u16 regDmn2G; 655 u8 isMultidomain; 656 u8 iso[3]; 657 }; 658 659 enum ath9k_eep_map { 660 EEP_MAP_DEFAULT = 0x0, 661 EEP_MAP_4KBITS, 662 EEP_MAP_AR9287, 663 EEP_MAP_MAX 664 }; 665 666 struct eeprom_ops { 667 int (*check_eeprom)(struct ath_hw *hw); 668 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 669 bool (*fill_eeprom)(struct ath_hw *hw); 670 int (*get_eeprom_ver)(struct ath_hw *hw); 671 int (*get_eeprom_rev)(struct ath_hw *hw); 672 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); 673 u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, 674 struct ath9k_channel *chan); 675 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 676 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 677 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 678 u16 cfgCtl, u8 twiceAntennaReduction, 679 u8 twiceMaxRegulatoryPower, u8 powerLimit); 680 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 681 }; 682 683 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 684 u32 shift, u32 val); 685 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 686 int16_t targetLeft, 687 int16_t targetRight); 688 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 689 u16 *indexL, u16 *indexR); 690 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data); 691 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 692 u8 *pVpdList, u16 numIntercepts, 693 u8 *pRetVpdList); 694 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 695 struct ath9k_channel *chan, 696 struct cal_target_power_leg *powInfo, 697 u16 numChannels, 698 struct cal_target_power_leg *pNewPower, 699 u16 numRates, bool isExtTarget); 700 void ath9k_hw_get_target_powers(struct ath_hw *ah, 701 struct ath9k_channel *chan, 702 struct cal_target_power_ht *powInfo, 703 u16 numChannels, 704 struct cal_target_power_ht *pNewPower, 705 u16 numRates, bool isHt40Target); 706 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 707 bool is2GHz, int num_band_edges); 708 int ath9k_hw_eeprom_init(struct ath_hw *ah); 709 710 #define ar5416_get_ntxchains(_txchainmask) \ 711 (((_txchainmask >> 2) & 1) + \ 712 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 713 714 extern const struct eeprom_ops eep_def_ops; 715 extern const struct eeprom_ops eep_4k_ops; 716 extern const struct eeprom_ops eep_AR9287_ops; 717 718 #endif /* EEPROM_H */ 719