1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "rc.h" 22 #include "dfs_debug.h" 23 24 struct ath_txq; 25 struct ath_buf; 26 struct fft_sample_tlv; 27 28 #ifdef CONFIG_ATH9K_DEBUGFS 29 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 30 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++ 31 #else 32 #define TX_STAT_INC(q, c) do { } while (0) 33 #define RESET_STAT_INC(sc, type) do { } while (0) 34 #endif 35 36 enum ath_reset_type { 37 RESET_TYPE_BB_HANG, 38 RESET_TYPE_BB_WATCHDOG, 39 RESET_TYPE_FATAL_INT, 40 RESET_TYPE_TX_ERROR, 41 RESET_TYPE_TX_HANG, 42 RESET_TYPE_PLL_HANG, 43 RESET_TYPE_MAC_HANG, 44 RESET_TYPE_BEACON_STUCK, 45 RESET_TYPE_MCI, 46 __RESET_TYPE_MAX 47 }; 48 49 #ifdef CONFIG_ATH9K_DEBUGFS 50 51 /** 52 * struct ath_interrupt_stats - Contains statistics about interrupts 53 * @total: Total no. of interrupts generated so far 54 * @rxok: RX with no errors 55 * @rxlp: RX with low priority RX 56 * @rxhp: RX with high priority, uapsd only 57 * @rxeol: RX with no more RXDESC available 58 * @rxorn: RX FIFO overrun 59 * @txok: TX completed at the requested rate 60 * @txurn: TX FIFO underrun 61 * @mib: MIB regs reaching its threshold 62 * @rxphyerr: RX with phy errors 63 * @rx_keycache_miss: RX with key cache misses 64 * @swba: Software Beacon Alert 65 * @bmiss: Beacon Miss 66 * @bnr: Beacon Not Ready 67 * @cst: Carrier Sense TImeout 68 * @gtt: Global TX Timeout 69 * @tim: RX beacon TIM occurrence 70 * @cabend: RX End of CAB traffic 71 * @dtimsync: DTIM sync lossage 72 * @dtim: RX Beacon with DTIM 73 * @bb_watchdog: Baseband watchdog 74 * @tsfoor: TSF out of range, indicates that the corrected TSF received 75 * from a beacon differs from the PCU's internal TSF by more than a 76 * (programmable) threshold 77 * @local_timeout: Internal bus timeout. 78 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets 79 * @gen_timer: Generic hardware timer interrupt 80 */ 81 struct ath_interrupt_stats { 82 u32 total; 83 u32 rxok; 84 u32 rxlp; 85 u32 rxhp; 86 u32 rxeol; 87 u32 rxorn; 88 u32 txok; 89 u32 txeol; 90 u32 txurn; 91 u32 mib; 92 u32 rxphyerr; 93 u32 rx_keycache_miss; 94 u32 swba; 95 u32 bmiss; 96 u32 bnr; 97 u32 cst; 98 u32 gtt; 99 u32 tim; 100 u32 cabend; 101 u32 dtimsync; 102 u32 dtim; 103 u32 bb_watchdog; 104 u32 tsfoor; 105 u32 mci; 106 u32 gen_timer; 107 108 /* Sync-cause stats */ 109 u32 sync_cause_all; 110 u32 sync_rtc_irq; 111 u32 sync_mac_irq; 112 u32 eeprom_illegal_access; 113 u32 apb_timeout; 114 u32 pci_mode_conflict; 115 u32 host1_fatal; 116 u32 host1_perr; 117 u32 trcv_fifo_perr; 118 u32 radm_cpl_ep; 119 u32 radm_cpl_dllp_abort; 120 u32 radm_cpl_tlp_abort; 121 u32 radm_cpl_ecrc_err; 122 u32 radm_cpl_timeout; 123 u32 local_timeout; 124 u32 pm_access; 125 u32 mac_awake; 126 u32 mac_asleep; 127 u32 mac_sleep_access; 128 }; 129 130 131 /** 132 * struct ath_tx_stats - Statistics about TX 133 * @tx_pkts_all: No. of total frames transmitted, including ones that 134 may have had errors. 135 * @tx_bytes_all: No. of total bytes transmitted, including ones that 136 may have had errors. 137 * @queued: Total MPDUs (non-aggr) queued 138 * @completed: Total MPDUs (non-aggr) completed 139 * @a_aggr: Total no. of aggregates queued 140 * @a_queued_hw: Total AMPDUs queued to hardware 141 * @a_queued_sw: Total AMPDUs queued to software queues 142 * @a_completed: Total AMPDUs completed 143 * @a_retries: No. of AMPDUs retried (SW) 144 * @a_xretries: No. of AMPDUs dropped due to xretries 145 * @txerr_filtered: No. of frames with TXERR_FILT flag set. 146 * @fifo_underrun: FIFO underrun occurrences 147 Valid only for: 148 - non-aggregate condition. 149 - first packet of aggregate. 150 * @xtxop: No. of frames filtered because of TXOP limit 151 * @timer_exp: Transmit timer expiry 152 * @desc_cfg_err: Descriptor configuration errors 153 * @data_urn: TX data underrun errors 154 * @delim_urn: TX delimiter underrun errors 155 * @puttxbuf: Number of times hardware was given txbuf to write. 156 * @txstart: Number of times hardware was told to start tx. 157 * @txprocdesc: Number of times tx descriptor was processed 158 * @txfailed: Out-of-memory or other errors in xmit path. 159 */ 160 struct ath_tx_stats { 161 u32 tx_pkts_all; 162 u32 tx_bytes_all; 163 u32 queued; 164 u32 completed; 165 u32 xretries; 166 u32 a_aggr; 167 u32 a_queued_hw; 168 u32 a_queued_sw; 169 u32 a_completed; 170 u32 a_retries; 171 u32 a_xretries; 172 u32 txerr_filtered; 173 u32 fifo_underrun; 174 u32 xtxop; 175 u32 timer_exp; 176 u32 desc_cfg_err; 177 u32 data_underrun; 178 u32 delim_underrun; 179 u32 puttxbuf; 180 u32 txstart; 181 u32 txprocdesc; 182 u32 txfailed; 183 }; 184 185 /* 186 * Various utility macros to print TX/Queue counters. 187 */ 188 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum 189 #define TXSTATS sc->debug.stats.txstats 190 #define PR(str, elem) \ 191 do { \ 192 len += snprintf(buf + len, size - len, \ 193 "%s%13u%11u%10u%10u\n", str, \ 194 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem, \ 195 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem, \ 196 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem, \ 197 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \ 198 } while(0) 199 200 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++) 201 202 /** 203 * struct ath_rx_stats - RX Statistics 204 * @rx_pkts_all: No. of total frames received, including ones that 205 may have had errors. 206 * @rx_bytes_all: No. of total bytes received, including ones that 207 may have had errors. 208 * @crc_err: No. of frames with incorrect CRC value 209 * @decrypt_crc_err: No. of frames whose CRC check failed after 210 decryption process completed 211 * @phy_err: No. of frames whose reception failed because the PHY 212 encountered an error 213 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 214 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 215 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 216 * @decrypt_busy_err: Decryption interruptions counter 217 * @phy_err_stats: Individual PHY error statistics 218 * @rx_len_err: No. of frames discarded due to bad length. 219 * @rx_oom_err: No. of frames dropped due to OOM issues. 220 * @rx_rate_err: No. of frames dropped due to rate errors. 221 * @rx_too_many_frags_err: Frames dropped due to too-many-frags received. 222 * @rx_beacons: No. of beacons received. 223 * @rx_frags: No. of rx-fragements received. 224 * @rx_spectral: No of spectral packets received. 225 */ 226 struct ath_rx_stats { 227 u32 rx_pkts_all; 228 u32 rx_bytes_all; 229 u32 crc_err; 230 u32 decrypt_crc_err; 231 u32 phy_err; 232 u32 mic_err; 233 u32 pre_delim_crc_err; 234 u32 post_delim_crc_err; 235 u32 decrypt_busy_err; 236 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 237 u32 rx_len_err; 238 u32 rx_oom_err; 239 u32 rx_rate_err; 240 u32 rx_too_many_frags_err; 241 u32 rx_beacons; 242 u32 rx_frags; 243 u32 rx_spectral; 244 }; 245 246 struct ath_stats { 247 struct ath_interrupt_stats istats; 248 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 249 struct ath_rx_stats rxstats; 250 struct ath_dfs_stats dfs_stats; 251 u32 reset[__RESET_TYPE_MAX]; 252 }; 253 254 #define ATH_DBG_MAX_SAMPLES 10 255 struct ath_dbg_bb_mac_samp { 256 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS]; 257 u32 pcu_obs, pcu_cr, noise; 258 struct { 259 u64 jiffies; 260 int8_t rssi_ctl0; 261 int8_t rssi_ctl1; 262 int8_t rssi_ctl2; 263 int8_t rssi_ext0; 264 int8_t rssi_ext1; 265 int8_t rssi_ext2; 266 int8_t rssi; 267 bool isok; 268 u8 rts_fail_cnt; 269 u8 data_fail_cnt; 270 u8 rateindex; 271 u8 qid; 272 u8 tid; 273 u32 ba_low; 274 u32 ba_high; 275 } ts[ATH_DBG_MAX_SAMPLES]; 276 struct { 277 u64 jiffies; 278 int8_t rssi_ctl0; 279 int8_t rssi_ctl1; 280 int8_t rssi_ctl2; 281 int8_t rssi_ext0; 282 int8_t rssi_ext1; 283 int8_t rssi_ext2; 284 int8_t rssi; 285 bool is_mybeacon; 286 u8 antenna; 287 u8 rate; 288 } rs[ATH_DBG_MAX_SAMPLES]; 289 struct ath_cycle_counters cc; 290 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 291 }; 292 293 struct ath9k_debug { 294 struct dentry *debugfs_phy; 295 u32 regidx; 296 struct ath_stats stats; 297 #ifdef CONFIG_ATH9K_MAC_DEBUG 298 spinlock_t samp_lock; 299 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES]; 300 u8 sampidx; 301 u8 tsidx; 302 u8 rsidx; 303 #endif 304 }; 305 306 int ath9k_init_debug(struct ath_hw *ah); 307 void ath9k_deinit_debug(struct ath_softc *sc); 308 309 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 310 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 311 struct ath_tx_status *ts, struct ath_txq *txq, 312 unsigned int flags); 313 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 314 int ath9k_get_et_sset_count(struct ieee80211_hw *hw, 315 struct ieee80211_vif *vif, int sset); 316 void ath9k_get_et_stats(struct ieee80211_hw *hw, 317 struct ieee80211_vif *vif, 318 struct ethtool_stats *stats, u64 *data); 319 void ath9k_get_et_strings(struct ieee80211_hw *hw, 320 struct ieee80211_vif *vif, 321 u32 sset, u8 *data); 322 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw, 323 struct ieee80211_vif *vif, 324 struct ieee80211_sta *sta, 325 struct dentry *dir); 326 void ath9k_sta_remove_debugfs(struct ieee80211_hw *hw, 327 struct ieee80211_vif *vif, 328 struct ieee80211_sta *sta, 329 struct dentry *dir); 330 331 void ath_debug_send_fft_sample(struct ath_softc *sc, 332 struct fft_sample_tlv *fft_sample); 333 334 #else 335 336 #define RX_STAT_INC(c) /* NOP */ 337 338 static inline int ath9k_init_debug(struct ath_hw *ah) 339 { 340 return 0; 341 } 342 343 static inline void ath9k_deinit_debug(struct ath_softc *sc) 344 { 345 } 346 347 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 348 enum ath9k_int status) 349 { 350 } 351 352 static inline void ath_debug_stat_tx(struct ath_softc *sc, 353 struct ath_buf *bf, 354 struct ath_tx_status *ts, 355 struct ath_txq *txq, 356 unsigned int flags) 357 { 358 } 359 360 static inline void ath_debug_stat_rx(struct ath_softc *sc, 361 struct ath_rx_status *rs) 362 { 363 } 364 365 #endif /* CONFIG_ATH9K_DEBUGFS */ 366 367 #ifdef CONFIG_ATH9K_MAC_DEBUG 368 369 void ath9k_debug_samp_bb_mac(struct ath_softc *sc); 370 371 #else 372 373 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc) 374 { 375 } 376 377 #endif 378 379 380 #endif /* DEBUG_H */ 381