1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "dfs_debug.h" 22 23 struct ath_txq; 24 struct ath_buf; 25 struct fft_sample_tlv; 26 27 #ifdef CONFIG_ATH9K_DEBUGFS 28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 29 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++) 30 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++ 31 #define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++ 32 #define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++; 33 #else 34 #define TX_STAT_INC(q, c) do { } while (0) 35 #define RX_STAT_INC(c) 36 #define RESET_STAT_INC(sc, type) do { } while (0) 37 #define ANT_STAT_INC(i, c) do { } while (0) 38 #define ANT_LNA_INC(i, c) do { } while (0) 39 #endif 40 41 enum ath_reset_type { 42 RESET_TYPE_BB_HANG, 43 RESET_TYPE_BB_WATCHDOG, 44 RESET_TYPE_FATAL_INT, 45 RESET_TYPE_TX_ERROR, 46 RESET_TYPE_TX_GTT, 47 RESET_TYPE_TX_HANG, 48 RESET_TYPE_PLL_HANG, 49 RESET_TYPE_MAC_HANG, 50 RESET_TYPE_BEACON_STUCK, 51 RESET_TYPE_MCI, 52 __RESET_TYPE_MAX 53 }; 54 55 #ifdef CONFIG_ATH9K_DEBUGFS 56 57 /** 58 * struct ath_interrupt_stats - Contains statistics about interrupts 59 * @total: Total no. of interrupts generated so far 60 * @rxok: RX with no errors 61 * @rxlp: RX with low priority RX 62 * @rxhp: RX with high priority, uapsd only 63 * @rxeol: RX with no more RXDESC available 64 * @rxorn: RX FIFO overrun 65 * @txok: TX completed at the requested rate 66 * @txurn: TX FIFO underrun 67 * @mib: MIB regs reaching its threshold 68 * @rxphyerr: RX with phy errors 69 * @rx_keycache_miss: RX with key cache misses 70 * @swba: Software Beacon Alert 71 * @bmiss: Beacon Miss 72 * @bnr: Beacon Not Ready 73 * @cst: Carrier Sense TImeout 74 * @gtt: Global TX Timeout 75 * @tim: RX beacon TIM occurrence 76 * @cabend: RX End of CAB traffic 77 * @dtimsync: DTIM sync lossage 78 * @dtim: RX Beacon with DTIM 79 * @bb_watchdog: Baseband watchdog 80 * @tsfoor: TSF out of range, indicates that the corrected TSF received 81 * from a beacon differs from the PCU's internal TSF by more than a 82 * (programmable) threshold 83 * @local_timeout: Internal bus timeout. 84 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets 85 * @gen_timer: Generic hardware timer interrupt 86 */ 87 struct ath_interrupt_stats { 88 u32 total; 89 u32 rxok; 90 u32 rxlp; 91 u32 rxhp; 92 u32 rxeol; 93 u32 rxorn; 94 u32 txok; 95 u32 txeol; 96 u32 txurn; 97 u32 mib; 98 u32 rxphyerr; 99 u32 rx_keycache_miss; 100 u32 swba; 101 u32 bmiss; 102 u32 bnr; 103 u32 cst; 104 u32 gtt; 105 u32 tim; 106 u32 cabend; 107 u32 dtimsync; 108 u32 dtim; 109 u32 bb_watchdog; 110 u32 tsfoor; 111 u32 mci; 112 u32 gen_timer; 113 114 /* Sync-cause stats */ 115 u32 sync_cause_all; 116 u32 sync_rtc_irq; 117 u32 sync_mac_irq; 118 u32 eeprom_illegal_access; 119 u32 apb_timeout; 120 u32 pci_mode_conflict; 121 u32 host1_fatal; 122 u32 host1_perr; 123 u32 trcv_fifo_perr; 124 u32 radm_cpl_ep; 125 u32 radm_cpl_dllp_abort; 126 u32 radm_cpl_tlp_abort; 127 u32 radm_cpl_ecrc_err; 128 u32 radm_cpl_timeout; 129 u32 local_timeout; 130 u32 pm_access; 131 u32 mac_awake; 132 u32 mac_asleep; 133 u32 mac_sleep_access; 134 }; 135 136 137 /** 138 * struct ath_tx_stats - Statistics about TX 139 * @tx_pkts_all: No. of total frames transmitted, including ones that 140 may have had errors. 141 * @tx_bytes_all: No. of total bytes transmitted, including ones that 142 may have had errors. 143 * @queued: Total MPDUs (non-aggr) queued 144 * @completed: Total MPDUs (non-aggr) completed 145 * @a_aggr: Total no. of aggregates queued 146 * @a_queued_hw: Total AMPDUs queued to hardware 147 * @a_queued_sw: Total AMPDUs queued to software queues 148 * @a_completed: Total AMPDUs completed 149 * @a_retries: No. of AMPDUs retried (SW) 150 * @a_xretries: No. of AMPDUs dropped due to xretries 151 * @txerr_filtered: No. of frames with TXERR_FILT flag set. 152 * @fifo_underrun: FIFO underrun occurrences 153 Valid only for: 154 - non-aggregate condition. 155 - first packet of aggregate. 156 * @xtxop: No. of frames filtered because of TXOP limit 157 * @timer_exp: Transmit timer expiry 158 * @desc_cfg_err: Descriptor configuration errors 159 * @data_urn: TX data underrun errors 160 * @delim_urn: TX delimiter underrun errors 161 * @puttxbuf: Number of times hardware was given txbuf to write. 162 * @txstart: Number of times hardware was told to start tx. 163 * @txprocdesc: Number of times tx descriptor was processed 164 * @txfailed: Out-of-memory or other errors in xmit path. 165 */ 166 struct ath_tx_stats { 167 u32 tx_pkts_all; 168 u32 tx_bytes_all; 169 u32 queued; 170 u32 completed; 171 u32 xretries; 172 u32 a_aggr; 173 u32 a_queued_hw; 174 u32 a_queued_sw; 175 u32 a_completed; 176 u32 a_retries; 177 u32 a_xretries; 178 u32 txerr_filtered; 179 u32 fifo_underrun; 180 u32 xtxop; 181 u32 timer_exp; 182 u32 desc_cfg_err; 183 u32 data_underrun; 184 u32 delim_underrun; 185 u32 puttxbuf; 186 u32 txstart; 187 u32 txprocdesc; 188 u32 txfailed; 189 }; 190 191 /* 192 * Various utility macros to print TX/Queue counters. 193 */ 194 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum 195 #define TXSTATS sc->debug.stats.txstats 196 #define PR(str, elem) \ 197 do { \ 198 len += scnprintf(buf + len, size - len, \ 199 "%s%13u%11u%10u%10u\n", str, \ 200 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\ 201 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\ 202 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\ 203 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \ 204 } while(0) 205 206 struct ath_rx_rate_stats { 207 struct { 208 u32 ht20_cnt; 209 u32 ht40_cnt; 210 u32 sgi_cnt; 211 u32 lgi_cnt; 212 } ht_stats[24]; 213 214 struct { 215 u32 ofdm_cnt; 216 } ofdm_stats[8]; 217 218 struct { 219 u32 cck_lp_cnt; 220 u32 cck_sp_cnt; 221 } cck_stats[4]; 222 }; 223 224 /** 225 * struct ath_rx_stats - RX Statistics 226 * @rx_pkts_all: No. of total frames received, including ones that 227 may have had errors. 228 * @rx_bytes_all: No. of total bytes received, including ones that 229 may have had errors. 230 * @crc_err: No. of frames with incorrect CRC value 231 * @decrypt_crc_err: No. of frames whose CRC check failed after 232 decryption process completed 233 * @phy_err: No. of frames whose reception failed because the PHY 234 encountered an error 235 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 236 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 237 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 238 * @decrypt_busy_err: Decryption interruptions counter 239 * @phy_err_stats: Individual PHY error statistics 240 * @rx_len_err: No. of frames discarded due to bad length. 241 * @rx_oom_err: No. of frames dropped due to OOM issues. 242 * @rx_rate_err: No. of frames dropped due to rate errors. 243 * @rx_too_many_frags_err: Frames dropped due to too-many-frags received. 244 * @rx_beacons: No. of beacons received. 245 * @rx_frags: No. of rx-fragements received. 246 * @rx_spectral: No of spectral packets received. 247 */ 248 struct ath_rx_stats { 249 u32 rx_pkts_all; 250 u32 rx_bytes_all; 251 u32 crc_err; 252 u32 decrypt_crc_err; 253 u32 phy_err; 254 u32 mic_err; 255 u32 pre_delim_crc_err; 256 u32 post_delim_crc_err; 257 u32 decrypt_busy_err; 258 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 259 u32 rx_len_err; 260 u32 rx_oom_err; 261 u32 rx_rate_err; 262 u32 rx_too_many_frags_err; 263 u32 rx_beacons; 264 u32 rx_frags; 265 u32 rx_spectral; 266 }; 267 268 #define ANT_MAIN 0 269 #define ANT_ALT 1 270 271 struct ath_antenna_stats { 272 u32 recv_cnt; 273 u32 rssi_avg; 274 u32 lna_recv_cnt[4]; 275 u32 lna_attempt_cnt[4]; 276 }; 277 278 struct ath_stats { 279 struct ath_interrupt_stats istats; 280 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 281 struct ath_rx_stats rxstats; 282 struct ath_dfs_stats dfs_stats; 283 struct ath_antenna_stats ant_stats[2]; 284 u32 reset[__RESET_TYPE_MAX]; 285 }; 286 287 struct ath9k_debug { 288 struct dentry *debugfs_phy; 289 u32 regidx; 290 struct ath_stats stats; 291 }; 292 293 int ath9k_init_debug(struct ath_hw *ah); 294 void ath9k_deinit_debug(struct ath_softc *sc); 295 296 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 297 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 298 struct ath_tx_status *ts, struct ath_txq *txq, 299 unsigned int flags); 300 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 301 int ath9k_get_et_sset_count(struct ieee80211_hw *hw, 302 struct ieee80211_vif *vif, int sset); 303 void ath9k_get_et_stats(struct ieee80211_hw *hw, 304 struct ieee80211_vif *vif, 305 struct ethtool_stats *stats, u64 *data); 306 void ath9k_get_et_strings(struct ieee80211_hw *hw, 307 struct ieee80211_vif *vif, 308 u32 sset, u8 *data); 309 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw, 310 struct ieee80211_vif *vif, 311 struct ieee80211_sta *sta, 312 struct dentry *dir); 313 void ath9k_debug_stat_ant(struct ath_softc *sc, 314 struct ath_hw_antcomb_conf *div_ant_conf, 315 int main_rssi_avg, int alt_rssi_avg); 316 void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause); 317 318 #else 319 320 static inline int ath9k_init_debug(struct ath_hw *ah) 321 { 322 return 0; 323 } 324 325 static inline void ath9k_deinit_debug(struct ath_softc *sc) 326 { 327 } 328 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 329 enum ath9k_int status) 330 { 331 } 332 static inline void ath_debug_stat_tx(struct ath_softc *sc, 333 struct ath_buf *bf, 334 struct ath_tx_status *ts, 335 struct ath_txq *txq, 336 unsigned int flags) 337 { 338 } 339 static inline void ath_debug_stat_rx(struct ath_softc *sc, 340 struct ath_rx_status *rs) 341 { 342 } 343 static inline void ath9k_debug_stat_ant(struct ath_softc *sc, 344 struct ath_hw_antcomb_conf *div_ant_conf, 345 int main_rssi_avg, int alt_rssi_avg) 346 { 347 348 } 349 350 static inline void 351 ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause) 352 { 353 } 354 355 #endif /* CONFIG_ATH9K_DEBUGFS */ 356 357 #ifdef CONFIG_ATH9K_STATION_STATISTICS 358 void ath_debug_rate_stats(struct ath_softc *sc, 359 struct ath_rx_status *rs, 360 struct sk_buff *skb); 361 #else 362 static inline void ath_debug_rate_stats(struct ath_softc *sc, 363 struct ath_rx_status *rs, 364 struct sk_buff *skb) 365 { 366 } 367 #endif /* CONFIG_ATH9K_STATION_STATISTICS */ 368 369 #endif /* DEBUG_H */ 370