1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "rc.h" 22 23 struct ath_txq; 24 struct ath_buf; 25 26 #ifdef CONFIG_ATH9K_DEBUGFS 27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 28 #else 29 #define TX_STAT_INC(q, c) do { } while (0) 30 #endif 31 32 #ifdef CONFIG_ATH9K_DEBUGFS 33 34 /** 35 * struct ath_interrupt_stats - Contains statistics about interrupts 36 * @total: Total no. of interrupts generated so far 37 * @rxok: RX with no errors 38 * @rxeol: RX with no more RXDESC available 39 * @rxorn: RX FIFO overrun 40 * @txok: TX completed at the requested rate 41 * @txurn: TX FIFO underrun 42 * @mib: MIB regs reaching its threshold 43 * @rxphyerr: RX with phy errors 44 * @rx_keycache_miss: RX with key cache misses 45 * @swba: Software Beacon Alert 46 * @bmiss: Beacon Miss 47 * @bnr: Beacon Not Ready 48 * @cst: Carrier Sense TImeout 49 * @gtt: Global TX Timeout 50 * @tim: RX beacon TIM occurrence 51 * @cabend: RX End of CAB traffic 52 * @dtimsync: DTIM sync lossage 53 * @dtim: RX Beacon with DTIM 54 */ 55 struct ath_interrupt_stats { 56 u32 total; 57 u32 rxok; 58 u32 rxeol; 59 u32 rxorn; 60 u32 txok; 61 u32 txeol; 62 u32 txurn; 63 u32 mib; 64 u32 rxphyerr; 65 u32 rx_keycache_miss; 66 u32 swba; 67 u32 bmiss; 68 u32 bnr; 69 u32 cst; 70 u32 gtt; 71 u32 tim; 72 u32 cabend; 73 u32 dtimsync; 74 u32 dtim; 75 }; 76 77 struct ath_rc_stats { 78 u32 success; 79 u32 retries; 80 u32 xretries; 81 u8 per; 82 }; 83 84 /** 85 * struct ath_tx_stats - Statistics about TX 86 * @queued: Total MPDUs (non-aggr) queued 87 * @completed: Total MPDUs (non-aggr) completed 88 * @a_aggr: Total no. of aggregates queued 89 * @a_queued: Total AMPDUs queued 90 * @a_completed: Total AMPDUs completed 91 * @a_retries: No. of AMPDUs retried (SW) 92 * @a_xretries: No. of AMPDUs dropped due to xretries 93 * @fifo_underrun: FIFO underrun occurrences 94 Valid only for: 95 - non-aggregate condition. 96 - first packet of aggregate. 97 * @xtxop: No. of frames filtered because of TXOP limit 98 * @timer_exp: Transmit timer expiry 99 * @desc_cfg_err: Descriptor configuration errors 100 * @data_urn: TX data underrun errors 101 * @delim_urn: TX delimiter underrun errors 102 */ 103 struct ath_tx_stats { 104 u32 queued; 105 u32 completed; 106 u32 a_aggr; 107 u32 a_queued; 108 u32 a_completed; 109 u32 a_retries; 110 u32 a_xretries; 111 u32 fifo_underrun; 112 u32 xtxop; 113 u32 timer_exp; 114 u32 desc_cfg_err; 115 u32 data_underrun; 116 u32 delim_underrun; 117 }; 118 119 /** 120 * struct ath_rx_stats - RX Statistics 121 * @crc_err: No. of frames with incorrect CRC value 122 * @decrypt_crc_err: No. of frames whose CRC check failed after 123 decryption process completed 124 * @phy_err: No. of frames whose reception failed because the PHY 125 encountered an error 126 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 127 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 128 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 129 * @decrypt_busy_err: Decryption interruptions counter 130 * @phy_err_stats: Individual PHY error statistics 131 */ 132 struct ath_rx_stats { 133 u32 crc_err; 134 u32 decrypt_crc_err; 135 u32 phy_err; 136 u32 mic_err; 137 u32 pre_delim_crc_err; 138 u32 post_delim_crc_err; 139 u32 decrypt_busy_err; 140 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 141 }; 142 143 struct ath_stats { 144 struct ath_interrupt_stats istats; 145 struct ath_rc_stats rcstats[RATE_TABLE_SIZE]; 146 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 147 struct ath_rx_stats rxstats; 148 }; 149 150 struct ath9k_debug { 151 struct dentry *debugfs_phy; 152 struct dentry *debugfs_debug; 153 struct dentry *debugfs_dma; 154 struct dentry *debugfs_interrupt; 155 struct dentry *debugfs_rcstat; 156 struct dentry *debugfs_wiphy; 157 struct dentry *debugfs_xmit; 158 struct dentry *debugfs_recv; 159 struct ath_stats stats; 160 }; 161 162 int ath9k_init_debug(struct ath_hw *ah); 163 void ath9k_exit_debug(struct ath_hw *ah); 164 165 int ath9k_debug_create_root(void); 166 void ath9k_debug_remove_root(void); 167 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 168 void ath_debug_stat_rc(struct ath_softc *sc, int final_rate); 169 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq, 170 struct ath_buf *bf); 171 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_buf *bf); 172 void ath_debug_stat_retries(struct ath_softc *sc, int rix, 173 int xretries, int retries, u8 per); 174 175 #else 176 177 static inline int ath9k_init_debug(struct ath_hw *ah) 178 { 179 return 0; 180 } 181 182 static inline void ath9k_exit_debug(struct ath_hw *ah) 183 { 184 } 185 186 static inline int ath9k_debug_create_root(void) 187 { 188 return 0; 189 } 190 191 static inline void ath9k_debug_remove_root(void) 192 { 193 } 194 195 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 196 enum ath9k_int status) 197 { 198 } 199 200 static inline void ath_debug_stat_rc(struct ath_softc *sc, 201 int final_rate) 202 { 203 } 204 205 static inline void ath_debug_stat_tx(struct ath_softc *sc, 206 struct ath_txq *txq, 207 struct ath_buf *bf) 208 { 209 } 210 211 static inline void ath_debug_stat_rx(struct ath_softc *sc, 212 struct ath_buf *bf) 213 { 214 } 215 216 static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix, 217 int xretries, int retries, u8 per) 218 { 219 } 220 221 #endif /* CONFIG_ATH9K_DEBUGFS */ 222 223 #endif /* DEBUG_H */ 224