1203c4805SLuis R. Rodriguez /*
25b68138eSSujith Manoharan * Copyright (c) 2008-2011 Atheros Communications Inc.
3203c4805SLuis R. Rodriguez *
4203c4805SLuis R. Rodriguez * Permission to use, copy, modify, and/or distribute this software for any
5203c4805SLuis R. Rodriguez * purpose with or without fee is hereby granted, provided that the above
6203c4805SLuis R. Rodriguez * copyright notice and this permission notice appear in all copies.
7203c4805SLuis R. Rodriguez *
8203c4805SLuis R. Rodriguez * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9203c4805SLuis R. Rodriguez * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10203c4805SLuis R. Rodriguez * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11203c4805SLuis R. Rodriguez * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12203c4805SLuis R. Rodriguez * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13203c4805SLuis R. Rodriguez * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14203c4805SLuis R. Rodriguez * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15203c4805SLuis R. Rodriguez */
16203c4805SLuis R. Rodriguez
17203c4805SLuis R. Rodriguez #ifndef DEBUG_H
18203c4805SLuis R. Rodriguez #define DEBUG_H
19203c4805SLuis R. Rodriguez
204d6b228dSLuis R. Rodriguez #include "hw.h"
2129942bc1SZefir Kurtisi #include "dfs_debug.h"
224d6b228dSLuis R. Rodriguez
23fec247c0SSujith struct ath_txq;
24fec247c0SSujith struct ath_buf;
25e93d083fSSimon Wunderlich struct fft_sample_tlv;
26fec247c0SSujith
27a830df07SFelix Fietkau #ifdef CONFIG_ATH9K_DEBUGFS
2872569b7bSArnd Bergmann #define TX_STAT_INC(sc, q, c) do { (sc)->debug.stats.txstats[q].c++; } while (0)
2972569b7bSArnd Bergmann #define RX_STAT_INC(sc, c) do { (sc)->debug.stats.rxstats.c++; } while (0)
3072569b7bSArnd Bergmann #define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0)
3172569b7bSArnd Bergmann #define ANT_STAT_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].c++; } while (0)
3272569b7bSArnd Bergmann #define ANT_LNA_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0)
33fec247c0SSujith #else
3472569b7bSArnd Bergmann #define TX_STAT_INC(sc, q, c) do { (void)(sc); } while (0)
3572569b7bSArnd Bergmann #define RX_STAT_INC(sc, c) do { (void)(sc); } while (0)
3672569b7bSArnd Bergmann #define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0)
3772569b7bSArnd Bergmann #define ANT_STAT_INC(sc, i, c) do { (void)(sc); } while (0)
3872569b7bSArnd Bergmann #define ANT_LNA_INC(sc, i, c) do { (void)(sc); } while (0)
39fec247c0SSujith #endif
40fec247c0SSujith
41124b979bSRajkumar Manoharan enum ath_reset_type {
42*053f9852SLinus Lüssing RESET_TYPE_USER,
43124b979bSRajkumar Manoharan RESET_TYPE_BB_HANG,
44124b979bSRajkumar Manoharan RESET_TYPE_BB_WATCHDOG,
45124b979bSRajkumar Manoharan RESET_TYPE_FATAL_INT,
46124b979bSRajkumar Manoharan RESET_TYPE_TX_ERROR,
47071aa9a8SSujith Manoharan RESET_TYPE_TX_GTT,
48124b979bSRajkumar Manoharan RESET_TYPE_TX_HANG,
49124b979bSRajkumar Manoharan RESET_TYPE_PLL_HANG,
50124b979bSRajkumar Manoharan RESET_TYPE_MAC_HANG,
51124b979bSRajkumar Manoharan RESET_TYPE_BEACON_STUCK,
52b88083bfSRajkumar Manoharan RESET_TYPE_MCI,
537b8aaeadSFelix Fietkau RESET_TYPE_CALIBRATION,
54e60ac9c7SFelix Fietkau RESET_TX_DMA_ERROR,
55e60ac9c7SFelix Fietkau RESET_RX_DMA_ERROR,
56124b979bSRajkumar Manoharan __RESET_TYPE_MAX
57124b979bSRajkumar Manoharan };
58124b979bSRajkumar Manoharan
59a830df07SFelix Fietkau #ifdef CONFIG_ATH9K_DEBUGFS
60203c4805SLuis R. Rodriguez
61203c4805SLuis R. Rodriguez /**
62203c4805SLuis R. Rodriguez * struct ath_interrupt_stats - Contains statistics about interrupts
63203c4805SLuis R. Rodriguez * @total: Total no. of interrupts generated so far
64203c4805SLuis R. Rodriguez * @rxok: RX with no errors
65a9616f41SLuis R. Rodriguez * @rxlp: RX with low priority RX
66a9616f41SLuis R. Rodriguez * @rxhp: RX with high priority, uapsd only
67203c4805SLuis R. Rodriguez * @rxeol: RX with no more RXDESC available
68203c4805SLuis R. Rodriguez * @rxorn: RX FIFO overrun
69203c4805SLuis R. Rodriguez * @txok: TX completed at the requested rate
70203c4805SLuis R. Rodriguez * @txurn: TX FIFO underrun
71203c4805SLuis R. Rodriguez * @mib: MIB regs reaching its threshold
72203c4805SLuis R. Rodriguez * @rxphyerr: RX with phy errors
73203c4805SLuis R. Rodriguez * @rx_keycache_miss: RX with key cache misses
74203c4805SLuis R. Rodriguez * @swba: Software Beacon Alert
75203c4805SLuis R. Rodriguez * @bmiss: Beacon Miss
76203c4805SLuis R. Rodriguez * @bnr: Beacon Not Ready
77203c4805SLuis R. Rodriguez * @cst: Carrier Sense TImeout
78203c4805SLuis R. Rodriguez * @gtt: Global TX Timeout
79203c4805SLuis R. Rodriguez * @tim: RX beacon TIM occurrence
80203c4805SLuis R. Rodriguez * @cabend: RX End of CAB traffic
81203c4805SLuis R. Rodriguez * @dtimsync: DTIM sync lossage
82203c4805SLuis R. Rodriguez * @dtim: RX Beacon with DTIM
8308578b8fSLuis R. Rodriguez * @bb_watchdog: Baseband watchdog
846dde1aabSMohammed Shafi Shajakhan * @tsfoor: TSF out of range, indicates that the corrected TSF received
856dde1aabSMohammed Shafi Shajakhan * from a beacon differs from the PCU's internal TSF by more than a
866dde1aabSMohammed Shafi Shajakhan * (programmable) threshold
87462e58f2SBen Greear * @local_timeout: Internal bus timeout.
88c9e6e980SMohammed Shafi Shajakhan * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
89c9e6e980SMohammed Shafi Shajakhan * @gen_timer: Generic hardware timer interrupt
90203c4805SLuis R. Rodriguez */
91203c4805SLuis R. Rodriguez struct ath_interrupt_stats {
92203c4805SLuis R. Rodriguez u32 total;
93203c4805SLuis R. Rodriguez u32 rxok;
94a9616f41SLuis R. Rodriguez u32 rxlp;
95a9616f41SLuis R. Rodriguez u32 rxhp;
96203c4805SLuis R. Rodriguez u32 rxeol;
97203c4805SLuis R. Rodriguez u32 rxorn;
98203c4805SLuis R. Rodriguez u32 txok;
99203c4805SLuis R. Rodriguez u32 txeol;
100203c4805SLuis R. Rodriguez u32 txurn;
101203c4805SLuis R. Rodriguez u32 mib;
102203c4805SLuis R. Rodriguez u32 rxphyerr;
103203c4805SLuis R. Rodriguez u32 rx_keycache_miss;
104203c4805SLuis R. Rodriguez u32 swba;
105203c4805SLuis R. Rodriguez u32 bmiss;
106203c4805SLuis R. Rodriguez u32 bnr;
107203c4805SLuis R. Rodriguez u32 cst;
108203c4805SLuis R. Rodriguez u32 gtt;
109203c4805SLuis R. Rodriguez u32 tim;
110203c4805SLuis R. Rodriguez u32 cabend;
111203c4805SLuis R. Rodriguez u32 dtimsync;
112203c4805SLuis R. Rodriguez u32 dtim;
11308578b8fSLuis R. Rodriguez u32 bb_watchdog;
1146dde1aabSMohammed Shafi Shajakhan u32 tsfoor;
11597ba515aSSujith Manoharan u32 mci;
116c9e6e980SMohammed Shafi Shajakhan u32 gen_timer;
117462e58f2SBen Greear
118462e58f2SBen Greear /* Sync-cause stats */
119462e58f2SBen Greear u32 sync_cause_all;
120462e58f2SBen Greear u32 sync_rtc_irq;
121462e58f2SBen Greear u32 sync_mac_irq;
122462e58f2SBen Greear u32 eeprom_illegal_access;
123462e58f2SBen Greear u32 apb_timeout;
124462e58f2SBen Greear u32 pci_mode_conflict;
125462e58f2SBen Greear u32 host1_fatal;
126462e58f2SBen Greear u32 host1_perr;
127462e58f2SBen Greear u32 trcv_fifo_perr;
128462e58f2SBen Greear u32 radm_cpl_ep;
129462e58f2SBen Greear u32 radm_cpl_dllp_abort;
130462e58f2SBen Greear u32 radm_cpl_tlp_abort;
131462e58f2SBen Greear u32 radm_cpl_ecrc_err;
132462e58f2SBen Greear u32 radm_cpl_timeout;
133462e58f2SBen Greear u32 local_timeout;
134462e58f2SBen Greear u32 pm_access;
135462e58f2SBen Greear u32 mac_awake;
136462e58f2SBen Greear u32 mac_asleep;
137462e58f2SBen Greear u32 mac_sleep_access;
138203c4805SLuis R. Rodriguez };
139203c4805SLuis R. Rodriguez
140462e58f2SBen Greear
141fec247c0SSujith /**
142fec247c0SSujith * struct ath_tx_stats - Statistics about TX
14399c15bf5SBen Greear * @tx_pkts_all: No. of total frames transmitted, including ones that
14499c15bf5SBen Greear may have had errors.
14599c15bf5SBen Greear * @tx_bytes_all: No. of total bytes transmitted, including ones that
14699c15bf5SBen Greear may have had errors.
147fec247c0SSujith * @queued: Total MPDUs (non-aggr) queued
148fec247c0SSujith * @completed: Total MPDUs (non-aggr) completed
149fec247c0SSujith * @a_aggr: Total no. of aggregates queued
150bda8addaSBen Greear * @a_queued_hw: Total AMPDUs queued to hardware
151fec247c0SSujith * @a_completed: Total AMPDUs completed
152fec247c0SSujith * @a_retries: No. of AMPDUs retried (SW)
153fec247c0SSujith * @a_xretries: No. of AMPDUs dropped due to xretries
1544d900389SBen Greear * @txerr_filtered: No. of frames with TXERR_FILT flag set.
155fec247c0SSujith * @fifo_underrun: FIFO underrun occurrences
156fec247c0SSujith Valid only for:
157fec247c0SSujith - non-aggregate condition.
158fec247c0SSujith - first packet of aggregate.
159fec247c0SSujith * @xtxop: No. of frames filtered because of TXOP limit
160fec247c0SSujith * @timer_exp: Transmit timer expiry
161fec247c0SSujith * @desc_cfg_err: Descriptor configuration errors
162fec247c0SSujith * @data_urn: TX data underrun errors
163fec247c0SSujith * @delim_urn: TX delimiter underrun errors
1642dac4fb9SBen Greear * @puttxbuf: Number of times hardware was given txbuf to write.
1652dac4fb9SBen Greear * @txstart: Number of times hardware was told to start tx.
1662dac4fb9SBen Greear * @txprocdesc: Number of times tx descriptor was processed
167a5a0bca1SBen Greear * @txfailed: Out-of-memory or other errors in xmit path.
168fec247c0SSujith */
169fec247c0SSujith struct ath_tx_stats {
17099c15bf5SBen Greear u32 tx_pkts_all;
17199c15bf5SBen Greear u32 tx_bytes_all;
172fec247c0SSujith u32 queued;
173fec247c0SSujith u32 completed;
1745a6f78afSFelix Fietkau u32 xretries;
175fec247c0SSujith u32 a_aggr;
176bda8addaSBen Greear u32 a_queued_hw;
177fec247c0SSujith u32 a_completed;
178fec247c0SSujith u32 a_retries;
179fec247c0SSujith u32 a_xretries;
1804d900389SBen Greear u32 txerr_filtered;
181fec247c0SSujith u32 fifo_underrun;
182fec247c0SSujith u32 xtxop;
183fec247c0SSujith u32 timer_exp;
184fec247c0SSujith u32 desc_cfg_err;
185fec247c0SSujith u32 data_underrun;
186fec247c0SSujith u32 delim_underrun;
1872dac4fb9SBen Greear u32 puttxbuf;
1882dac4fb9SBen Greear u32 txstart;
1892dac4fb9SBen Greear u32 txprocdesc;
190a5a0bca1SBen Greear u32 txfailed;
191fec247c0SSujith };
192fec247c0SSujith
19378ef731cSSujith Manoharan /*
19478ef731cSSujith Manoharan * Various utility macros to print TX/Queue counters.
19578ef731cSSujith Manoharan */
19678ef731cSSujith Manoharan #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
19778ef731cSSujith Manoharan #define TXSTATS sc->debug.stats.txstats
19878ef731cSSujith Manoharan #define PR(str, elem) \
19978ef731cSSujith Manoharan do { \
200631bee25SArend van Spriel seq_printf(file, "%s%13u%11u%10u%10u\n", str, \
20178ef731cSSujith Manoharan TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
20278ef731cSSujith Manoharan TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
20378ef731cSSujith Manoharan TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
20478ef731cSSujith Manoharan TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
20578ef731cSSujith Manoharan } while(0)
20678ef731cSSujith Manoharan
207350e2dcbSSujith Manoharan struct ath_rx_rate_stats {
208350e2dcbSSujith Manoharan struct {
209350e2dcbSSujith Manoharan u32 ht20_cnt;
210350e2dcbSSujith Manoharan u32 ht40_cnt;
211350e2dcbSSujith Manoharan u32 sgi_cnt;
212350e2dcbSSujith Manoharan u32 lgi_cnt;
213350e2dcbSSujith Manoharan } ht_stats[24];
214350e2dcbSSujith Manoharan
215350e2dcbSSujith Manoharan struct {
216350e2dcbSSujith Manoharan u32 ofdm_cnt;
217350e2dcbSSujith Manoharan } ofdm_stats[8];
218350e2dcbSSujith Manoharan
219350e2dcbSSujith Manoharan struct {
220350e2dcbSSujith Manoharan u32 cck_lp_cnt;
221350e2dcbSSujith Manoharan u32 cck_sp_cnt;
222350e2dcbSSujith Manoharan } cck_stats[4];
223350e2dcbSSujith Manoharan };
22415072189SBen Greear
22563fefa05SToke Høiland-Jørgensen struct ath_airtime_stats {
22663fefa05SToke Høiland-Jørgensen u32 rx_airtime;
22763fefa05SToke Høiland-Jørgensen u32 tx_airtime;
22863fefa05SToke Høiland-Jørgensen };
22963fefa05SToke Høiland-Jørgensen
2303fbaf4c5SSujith Manoharan #define ANT_MAIN 0
2313fbaf4c5SSujith Manoharan #define ANT_ALT 1
2323fbaf4c5SSujith Manoharan
2333fbaf4c5SSujith Manoharan struct ath_antenna_stats {
2343fbaf4c5SSujith Manoharan u32 recv_cnt;
235e3d52914SSujith Manoharan u32 rssi_avg;
236e3d52914SSujith Manoharan u32 lna_recv_cnt[4];
237e3d52914SSujith Manoharan u32 lna_attempt_cnt[4];
2383fbaf4c5SSujith Manoharan };
2393fbaf4c5SSujith Manoharan
240203c4805SLuis R. Rodriguez struct ath_stats {
241203c4805SLuis R. Rodriguez struct ath_interrupt_stats istats;
2424f7dc951SSujith Manoharan struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
2431395d3f0SSujith struct ath_rx_stats rxstats;
24429942bc1SZefir Kurtisi struct ath_dfs_stats dfs_stats;
2453fbaf4c5SSujith Manoharan struct ath_antenna_stats ant_stats[2];
246030d6294SFelix Fietkau u32 reset[__RESET_TYPE_MAX];
247203c4805SLuis R. Rodriguez };
248203c4805SLuis R. Rodriguez
249203c4805SLuis R. Rodriguez struct ath9k_debug {
250203c4805SLuis R. Rodriguez struct dentry *debugfs_phy;
2519bff0bc4SFelix Fietkau u32 regidx;
252203c4805SLuis R. Rodriguez struct ath_stats stats;
253203c4805SLuis R. Rodriguez };
254203c4805SLuis R. Rodriguez
2554d6b228dSLuis R. Rodriguez int ath9k_init_debug(struct ath_hw *ah);
256af690092SSujith Manoharan void ath9k_deinit_debug(struct ath_softc *sc);
2574d6b228dSLuis R. Rodriguez
258203c4805SLuis R. Rodriguez void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
259066dae93SFelix Fietkau void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
26055797b1aSFelix Fietkau struct ath_tx_status *ts, struct ath_txq *txq,
26155797b1aSFelix Fietkau unsigned int flags);
2628e6f5aa2SFelix Fietkau void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
263c175db87SSujith Manoharan int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
264c175db87SSujith Manoharan struct ieee80211_vif *vif, int sset);
265c175db87SSujith Manoharan void ath9k_get_et_stats(struct ieee80211_hw *hw,
266c175db87SSujith Manoharan struct ieee80211_vif *vif,
267c175db87SSujith Manoharan struct ethtool_stats *stats, u64 *data);
268c175db87SSujith Manoharan void ath9k_get_et_strings(struct ieee80211_hw *hw,
269c175db87SSujith Manoharan struct ieee80211_vif *vif,
270c175db87SSujith Manoharan u32 sset, u8 *data);
271a145daf7SSujith Manoharan void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
272a145daf7SSujith Manoharan struct ieee80211_vif *vif,
273a145daf7SSujith Manoharan struct ieee80211_sta *sta,
274a145daf7SSujith Manoharan struct dentry *dir);
275e3d52914SSujith Manoharan void ath9k_debug_stat_ant(struct ath_softc *sc,
276e3d52914SSujith Manoharan struct ath_hw_antcomb_conf *div_ant_conf,
277e3d52914SSujith Manoharan int main_rssi_avg, int alt_rssi_avg);
2786a4d05dcSFelix Fietkau void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
2796a4d05dcSFelix Fietkau
280203c4805SLuis R. Rodriguez #else
281203c4805SLuis R. Rodriguez
ath9k_init_debug(struct ath_hw * ah)2824d6b228dSLuis R. Rodriguez static inline int ath9k_init_debug(struct ath_hw *ah)
283203c4805SLuis R. Rodriguez {
284203c4805SLuis R. Rodriguez return 0;
285203c4805SLuis R. Rodriguez }
286203c4805SLuis R. Rodriguez
ath9k_deinit_debug(struct ath_softc * sc)287af690092SSujith Manoharan static inline void ath9k_deinit_debug(struct ath_softc *sc)
288af690092SSujith Manoharan {
289af690092SSujith Manoharan }
ath_debug_stat_interrupt(struct ath_softc * sc,enum ath9k_int status)290203c4805SLuis R. Rodriguez static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
291203c4805SLuis R. Rodriguez enum ath9k_int status)
292203c4805SLuis R. Rodriguez {
293203c4805SLuis R. Rodriguez }
ath_debug_stat_tx(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,struct ath_txq * txq,unsigned int flags)294fec247c0SSujith static inline void ath_debug_stat_tx(struct ath_softc *sc,
29532ffb1f4SFelix Fietkau struct ath_buf *bf,
2963bf63e59SFelix Fietkau struct ath_tx_status *ts,
29755797b1aSFelix Fietkau struct ath_txq *txq,
29855797b1aSFelix Fietkau unsigned int flags)
299fec247c0SSujith {
300fec247c0SSujith }
ath_debug_stat_rx(struct ath_softc * sc,struct ath_rx_status * rs)3011395d3f0SSujith static inline void ath_debug_stat_rx(struct ath_softc *sc,
30232ffb1f4SFelix Fietkau struct ath_rx_status *rs)
3031395d3f0SSujith {
3041395d3f0SSujith }
ath9k_debug_stat_ant(struct ath_softc * sc,struct ath_hw_antcomb_conf * div_ant_conf,int main_rssi_avg,int alt_rssi_avg)305e3d52914SSujith Manoharan static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
306e3d52914SSujith Manoharan struct ath_hw_antcomb_conf *div_ant_conf,
307e3d52914SSujith Manoharan int main_rssi_avg, int alt_rssi_avg)
308e3d52914SSujith Manoharan {
309e3d52914SSujith Manoharan
310e3d52914SSujith Manoharan }
3111395d3f0SSujith
3126a4d05dcSFelix Fietkau static inline void
ath9k_debug_sync_cause(struct ath_softc * sc,u32 sync_cause)3136a4d05dcSFelix Fietkau ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
3146a4d05dcSFelix Fietkau {
3156a4d05dcSFelix Fietkau }
3166a4d05dcSFelix Fietkau
317a830df07SFelix Fietkau #endif /* CONFIG_ATH9K_DEBUGFS */
318203c4805SLuis R. Rodriguez
319350e2dcbSSujith Manoharan #ifdef CONFIG_ATH9K_STATION_STATISTICS
320350e2dcbSSujith Manoharan void ath_debug_rate_stats(struct ath_softc *sc,
321350e2dcbSSujith Manoharan struct ath_rx_status *rs,
322350e2dcbSSujith Manoharan struct sk_buff *skb);
323350e2dcbSSujith Manoharan #else
ath_debug_rate_stats(struct ath_softc * sc,struct ath_rx_status * rs,struct sk_buff * skb)324350e2dcbSSujith Manoharan static inline void ath_debug_rate_stats(struct ath_softc *sc,
325350e2dcbSSujith Manoharan struct ath_rx_status *rs,
326350e2dcbSSujith Manoharan struct sk_buff *skb)
327350e2dcbSSujith Manoharan {
328350e2dcbSSujith Manoharan }
329350e2dcbSSujith Manoharan #endif /* CONFIG_ATH9K_STATION_STATISTICS */
330350e2dcbSSujith Manoharan
331203c4805SLuis R. Rodriguez #endif /* DEBUG_H */
332