1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <net/mac80211.h> 23 #include <linux/leds.h> 24 25 #include "hw.h" 26 #include "rc.h" 27 #include "debug.h" 28 #include "../ath.h" 29 #include "btcoex.h" 30 31 struct ath_node; 32 33 /* Macro to expand scalars to 64-bit objects */ 34 35 #define ito64(x) (sizeof(x) == 8) ? \ 36 (((unsigned long long int)(x)) & (0xff)) : \ 37 (sizeof(x) == 16) ? \ 38 (((unsigned long long int)(x)) & 0xffff) : \ 39 ((sizeof(x) == 32) ? \ 40 (((unsigned long long int)(x)) & 0xffffffff) : \ 41 (unsigned long long int)(x)) 42 43 /* increment with wrap-around */ 44 #define INCR(_l, _sz) do { \ 45 (_l)++; \ 46 (_l) &= ((_sz) - 1); \ 47 } while (0) 48 49 /* decrement with wrap-around */ 50 #define DECR(_l, _sz) do { \ 51 (_l)--; \ 52 (_l) &= ((_sz) - 1); \ 53 } while (0) 54 55 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 56 57 #define ASSERT(exp) BUG_ON(!(exp)) 58 59 #define TSF_TO_TU(_h,_l) \ 60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 61 62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 63 64 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 65 66 struct ath_config { 67 u32 ath_aggr_prot; 68 u16 txpowlimit; 69 u8 cabqReadytime; 70 }; 71 72 /*************************/ 73 /* Descriptor Management */ 74 /*************************/ 75 76 #define ATH_TXBUF_RESET(_bf) do { \ 77 (_bf)->bf_stale = false; \ 78 (_bf)->bf_lastbf = NULL; \ 79 (_bf)->bf_next = NULL; \ 80 memset(&((_bf)->bf_state), 0, \ 81 sizeof(struct ath_buf_state)); \ 82 } while (0) 83 84 #define ATH_RXBUF_RESET(_bf) do { \ 85 (_bf)->bf_stale = false; \ 86 } while (0) 87 88 /** 89 * enum buffer_type - Buffer type flags 90 * 91 * @BUF_HT: Send this buffer using HT capabilities 92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 93 * @BUF_AGGR: Indicates whether the buffer can be aggregated 94 * (used in aggregation scheduling) 95 * @BUF_RETRY: Indicates whether the buffer is retried 96 * @BUF_XRETRY: To denote excessive retries of the buffer 97 */ 98 enum buffer_type { 99 BUF_HT = BIT(1), 100 BUF_AMPDU = BIT(2), 101 BUF_AGGR = BIT(3), 102 BUF_RETRY = BIT(4), 103 BUF_XRETRY = BIT(5), 104 }; 105 106 struct ath_buf_state { 107 int bfs_nframes; 108 u16 bfs_al; 109 u16 bfs_frmlen; 110 int bfs_seqno; 111 int bfs_tidno; 112 int bfs_retries; 113 u8 bf_type; 114 u32 bfs_keyix; 115 enum ath9k_key_type bfs_keytype; 116 }; 117 118 #define bf_nframes bf_state.bfs_nframes 119 #define bf_al bf_state.bfs_al 120 #define bf_frmlen bf_state.bfs_frmlen 121 #define bf_retries bf_state.bfs_retries 122 #define bf_seqno bf_state.bfs_seqno 123 #define bf_tidno bf_state.bfs_tidno 124 #define bf_keyix bf_state.bfs_keyix 125 #define bf_keytype bf_state.bfs_keytype 126 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) 127 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 128 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 129 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 130 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 131 132 struct ath_buf { 133 struct list_head list; 134 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 135 an aggregate) */ 136 struct ath_buf *bf_next; /* next subframe in the aggregate */ 137 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 138 struct ath_desc *bf_desc; /* virtual addr of desc */ 139 dma_addr_t bf_daddr; /* physical addr of desc */ 140 dma_addr_t bf_buf_addr; /* physical addr of data buffer */ 141 bool bf_stale; 142 u16 bf_flags; 143 struct ath_buf_state bf_state; 144 dma_addr_t bf_dmacontext; 145 }; 146 147 struct ath_descdma { 148 struct ath_desc *dd_desc; 149 dma_addr_t dd_desc_paddr; 150 u32 dd_desc_len; 151 struct ath_buf *dd_bufptr; 152 }; 153 154 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 155 struct list_head *head, const char *name, 156 int nbuf, int ndesc); 157 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 158 struct list_head *head); 159 160 /***********/ 161 /* RX / TX */ 162 /***********/ 163 164 #define ATH_MAX_ANTENNA 3 165 #define ATH_RXBUF 512 166 #define WME_NUM_TID 16 167 #define ATH_TXBUF 512 168 #define ATH_TXMAXTRY 13 169 #define ATH_MGT_TXMAXTRY 4 170 #define WME_BA_BMP_SIZE 64 171 #define WME_MAX_BA WME_BA_BMP_SIZE 172 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) 173 174 #define TID_TO_WME_AC(_tid) \ 175 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 176 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 177 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 178 WME_AC_VO) 179 180 #define WME_AC_BE 0 181 #define WME_AC_BK 1 182 #define WME_AC_VI 2 183 #define WME_AC_VO 3 184 #define WME_NUM_AC 4 185 186 #define ADDBA_EXCHANGE_ATTEMPTS 10 187 #define ATH_AGGR_DELIM_SZ 4 188 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 189 /* number of delimiters for encryption padding */ 190 #define ATH_AGGR_ENCRYPTDELIM 10 191 /* minimum h/w qdepth to be sustained to maximize aggregation */ 192 #define ATH_AGGR_MIN_QDEPTH 2 193 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 194 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 195 196 #define IEEE80211_SEQ_SEQ_SHIFT 4 197 #define IEEE80211_SEQ_MAX 4096 198 #define IEEE80211_WEP_IVLEN 3 199 #define IEEE80211_WEP_KIDLEN 1 200 #define IEEE80211_WEP_CRCLEN 4 201 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 202 (IEEE80211_WEP_IVLEN + \ 203 IEEE80211_WEP_KIDLEN + \ 204 IEEE80211_WEP_CRCLEN)) 205 206 /* return whether a bit at index _n in bitmap _bm is set 207 * _sz is the size of the bitmap */ 208 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 209 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 210 211 /* return block-ack bitmap index given sequence and starting sequence */ 212 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 213 214 /* returns delimiter padding required given the packet length */ 215 #define ATH_AGGR_GET_NDELIM(_len) \ 216 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ 217 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) 218 219 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 220 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 221 222 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) 223 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) 224 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) 225 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 226 227 #define ATH_TX_COMPLETE_POLL_INT 1000 228 229 enum ATH_AGGR_STATUS { 230 ATH_AGGR_DONE, 231 ATH_AGGR_BAW_CLOSED, 232 ATH_AGGR_LIMITED, 233 }; 234 235 struct ath_txq { 236 u32 axq_qnum; 237 u32 *axq_link; 238 struct list_head axq_q; 239 spinlock_t axq_lock; 240 u32 axq_depth; 241 u8 axq_aggr_depth; 242 bool stopped; 243 bool axq_tx_inprogress; 244 struct ath_buf *axq_linkbuf; 245 246 /* first desc of the last descriptor that contains CTS */ 247 struct ath_desc *axq_lastdsWithCTS; 248 249 /* final desc of the gating desc that determines whether 250 lastdsWithCTS has been DMA'ed or not */ 251 struct ath_desc *axq_gatingds; 252 253 struct list_head axq_acq; 254 }; 255 256 #define AGGR_CLEANUP BIT(1) 257 #define AGGR_ADDBA_COMPLETE BIT(2) 258 #define AGGR_ADDBA_PROGRESS BIT(3) 259 260 struct ath_atx_tid { 261 struct list_head list; 262 struct list_head buf_q; 263 struct ath_node *an; 264 struct ath_atx_ac *ac; 265 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 266 u16 seq_start; 267 u16 seq_next; 268 u16 baw_size; 269 int tidno; 270 int baw_head; /* first un-acked tx buffer */ 271 int baw_tail; /* next unused tx buffer slot */ 272 int sched; 273 int paused; 274 u8 state; 275 }; 276 277 struct ath_atx_ac { 278 int sched; 279 int qnum; 280 struct list_head list; 281 struct list_head tid_q; 282 }; 283 284 struct ath_tx_control { 285 struct ath_txq *txq; 286 int if_id; 287 enum ath9k_internal_frame_type frame_type; 288 }; 289 290 #define ATH_TX_ERROR 0x01 291 #define ATH_TX_XRETRY 0x02 292 #define ATH_TX_BAR 0x04 293 294 #define ATH_RSSI_LPF_LEN 10 295 #define RSSI_LPF_THRESHOLD -20 296 #define ATH9K_RSSI_BAD 0x80 297 #define ATH_RSSI_EP_MULTIPLIER (1<<7) 298 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 299 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER)) 300 #define ATH_LPF_RSSI(x, y, len) \ 301 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 302 #define ATH_RSSI_LPF(x, y) do { \ 303 if ((y) >= RSSI_LPF_THRESHOLD) \ 304 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 305 } while (0) 306 #define ATH_EP_RND(x, mul) \ 307 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 308 309 struct ath_node { 310 struct ath_softc *an_sc; 311 struct ath_atx_tid tid[WME_NUM_TID]; 312 struct ath_atx_ac ac[WME_NUM_AC]; 313 u16 maxampdu; 314 u8 mpdudensity; 315 int last_rssi; 316 }; 317 318 struct ath_tx { 319 u16 seq_no; 320 u32 txqsetup; 321 int hwq_map[ATH9K_WME_AC_VO+1]; 322 spinlock_t txbuflock; 323 struct list_head txbuf; 324 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 325 struct ath_descdma txdma; 326 }; 327 328 struct ath_rx { 329 u8 defant; 330 u8 rxotherant; 331 u32 *rxlink; 332 int bufsize; 333 unsigned int rxfilter; 334 spinlock_t rxflushlock; 335 spinlock_t rxbuflock; 336 struct list_head rxbuf; 337 struct ath_descdma rxdma; 338 }; 339 340 int ath_startrecv(struct ath_softc *sc); 341 bool ath_stoprecv(struct ath_softc *sc); 342 void ath_flushrecv(struct ath_softc *sc); 343 u32 ath_calcrxfilter(struct ath_softc *sc); 344 int ath_rx_init(struct ath_softc *sc, int nbufs); 345 void ath_rx_cleanup(struct ath_softc *sc); 346 int ath_rx_tasklet(struct ath_softc *sc, int flush); 347 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 348 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 349 int ath_tx_setup(struct ath_softc *sc, int haltype); 350 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 351 void ath_draintxq(struct ath_softc *sc, 352 struct ath_txq *txq, bool retry_tx); 353 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 354 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 355 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 356 int ath_tx_init(struct ath_softc *sc, int nbufs); 357 void ath_tx_cleanup(struct ath_softc *sc); 358 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); 359 int ath_txq_update(struct ath_softc *sc, int qnum, 360 struct ath9k_tx_queue_info *q); 361 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 362 struct ath_tx_control *txctl); 363 void ath_tx_tasklet(struct ath_softc *sc); 364 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); 365 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); 366 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 367 u16 tid, u16 *ssn); 368 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 369 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 370 371 /********/ 372 /* VIFs */ 373 /********/ 374 375 struct ath_vif { 376 int av_bslot; 377 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 378 enum nl80211_iftype av_opmode; 379 struct ath_buf *av_bcbuf; 380 struct ath_tx_control av_btxctl; 381 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ 382 }; 383 384 /*******************/ 385 /* Beacon Handling */ 386 /*******************/ 387 388 /* 389 * Regardless of the number of beacons we stagger, (i.e. regardless of the 390 * number of BSSIDs) if a given beacon does not go out even after waiting this 391 * number of beacon intervals, the game's up. 392 */ 393 #define BSTUCK_THRESH (9 * ATH_BCBUF) 394 #define ATH_BCBUF 4 395 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 396 #define ATH_DEFAULT_BMISS_LIMIT 10 397 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 398 399 struct ath_beacon_config { 400 u16 beacon_interval; 401 u16 listen_interval; 402 u16 dtim_period; 403 u16 bmiss_timeout; 404 u8 dtim_count; 405 }; 406 407 struct ath_beacon { 408 enum { 409 OK, /* no change needed */ 410 UPDATE, /* update pending */ 411 COMMIT /* beacon sent, commit change */ 412 } updateslot; /* slot time update fsm */ 413 414 u32 beaconq; 415 u32 bmisscnt; 416 u32 ast_be_xmit; 417 u64 bc_tstamp; 418 struct ieee80211_vif *bslot[ATH_BCBUF]; 419 struct ath_wiphy *bslot_aphy[ATH_BCBUF]; 420 int slottime; 421 int slotupdate; 422 struct ath9k_tx_queue_info beacon_qi; 423 struct ath_descdma bdma; 424 struct ath_txq *cabq; 425 struct list_head bbuf; 426 }; 427 428 void ath_beacon_tasklet(unsigned long data); 429 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 430 int ath_beaconq_setup(struct ath_hw *ah); 431 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 432 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 433 434 /*******/ 435 /* ANI */ 436 /*******/ 437 438 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 439 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 440 #define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ 441 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 442 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 443 444 struct ath_ani { 445 bool caldone; 446 int16_t noise_floor; 447 unsigned int longcal_timer; 448 unsigned int shortcal_timer; 449 unsigned int resetcal_timer; 450 unsigned int checkani_timer; 451 struct timer_list timer; 452 }; 453 454 /********************/ 455 /* LED Control */ 456 /********************/ 457 458 #define ATH_LED_PIN_DEF 1 459 #define ATH_LED_PIN_9287 8 460 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ 461 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ 462 463 enum ath_led_type { 464 ATH_LED_RADIO, 465 ATH_LED_ASSOC, 466 ATH_LED_TX, 467 ATH_LED_RX 468 }; 469 470 struct ath_led { 471 struct ath_softc *sc; 472 struct led_classdev led_cdev; 473 enum ath_led_type led_type; 474 char name[32]; 475 bool registered; 476 }; 477 478 /********************/ 479 /* Main driver core */ 480 /********************/ 481 482 /* 483 * Default cache line size, in bytes. 484 * Used when PCI device not fully initialized by bootrom/BIOS 485 */ 486 #define DEFAULT_CACHELINE 32 487 #define ATH_DEFAULT_NOISE_FLOOR -95 488 #define ATH_REGCLASSIDS_MAX 10 489 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 490 #define ATH_MAX_SW_RETRIES 10 491 #define ATH_CHAN_MAX 255 492 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 493 494 /* 495 * The key cache is used for h/w cipher state and also for 496 * tracking station state such as the current tx antenna. 497 * We also setup a mapping table between key cache slot indices 498 * and station state to short-circuit node lookups on rx. 499 * Different parts have different size key caches. We handle 500 * up to ATH_KEYMAX entries (could dynamically allocate state). 501 */ 502 #define ATH_KEYMAX 128 /* max key cache size we handle */ 503 504 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 505 #define ATH_RSSI_DUMMY_MARKER 0x127 506 #define ATH_RATE_DUMMY_MARKER 0 507 508 #define SC_OP_INVALID BIT(0) 509 #define SC_OP_BEACONS BIT(1) 510 #define SC_OP_RXAGGR BIT(2) 511 #define SC_OP_TXAGGR BIT(3) 512 #define SC_OP_FULL_RESET BIT(4) 513 #define SC_OP_PREAMBLE_SHORT BIT(5) 514 #define SC_OP_PROTECT_ENABLE BIT(6) 515 #define SC_OP_RXFLUSH BIT(7) 516 #define SC_OP_LED_ASSOCIATED BIT(8) 517 #define SC_OP_WAIT_FOR_BEACON BIT(12) 518 #define SC_OP_LED_ON BIT(13) 519 #define SC_OP_SCANNING BIT(14) 520 #define SC_OP_TSF_RESET BIT(15) 521 #define SC_OP_WAIT_FOR_CAB BIT(16) 522 #define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17) 523 #define SC_OP_WAIT_FOR_TX_ACK BIT(18) 524 #define SC_OP_BEACON_SYNC BIT(19) 525 #define SC_OP_BTCOEX_ENABLED BIT(20) 526 #define SC_OP_BT_PRIORITY_DETECTED BIT(21) 527 528 struct ath_bus_ops { 529 void (*read_cachesize)(struct ath_softc *sc, int *csz); 530 void (*cleanup)(struct ath_softc *sc); 531 bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); 532 }; 533 534 struct ath_wiphy; 535 536 struct ath_softc { 537 struct ieee80211_hw *hw; 538 struct device *dev; 539 540 struct ath_common common; 541 542 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 543 struct ath_wiphy *pri_wiphy; 544 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 545 * have NULL entries */ 546 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ 547 int chan_idx; 548 int chan_is_ht; 549 struct ath_wiphy *next_wiphy; 550 struct work_struct chan_work; 551 int wiphy_select_failures; 552 unsigned long wiphy_select_first_fail; 553 struct delayed_work wiphy_work; 554 unsigned long wiphy_scheduler_int; 555 int wiphy_scheduler_index; 556 557 struct tasklet_struct intr_tq; 558 struct tasklet_struct bcon_tasklet; 559 struct ath_hw *sc_ah; 560 void __iomem *mem; 561 int irq; 562 spinlock_t sc_resetlock; 563 spinlock_t sc_serial_rw; 564 spinlock_t ani_lock; 565 spinlock_t sc_pm_lock; 566 struct mutex mutex; 567 568 u8 curbssid[ETH_ALEN]; 569 u8 bssidmask[ETH_ALEN]; 570 u32 intrstatus; 571 u32 sc_flags; /* SC_OP_* */ 572 u16 curtxpow; 573 u16 curaid; 574 u8 nbcnvifs; 575 u16 nvifs; 576 u8 tx_chainmask; 577 u8 rx_chainmask; 578 u32 keymax; 579 DECLARE_BITMAP(keymap, ATH_KEYMAX); 580 u8 splitmic; 581 bool ps_enabled; 582 unsigned long ps_usecount; 583 enum ath9k_int imask; 584 enum ath9k_ht_extprotspacing ht_extprotspacing; 585 enum ath9k_ht_macmode tx_chan_width; 586 587 struct ath_config config; 588 struct ath_rx rx; 589 struct ath_tx tx; 590 struct ath_beacon beacon; 591 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 592 const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 593 const struct ath_rate_table *cur_rate_table; 594 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 595 596 struct ath_led radio_led; 597 struct ath_led assoc_led; 598 struct ath_led tx_led; 599 struct ath_led rx_led; 600 struct delayed_work ath_led_blink_work; 601 int led_on_duration; 602 int led_off_duration; 603 int led_on_cnt; 604 int led_off_cnt; 605 606 int beacon_interval; 607 608 struct ath_ani ani; 609 #ifdef CONFIG_ATH9K_DEBUG 610 struct ath9k_debug debug; 611 #endif 612 struct ath_bus_ops *bus_ops; 613 struct ath_beacon_config cur_beacon_conf; 614 struct delayed_work tx_complete_work; 615 struct ath_btcoex_info btcoex_info; 616 }; 617 618 struct ath_wiphy { 619 struct ath_softc *sc; /* shared for all virtual wiphys */ 620 struct ieee80211_hw *hw; 621 enum ath_wiphy_state { 622 ATH_WIPHY_INACTIVE, 623 ATH_WIPHY_ACTIVE, 624 ATH_WIPHY_PAUSING, 625 ATH_WIPHY_PAUSED, 626 ATH_WIPHY_SCAN, 627 } state; 628 int chan_idx; 629 int chan_is_ht; 630 }; 631 632 int ath_reset(struct ath_softc *sc, bool retry_tx); 633 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); 634 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 635 int ath_cabq_update(struct ath_softc *); 636 637 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 638 { 639 return &ah->ah_sc->common; 640 } 641 642 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 643 { 644 return &(ath9k_hw_common(ah)->regulatory); 645 } 646 647 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) 648 { 649 sc->bus_ops->read_cachesize(sc, csz); 650 } 651 652 static inline void ath_bus_cleanup(struct ath_softc *sc) 653 { 654 sc->bus_ops->cleanup(sc); 655 } 656 657 extern struct ieee80211_ops ath9k_ops; 658 659 irqreturn_t ath_isr(int irq, void *dev); 660 void ath_cleanup(struct ath_softc *sc); 661 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid); 662 void ath_detach(struct ath_softc *sc); 663 const char *ath_mac_bb_name(u32 mac_bb_version); 664 const char *ath_rf_name(u16 rf_version); 665 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 666 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 667 struct ath9k_channel *ichan); 668 void ath_update_chainmask(struct ath_softc *sc, int is_ht); 669 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 670 struct ath9k_channel *hchan); 671 void ath_radio_enable(struct ath_softc *sc); 672 void ath_radio_disable(struct ath_softc *sc); 673 674 #ifdef CONFIG_PCI 675 int ath_pci_init(void); 676 void ath_pci_exit(void); 677 #else 678 static inline int ath_pci_init(void) { return 0; }; 679 static inline void ath_pci_exit(void) {}; 680 #endif 681 682 #ifdef CONFIG_ATHEROS_AR71XX 683 int ath_ahb_init(void); 684 void ath_ahb_exit(void); 685 #else 686 static inline int ath_ahb_init(void) { return 0; }; 687 static inline void ath_ahb_exit(void) {}; 688 #endif 689 690 void ath9k_ps_wakeup(struct ath_softc *sc); 691 void ath9k_ps_restore(struct ath_softc *sc); 692 693 void ath9k_set_bssid_mask(struct ieee80211_hw *hw); 694 int ath9k_wiphy_add(struct ath_softc *sc); 695 int ath9k_wiphy_del(struct ath_wiphy *aphy); 696 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); 697 int ath9k_wiphy_pause(struct ath_wiphy *aphy); 698 int ath9k_wiphy_unpause(struct ath_wiphy *aphy); 699 int ath9k_wiphy_select(struct ath_wiphy *aphy); 700 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); 701 void ath9k_wiphy_chan_work(struct work_struct *work); 702 bool ath9k_wiphy_started(struct ath_softc *sc); 703 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, 704 struct ath_wiphy *selected); 705 bool ath9k_wiphy_scanning(struct ath_softc *sc); 706 void ath9k_wiphy_work(struct work_struct *work); 707 bool ath9k_all_wiphys_idle(struct ath_softc *sc); 708 709 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); 710 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); 711 712 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); 713 #endif /* ATH9K_H */ 714