1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/leds.h> 23 #include <linux/completion.h> 24 #include <linux/pm_qos_params.h> 25 26 #include "debug.h" 27 #include "common.h" 28 29 /* 30 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 31 * should rely on this file or its contents. 32 */ 33 34 struct ath_node; 35 36 /* Macro to expand scalars to 64-bit objects */ 37 38 #define ito64(x) (sizeof(x) == 1) ? \ 39 (((unsigned long long int)(x)) & (0xff)) : \ 40 (sizeof(x) == 2) ? \ 41 (((unsigned long long int)(x)) & 0xffff) : \ 42 ((sizeof(x) == 4) ? \ 43 (((unsigned long long int)(x)) & 0xffffffff) : \ 44 (unsigned long long int)(x)) 45 46 /* increment with wrap-around */ 47 #define INCR(_l, _sz) do { \ 48 (_l)++; \ 49 (_l) &= ((_sz) - 1); \ 50 } while (0) 51 52 /* decrement with wrap-around */ 53 #define DECR(_l, _sz) do { \ 54 (_l)--; \ 55 (_l) &= ((_sz) - 1); \ 56 } while (0) 57 58 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 59 60 #define ATH9K_PM_QOS_DEFAULT_VALUE 55 61 62 #define TSF_TO_TU(_h,_l) \ 63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 64 65 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 66 67 struct ath_config { 68 u32 ath_aggr_prot; 69 u16 txpowlimit; 70 u8 cabqReadytime; 71 }; 72 73 /*************************/ 74 /* Descriptor Management */ 75 /*************************/ 76 77 #define ATH_TXBUF_RESET(_bf) do { \ 78 (_bf)->bf_stale = false; \ 79 (_bf)->bf_lastbf = NULL; \ 80 (_bf)->bf_next = NULL; \ 81 memset(&((_bf)->bf_state), 0, \ 82 sizeof(struct ath_buf_state)); \ 83 } while (0) 84 85 #define ATH_RXBUF_RESET(_bf) do { \ 86 (_bf)->bf_stale = false; \ 87 } while (0) 88 89 /** 90 * enum buffer_type - Buffer type flags 91 * 92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 93 * @BUF_AGGR: Indicates whether the buffer can be aggregated 94 * (used in aggregation scheduling) 95 * @BUF_XRETRY: To denote excessive retries of the buffer 96 */ 97 enum buffer_type { 98 BUF_AMPDU = BIT(2), 99 BUF_AGGR = BIT(3), 100 BUF_XRETRY = BIT(5), 101 }; 102 103 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 104 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 105 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 106 107 #define ATH_TXSTATUS_RING_SIZE 64 108 109 struct ath_descdma { 110 void *dd_desc; 111 dma_addr_t dd_desc_paddr; 112 u32 dd_desc_len; 113 struct ath_buf *dd_bufptr; 114 }; 115 116 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 117 struct list_head *head, const char *name, 118 int nbuf, int ndesc, bool is_tx); 119 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 120 struct list_head *head); 121 122 /***********/ 123 /* RX / TX */ 124 /***********/ 125 126 #define ATH_MAX_ANTENNA 3 127 #define ATH_RXBUF 512 128 #define ATH_TXBUF 512 129 #define ATH_TXBUF_RESERVE 5 130 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 131 #define ATH_TXMAXTRY 13 132 #define ATH_MGT_TXMAXTRY 4 133 134 #define TID_TO_WME_AC(_tid) \ 135 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 136 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 137 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 138 WME_AC_VO) 139 140 #define ADDBA_EXCHANGE_ATTEMPTS 10 141 #define ATH_AGGR_DELIM_SZ 4 142 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 143 /* number of delimiters for encryption padding */ 144 #define ATH_AGGR_ENCRYPTDELIM 10 145 /* minimum h/w qdepth to be sustained to maximize aggregation */ 146 #define ATH_AGGR_MIN_QDEPTH 2 147 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 148 149 #define IEEE80211_SEQ_SEQ_SHIFT 4 150 #define IEEE80211_SEQ_MAX 4096 151 #define IEEE80211_WEP_IVLEN 3 152 #define IEEE80211_WEP_KIDLEN 1 153 #define IEEE80211_WEP_CRCLEN 4 154 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 155 (IEEE80211_WEP_IVLEN + \ 156 IEEE80211_WEP_KIDLEN + \ 157 IEEE80211_WEP_CRCLEN)) 158 159 /* return whether a bit at index _n in bitmap _bm is set 160 * _sz is the size of the bitmap */ 161 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 162 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 163 164 /* return block-ack bitmap index given sequence and starting sequence */ 165 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 166 167 /* returns delimiter padding required given the packet length */ 168 #define ATH_AGGR_GET_NDELIM(_len) \ 169 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 170 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 171 172 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 173 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 174 175 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 176 177 #define ATH_TX_COMPLETE_POLL_INT 1000 178 179 enum ATH_AGGR_STATUS { 180 ATH_AGGR_DONE, 181 ATH_AGGR_BAW_CLOSED, 182 ATH_AGGR_LIMITED, 183 }; 184 185 #define ATH_TXFIFO_DEPTH 8 186 struct ath_txq { 187 u32 axq_qnum; 188 u32 *axq_link; 189 struct list_head axq_q; 190 spinlock_t axq_lock; 191 u32 axq_depth; 192 u32 axq_ampdu_depth; 193 bool stopped; 194 bool axq_tx_inprogress; 195 struct list_head axq_acq; 196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 197 struct list_head txq_fifo_pending; 198 u8 txq_headidx; 199 u8 txq_tailidx; 200 int pending_frames; 201 }; 202 203 struct ath_atx_ac { 204 struct ath_txq *txq; 205 int sched; 206 struct list_head list; 207 struct list_head tid_q; 208 }; 209 210 struct ath_frame_info { 211 int framelen; 212 u32 keyix; 213 enum ath9k_key_type keytype; 214 u8 retries; 215 u16 seqno; 216 }; 217 218 struct ath_buf_state { 219 u8 bf_type; 220 u8 bfs_paprd; 221 unsigned long bfs_paprd_timestamp; 222 enum ath9k_internal_frame_type bfs_ftype; 223 }; 224 225 struct ath_buf { 226 struct list_head list; 227 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 228 an aggregate) */ 229 struct ath_buf *bf_next; /* next subframe in the aggregate */ 230 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 231 void *bf_desc; /* virtual addr of desc */ 232 dma_addr_t bf_daddr; /* physical addr of desc */ 233 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 234 bool bf_stale; 235 u16 bf_flags; 236 struct ath_buf_state bf_state; 237 struct ath_wiphy *aphy; 238 }; 239 240 struct ath_atx_tid { 241 struct list_head list; 242 struct list_head buf_q; 243 struct ath_node *an; 244 struct ath_atx_ac *ac; 245 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 246 u16 seq_start; 247 u16 seq_next; 248 u16 baw_size; 249 int tidno; 250 int baw_head; /* first un-acked tx buffer */ 251 int baw_tail; /* next unused tx buffer slot */ 252 int sched; 253 int paused; 254 u8 state; 255 }; 256 257 struct ath_node { 258 struct ath_common *common; 259 struct ath_atx_tid tid[WME_NUM_TID]; 260 struct ath_atx_ac ac[WME_NUM_AC]; 261 u16 maxampdu; 262 u8 mpdudensity; 263 }; 264 265 #define AGGR_CLEANUP BIT(1) 266 #define AGGR_ADDBA_COMPLETE BIT(2) 267 #define AGGR_ADDBA_PROGRESS BIT(3) 268 269 struct ath_tx_control { 270 struct ath_txq *txq; 271 struct ath_node *an; 272 int if_id; 273 enum ath9k_internal_frame_type frame_type; 274 u8 paprd; 275 }; 276 277 #define ATH_TX_ERROR 0x01 278 #define ATH_TX_XRETRY 0x02 279 #define ATH_TX_BAR 0x04 280 281 struct ath_tx { 282 u16 seq_no; 283 u32 txqsetup; 284 spinlock_t txbuflock; 285 struct list_head txbuf; 286 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 287 struct ath_descdma txdma; 288 struct ath_txq *txq_map[WME_NUM_AC]; 289 }; 290 291 struct ath_rx_edma { 292 struct sk_buff_head rx_fifo; 293 struct sk_buff_head rx_buffers; 294 u32 rx_fifo_hwsize; 295 }; 296 297 struct ath_rx { 298 u8 defant; 299 u8 rxotherant; 300 u32 *rxlink; 301 unsigned int rxfilter; 302 spinlock_t rxbuflock; 303 struct list_head rxbuf; 304 struct ath_descdma rxdma; 305 struct ath_buf *rx_bufptr; 306 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 307 }; 308 309 int ath_startrecv(struct ath_softc *sc); 310 bool ath_stoprecv(struct ath_softc *sc); 311 void ath_flushrecv(struct ath_softc *sc); 312 u32 ath_calcrxfilter(struct ath_softc *sc); 313 int ath_rx_init(struct ath_softc *sc, int nbufs); 314 void ath_rx_cleanup(struct ath_softc *sc); 315 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 316 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 317 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 318 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 319 void ath_draintxq(struct ath_softc *sc, 320 struct ath_txq *txq, bool retry_tx); 321 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 322 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 323 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 324 int ath_tx_init(struct ath_softc *sc, int nbufs); 325 void ath_tx_cleanup(struct ath_softc *sc); 326 int ath_txq_update(struct ath_softc *sc, int qnum, 327 struct ath9k_tx_queue_info *q); 328 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 329 struct ath_tx_control *txctl); 330 void ath_tx_tasklet(struct ath_softc *sc); 331 void ath_tx_edma_tasklet(struct ath_softc *sc); 332 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 333 u16 tid, u16 *ssn); 334 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 335 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 336 337 /********/ 338 /* VIFs */ 339 /********/ 340 341 struct ath_vif { 342 int av_bslot; 343 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 344 enum nl80211_iftype av_opmode; 345 struct ath_buf *av_bcbuf; 346 struct ath_tx_control av_btxctl; 347 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ 348 }; 349 350 /*******************/ 351 /* Beacon Handling */ 352 /*******************/ 353 354 /* 355 * Regardless of the number of beacons we stagger, (i.e. regardless of the 356 * number of BSSIDs) if a given beacon does not go out even after waiting this 357 * number of beacon intervals, the game's up. 358 */ 359 #define BSTUCK_THRESH (9 * ATH_BCBUF) 360 #define ATH_BCBUF 4 361 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 362 #define ATH_DEFAULT_BMISS_LIMIT 10 363 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 364 365 struct ath_beacon_config { 366 u16 beacon_interval; 367 u16 listen_interval; 368 u16 dtim_period; 369 u16 bmiss_timeout; 370 u8 dtim_count; 371 }; 372 373 struct ath_beacon { 374 enum { 375 OK, /* no change needed */ 376 UPDATE, /* update pending */ 377 COMMIT /* beacon sent, commit change */ 378 } updateslot; /* slot time update fsm */ 379 380 u32 beaconq; 381 u32 bmisscnt; 382 u32 ast_be_xmit; 383 u64 bc_tstamp; 384 struct ieee80211_vif *bslot[ATH_BCBUF]; 385 struct ath_wiphy *bslot_aphy[ATH_BCBUF]; 386 int slottime; 387 int slotupdate; 388 struct ath9k_tx_queue_info beacon_qi; 389 struct ath_descdma bdma; 390 struct ath_txq *cabq; 391 struct list_head bbuf; 392 }; 393 394 void ath_beacon_tasklet(unsigned long data); 395 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 396 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 397 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 398 int ath_beaconq_config(struct ath_softc *sc); 399 400 /*******/ 401 /* ANI */ 402 /*******/ 403 404 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 405 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 406 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 407 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 408 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 409 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 410 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 411 412 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 413 414 void ath_hw_check(struct work_struct *work); 415 void ath_paprd_calibrate(struct work_struct *work); 416 void ath_ani_calibrate(unsigned long data); 417 418 /**********/ 419 /* BTCOEX */ 420 /**********/ 421 422 struct ath_btcoex { 423 bool hw_timer_enabled; 424 spinlock_t btcoex_lock; 425 struct timer_list period_timer; /* Timer for BT period */ 426 u32 bt_priority_cnt; 427 unsigned long bt_priority_time; 428 int bt_stomp_type; /* Types of BT stomping */ 429 u32 btcoex_no_stomp; /* in usec */ 430 u32 btcoex_period; /* in usec */ 431 u32 btscan_no_stomp; /* in usec */ 432 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 433 }; 434 435 int ath_init_btcoex_timer(struct ath_softc *sc); 436 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 437 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 438 439 /********************/ 440 /* LED Control */ 441 /********************/ 442 443 #define ATH_LED_PIN_DEF 1 444 #define ATH_LED_PIN_9287 8 445 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ 446 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ 447 448 enum ath_led_type { 449 ATH_LED_RADIO, 450 ATH_LED_ASSOC, 451 ATH_LED_TX, 452 ATH_LED_RX 453 }; 454 455 struct ath_led { 456 struct ath_softc *sc; 457 struct led_classdev led_cdev; 458 enum ath_led_type led_type; 459 char name[32]; 460 bool registered; 461 }; 462 463 void ath_init_leds(struct ath_softc *sc); 464 void ath_deinit_leds(struct ath_softc *sc); 465 466 /* Antenna diversity/combining */ 467 #define ATH_ANT_RX_CURRENT_SHIFT 4 468 #define ATH_ANT_RX_MAIN_SHIFT 2 469 #define ATH_ANT_RX_MASK 0x3 470 471 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 472 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 473 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 474 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 475 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 476 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 477 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 478 479 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3 480 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 481 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 482 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 483 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 484 485 enum ath9k_ant_div_comb_lna_conf { 486 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 487 ATH_ANT_DIV_COMB_LNA2, 488 ATH_ANT_DIV_COMB_LNA1, 489 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 490 }; 491 492 struct ath_ant_comb { 493 u16 count; 494 u16 total_pkt_count; 495 bool scan; 496 bool scan_not_start; 497 int main_total_rssi; 498 int alt_total_rssi; 499 int alt_recv_cnt; 500 int main_recv_cnt; 501 int rssi_lna1; 502 int rssi_lna2; 503 int rssi_add; 504 int rssi_sub; 505 int rssi_first; 506 int rssi_second; 507 int rssi_third; 508 bool alt_good; 509 int quick_scan_cnt; 510 int main_conf; 511 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 512 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 513 int first_bias; 514 int second_bias; 515 bool first_ratio; 516 bool second_ratio; 517 unsigned long scan_start_time; 518 }; 519 520 /********************/ 521 /* Main driver core */ 522 /********************/ 523 524 /* 525 * Default cache line size, in bytes. 526 * Used when PCI device not fully initialized by bootrom/BIOS 527 */ 528 #define DEFAULT_CACHELINE 32 529 #define ATH_REGCLASSIDS_MAX 10 530 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 531 #define ATH_MAX_SW_RETRIES 10 532 #define ATH_CHAN_MAX 255 533 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 534 535 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 536 #define ATH_RATE_DUMMY_MARKER 0 537 538 #define SC_OP_INVALID BIT(0) 539 #define SC_OP_BEACONS BIT(1) 540 #define SC_OP_RXAGGR BIT(2) 541 #define SC_OP_TXAGGR BIT(3) 542 #define SC_OP_OFFCHANNEL BIT(4) 543 #define SC_OP_PREAMBLE_SHORT BIT(5) 544 #define SC_OP_PROTECT_ENABLE BIT(6) 545 #define SC_OP_RXFLUSH BIT(7) 546 #define SC_OP_LED_ASSOCIATED BIT(8) 547 #define SC_OP_LED_ON BIT(9) 548 #define SC_OP_TSF_RESET BIT(11) 549 #define SC_OP_BT_PRIORITY_DETECTED BIT(12) 550 #define SC_OP_BT_SCAN BIT(13) 551 #define SC_OP_ANI_RUN BIT(14) 552 #define SC_OP_ENABLE_APM BIT(15) 553 554 /* Powersave flags */ 555 #define PS_WAIT_FOR_BEACON BIT(0) 556 #define PS_WAIT_FOR_CAB BIT(1) 557 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 558 #define PS_WAIT_FOR_TX_ACK BIT(3) 559 #define PS_BEACON_SYNC BIT(4) 560 561 struct ath_wiphy; 562 struct ath_rate_table; 563 564 struct ath_softc { 565 struct ieee80211_hw *hw; 566 struct device *dev; 567 568 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 569 struct ath_wiphy *pri_wiphy; 570 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 571 * have NULL entries */ 572 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ 573 int chan_idx; 574 int chan_is_ht; 575 struct ath_wiphy *next_wiphy; 576 struct work_struct chan_work; 577 int wiphy_select_failures; 578 unsigned long wiphy_select_first_fail; 579 struct delayed_work wiphy_work; 580 unsigned long wiphy_scheduler_int; 581 int wiphy_scheduler_index; 582 struct survey_info *cur_survey; 583 struct survey_info survey[ATH9K_NUM_CHANNELS]; 584 585 struct tasklet_struct intr_tq; 586 struct tasklet_struct bcon_tasklet; 587 struct ath_hw *sc_ah; 588 void __iomem *mem; 589 int irq; 590 spinlock_t sc_serial_rw; 591 spinlock_t sc_pm_lock; 592 spinlock_t sc_pcu_lock; 593 struct mutex mutex; 594 struct work_struct paprd_work; 595 struct work_struct hw_check_work; 596 struct completion paprd_complete; 597 598 u32 intrstatus; 599 u32 sc_flags; /* SC_OP_* */ 600 u16 ps_flags; /* PS_* */ 601 u16 curtxpow; 602 u8 nbcnvifs; 603 u16 nvifs; 604 bool ps_enabled; 605 bool ps_idle; 606 unsigned long ps_usecount; 607 608 struct ath_config config; 609 struct ath_rx rx; 610 struct ath_tx tx; 611 struct ath_beacon beacon; 612 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 613 614 struct ath_led radio_led; 615 struct ath_led assoc_led; 616 struct ath_led tx_led; 617 struct ath_led rx_led; 618 struct delayed_work ath_led_blink_work; 619 int led_on_duration; 620 int led_off_duration; 621 int led_on_cnt; 622 int led_off_cnt; 623 624 int beacon_interval; 625 626 #ifdef CONFIG_ATH9K_DEBUGFS 627 struct ath9k_debug debug; 628 #endif 629 struct ath_beacon_config cur_beacon_conf; 630 struct delayed_work tx_complete_work; 631 struct ath_btcoex btcoex; 632 633 struct ath_descdma txsdma; 634 635 struct ath_ant_comb ant_comb; 636 637 struct pm_qos_request_list pm_qos_req; 638 }; 639 640 struct ath_wiphy { 641 struct ath_softc *sc; /* shared for all virtual wiphys */ 642 struct ieee80211_hw *hw; 643 struct ath9k_hw_cal_data caldata; 644 enum ath_wiphy_state { 645 ATH_WIPHY_INACTIVE, 646 ATH_WIPHY_ACTIVE, 647 ATH_WIPHY_PAUSING, 648 ATH_WIPHY_PAUSED, 649 ATH_WIPHY_SCAN, 650 } state; 651 bool idle; 652 int chan_idx; 653 int chan_is_ht; 654 int last_rssi; 655 }; 656 657 void ath9k_tasklet(unsigned long data); 658 int ath_reset(struct ath_softc *sc, bool retry_tx); 659 int ath_cabq_update(struct ath_softc *); 660 661 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 662 { 663 common->bus_ops->read_cachesize(common, csz); 664 } 665 666 extern struct ieee80211_ops ath9k_ops; 667 extern int ath9k_modparam_nohwcrypt; 668 extern int led_blink; 669 extern int ath9k_pm_qos_value; 670 extern bool is_ath9k_unloaded; 671 672 irqreturn_t ath_isr(int irq, void *dev); 673 void ath9k_init_crypto(struct ath_softc *sc); 674 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, 675 const struct ath_bus_ops *bus_ops); 676 void ath9k_deinit_device(struct ath_softc *sc); 677 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 678 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 679 struct ath9k_channel *ichan); 680 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 681 struct ath9k_channel *hchan); 682 683 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); 684 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); 685 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); 686 687 #ifdef CONFIG_PCI 688 int ath_pci_init(void); 689 void ath_pci_exit(void); 690 #else 691 static inline int ath_pci_init(void) { return 0; }; 692 static inline void ath_pci_exit(void) {}; 693 #endif 694 695 #ifdef CONFIG_ATHEROS_AR71XX 696 int ath_ahb_init(void); 697 void ath_ahb_exit(void); 698 #else 699 static inline int ath_ahb_init(void) { return 0; }; 700 static inline void ath_ahb_exit(void) {}; 701 #endif 702 703 void ath9k_ps_wakeup(struct ath_softc *sc); 704 void ath9k_ps_restore(struct ath_softc *sc); 705 706 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 707 708 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 709 int ath9k_wiphy_add(struct ath_softc *sc); 710 int ath9k_wiphy_del(struct ath_wiphy *aphy); 711 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype); 712 int ath9k_wiphy_pause(struct ath_wiphy *aphy); 713 int ath9k_wiphy_unpause(struct ath_wiphy *aphy); 714 int ath9k_wiphy_select(struct ath_wiphy *aphy); 715 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); 716 void ath9k_wiphy_chan_work(struct work_struct *work); 717 bool ath9k_wiphy_started(struct ath_softc *sc); 718 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, 719 struct ath_wiphy *selected); 720 bool ath9k_wiphy_scanning(struct ath_softc *sc); 721 void ath9k_wiphy_work(struct work_struct *work); 722 bool ath9k_all_wiphys_idle(struct ath_softc *sc); 723 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); 724 725 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); 726 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); 727 728 void ath_start_rfkill_poll(struct ath_softc *sc); 729 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 730 731 #endif /* ATH9K_H */ 732