1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 #include "spectral.h" 31 32 struct ath_node; 33 34 extern struct ieee80211_ops ath9k_ops; 35 extern int ath9k_modparam_nohwcrypt; 36 extern int led_blink; 37 extern bool is_ath9k_unloaded; 38 39 struct ath_config { 40 u16 txpowlimit; 41 }; 42 43 /*************************/ 44 /* Descriptor Management */ 45 /*************************/ 46 47 #define ATH_TXSTATUS_RING_SIZE 512 48 49 /* Macro to expand scalars to 64-bit objects */ 50 #define ito64(x) (sizeof(x) == 1) ? \ 51 (((unsigned long long int)(x)) & (0xff)) : \ 52 (sizeof(x) == 2) ? \ 53 (((unsigned long long int)(x)) & 0xffff) : \ 54 ((sizeof(x) == 4) ? \ 55 (((unsigned long long int)(x)) & 0xffffffff) : \ 56 (unsigned long long int)(x)) 57 58 #define ATH_TXBUF_RESET(_bf) do { \ 59 (_bf)->bf_lastbf = NULL; \ 60 (_bf)->bf_next = NULL; \ 61 memset(&((_bf)->bf_state), 0, \ 62 sizeof(struct ath_buf_state)); \ 63 } while (0) 64 65 #define DS2PHYS(_dd, _ds) \ 66 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 67 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 68 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 69 70 struct ath_descdma { 71 void *dd_desc; 72 dma_addr_t dd_desc_paddr; 73 u32 dd_desc_len; 74 }; 75 76 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 77 struct list_head *head, const char *name, 78 int nbuf, int ndesc, bool is_tx); 79 80 /***********/ 81 /* RX / TX */ 82 /***********/ 83 84 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 85 86 /* increment with wrap-around */ 87 #define INCR(_l, _sz) do { \ 88 (_l)++; \ 89 (_l) &= ((_sz) - 1); \ 90 } while (0) 91 92 #define ATH_RXBUF 512 93 #define ATH_TXBUF 512 94 #define ATH_TXBUF_RESERVE 5 95 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 96 #define ATH_TXMAXTRY 13 97 #define ATH_MAX_SW_RETRIES 30 98 99 #define TID_TO_WME_AC(_tid) \ 100 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ 101 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ 102 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ 103 IEEE80211_AC_VO) 104 105 #define ATH_AGGR_DELIM_SZ 4 106 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 107 /* number of delimiters for encryption padding */ 108 #define ATH_AGGR_ENCRYPTDELIM 10 109 /* minimum h/w qdepth to be sustained to maximize aggregation */ 110 #define ATH_AGGR_MIN_QDEPTH 2 111 /* minimum h/w qdepth for non-aggregated traffic */ 112 #define ATH_NON_AGGR_MIN_QDEPTH 8 113 #define ATH_TX_COMPLETE_POLL_INT 1000 114 #define ATH_TXFIFO_DEPTH 8 115 #define ATH_TX_ERROR 0x01 116 117 #define IEEE80211_SEQ_SEQ_SHIFT 4 118 #define IEEE80211_SEQ_MAX 4096 119 #define IEEE80211_WEP_IVLEN 3 120 #define IEEE80211_WEP_KIDLEN 1 121 #define IEEE80211_WEP_CRCLEN 4 122 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 123 (IEEE80211_WEP_IVLEN + \ 124 IEEE80211_WEP_KIDLEN + \ 125 IEEE80211_WEP_CRCLEN)) 126 127 /* return whether a bit at index _n in bitmap _bm is set 128 * _sz is the size of the bitmap */ 129 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 130 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 131 132 /* return block-ack bitmap index given sequence and starting sequence */ 133 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 134 135 /* return the seqno for _start + _offset */ 136 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 137 138 /* returns delimiter padding required given the packet length */ 139 #define ATH_AGGR_GET_NDELIM(_len) \ 140 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 141 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 142 143 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 144 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 145 146 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 147 148 #define IS_HT_RATE(rate) (rate & 0x80) 149 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 150 #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf)) 151 152 enum { 153 WLAN_RC_PHY_OFDM, 154 WLAN_RC_PHY_CCK, 155 }; 156 157 struct ath_txq { 158 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 159 u32 axq_qnum; /* ath9k hardware queue number */ 160 void *axq_link; 161 struct list_head axq_q; 162 spinlock_t axq_lock; 163 u32 axq_depth; 164 u32 axq_ampdu_depth; 165 bool stopped; 166 bool axq_tx_inprogress; 167 struct list_head axq_acq; 168 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 169 u8 txq_headidx; 170 u8 txq_tailidx; 171 int pending_frames; 172 struct sk_buff_head complete_q; 173 }; 174 175 struct ath_atx_ac { 176 struct ath_txq *txq; 177 struct list_head list; 178 struct list_head tid_q; 179 bool clear_ps_filter; 180 bool sched; 181 }; 182 183 struct ath_frame_info { 184 struct ath_buf *bf; 185 int framelen; 186 enum ath9k_key_type keytype; 187 u8 keyix; 188 u8 rtscts_rate; 189 u8 retries : 7; 190 u8 baw_tracked : 1; 191 }; 192 193 struct ath_rxbuf { 194 struct list_head list; 195 struct sk_buff *bf_mpdu; 196 void *bf_desc; 197 dma_addr_t bf_daddr; 198 dma_addr_t bf_buf_addr; 199 }; 200 201 /** 202 * enum buffer_type - Buffer type flags 203 * 204 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 205 * @BUF_AGGR: Indicates whether the buffer can be aggregated 206 * (used in aggregation scheduling) 207 */ 208 enum buffer_type { 209 BUF_AMPDU = BIT(0), 210 BUF_AGGR = BIT(1), 211 }; 212 213 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 214 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 215 216 struct ath_buf_state { 217 u8 bf_type; 218 u8 bfs_paprd; 219 u8 ndelim; 220 bool stale; 221 u16 seqno; 222 unsigned long bfs_paprd_timestamp; 223 }; 224 225 struct ath_buf { 226 struct list_head list; 227 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 228 an aggregate) */ 229 struct ath_buf *bf_next; /* next subframe in the aggregate */ 230 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 231 void *bf_desc; /* virtual addr of desc */ 232 dma_addr_t bf_daddr; /* physical addr of desc */ 233 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 234 struct ieee80211_tx_rate rates[4]; 235 struct ath_buf_state bf_state; 236 }; 237 238 struct ath_atx_tid { 239 struct list_head list; 240 struct sk_buff_head buf_q; 241 struct sk_buff_head retry_q; 242 struct ath_node *an; 243 struct ath_atx_ac *ac; 244 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 245 u16 seq_start; 246 u16 seq_next; 247 u16 baw_size; 248 u8 tidno; 249 int baw_head; /* first un-acked tx buffer */ 250 int baw_tail; /* next unused tx buffer slot */ 251 252 s8 bar_index; 253 bool sched; 254 bool paused; 255 bool active; 256 }; 257 258 struct ath_node { 259 struct ath_softc *sc; 260 struct ieee80211_sta *sta; /* station struct we're part of */ 261 struct ieee80211_vif *vif; /* interface with which we're associated */ 262 struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; 263 struct ath_atx_ac ac[IEEE80211_NUM_ACS]; 264 265 u16 maxampdu; 266 u8 mpdudensity; 267 s8 ps_key; 268 269 bool sleeping; 270 bool no_ps_filter; 271 272 #ifdef CONFIG_ATH9K_STATION_STATISTICS 273 struct ath_rx_rate_stats rx_rate_stats; 274 #endif 275 }; 276 277 struct ath_tx_control { 278 struct ath_txq *txq; 279 struct ath_node *an; 280 u8 paprd; 281 struct ieee80211_sta *sta; 282 }; 283 284 285 /** 286 * @txq_map: Index is mac80211 queue number. This is 287 * not necessarily the same as the hardware queue number 288 * (axq_qnum). 289 */ 290 struct ath_tx { 291 u16 seq_no; 292 u32 txqsetup; 293 spinlock_t txbuflock; 294 struct list_head txbuf; 295 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 296 struct ath_descdma txdma; 297 struct ath_txq *txq_map[IEEE80211_NUM_ACS]; 298 struct ath_txq *uapsdq; 299 u32 txq_max_pending[IEEE80211_NUM_ACS]; 300 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; 301 }; 302 303 struct ath_rx_edma { 304 struct sk_buff_head rx_fifo; 305 u32 rx_fifo_hwsize; 306 }; 307 308 struct ath_rx { 309 u8 defant; 310 u8 rxotherant; 311 bool discard_next; 312 u32 *rxlink; 313 u32 num_pkts; 314 unsigned int rxfilter; 315 struct list_head rxbuf; 316 struct ath_descdma rxdma; 317 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 318 319 struct ath_rxbuf *buf_hold; 320 struct sk_buff *frag; 321 322 u32 ampdu_ref; 323 }; 324 325 int ath_startrecv(struct ath_softc *sc); 326 bool ath_stoprecv(struct ath_softc *sc); 327 u32 ath_calcrxfilter(struct ath_softc *sc); 328 int ath_rx_init(struct ath_softc *sc, int nbufs); 329 void ath_rx_cleanup(struct ath_softc *sc); 330 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 331 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 332 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 333 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 334 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 335 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 336 bool ath_drain_all_txq(struct ath_softc *sc); 337 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); 338 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 339 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 340 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 341 int ath_tx_init(struct ath_softc *sc, int nbufs); 342 int ath_txq_update(struct ath_softc *sc, int qnum, 343 struct ath9k_tx_queue_info *q); 344 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 345 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 346 struct ath_tx_control *txctl); 347 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 348 struct sk_buff *skb); 349 void ath_tx_tasklet(struct ath_softc *sc); 350 void ath_tx_edma_tasklet(struct ath_softc *sc); 351 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 352 u16 tid, u16 *ssn); 353 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 354 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 355 356 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 357 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 358 struct ath_node *an); 359 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 360 struct ieee80211_sta *sta, 361 u16 tids, int nframes, 362 enum ieee80211_frame_release_type reason, 363 bool more_data); 364 365 /********/ 366 /* VIFs */ 367 /********/ 368 369 struct ath_vif { 370 struct ath_node mcast_node; 371 int av_bslot; 372 bool primary_sta_vif; 373 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 374 struct ath_buf *av_bcbuf; 375 }; 376 377 struct ath9k_vif_iter_data { 378 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ 379 u8 mask[ETH_ALEN]; /* bssid mask */ 380 bool has_hw_macaddr; 381 382 int naps; /* number of AP vifs */ 383 int nmeshes; /* number of mesh vifs */ 384 int nstations; /* number of station vifs */ 385 int nwds; /* number of WDS vifs */ 386 int nadhocs; /* number of adhoc vifs */ 387 }; 388 389 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 390 struct ieee80211_vif *vif, 391 struct ath9k_vif_iter_data *iter_data); 392 393 /*******************/ 394 /* Beacon Handling */ 395 /*******************/ 396 397 /* 398 * Regardless of the number of beacons we stagger, (i.e. regardless of the 399 * number of BSSIDs) if a given beacon does not go out even after waiting this 400 * number of beacon intervals, the game's up. 401 */ 402 #define BSTUCK_THRESH 9 403 #define ATH_BCBUF 8 404 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 405 #define ATH_DEFAULT_BMISS_LIMIT 10 406 407 #define TSF_TO_TU(_h,_l) \ 408 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 409 410 struct ath_beacon { 411 enum { 412 OK, /* no change needed */ 413 UPDATE, /* update pending */ 414 COMMIT /* beacon sent, commit change */ 415 } updateslot; /* slot time update fsm */ 416 417 u32 beaconq; 418 u32 bmisscnt; 419 struct ieee80211_vif *bslot[ATH_BCBUF]; 420 int slottime; 421 int slotupdate; 422 struct ath_descdma bdma; 423 struct ath_txq *cabq; 424 struct list_head bbuf; 425 426 bool tx_processed; 427 bool tx_last; 428 }; 429 430 void ath9k_beacon_tasklet(unsigned long data); 431 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 432 u32 changed); 433 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 434 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 435 void ath9k_set_beacon(struct ath_softc *sc); 436 bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif); 437 void ath9k_csa_update(struct ath_softc *sc); 438 439 /*******************/ 440 /* Link Monitoring */ 441 /*******************/ 442 443 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 444 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 445 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 446 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 447 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 448 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 449 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 450 #define ATH_ANI_MAX_SKIP_COUNT 10 451 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 452 #define ATH_PLL_WORK_INTERVAL 100 453 454 void ath_tx_complete_poll_work(struct work_struct *work); 455 void ath_reset_work(struct work_struct *work); 456 bool ath_hw_check(struct ath_softc *sc); 457 void ath_hw_pll_work(struct work_struct *work); 458 void ath_paprd_calibrate(struct work_struct *work); 459 void ath_ani_calibrate(unsigned long data); 460 void ath_start_ani(struct ath_softc *sc); 461 void ath_stop_ani(struct ath_softc *sc); 462 void ath_check_ani(struct ath_softc *sc); 463 int ath_update_survey_stats(struct ath_softc *sc); 464 void ath_update_survey_nf(struct ath_softc *sc, int channel); 465 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 466 void ath_ps_full_sleep(unsigned long data); 467 468 /**********/ 469 /* BTCOEX */ 470 /**********/ 471 472 #define ATH_DUMP_BTCOEX(_s, _val) \ 473 do { \ 474 len += scnprintf(buf + len, size - len, \ 475 "%20s : %10d\n", _s, (_val)); \ 476 } while (0) 477 478 enum bt_op_flags { 479 BT_OP_PRIORITY_DETECTED, 480 BT_OP_SCAN, 481 }; 482 483 struct ath_btcoex { 484 spinlock_t btcoex_lock; 485 struct timer_list period_timer; /* Timer for BT period */ 486 struct timer_list no_stomp_timer; 487 u32 bt_priority_cnt; 488 unsigned long bt_priority_time; 489 unsigned long op_flags; 490 int bt_stomp_type; /* Types of BT stomping */ 491 u32 btcoex_no_stomp; /* in msec */ 492 u32 btcoex_period; /* in msec */ 493 u32 btscan_no_stomp; /* in msec */ 494 u32 duty_cycle; 495 u32 bt_wait_time; 496 int rssi_count; 497 struct ath_mci_profile mci; 498 u8 stomp_audio; 499 }; 500 501 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 502 int ath9k_init_btcoex(struct ath_softc *sc); 503 void ath9k_deinit_btcoex(struct ath_softc *sc); 504 void ath9k_start_btcoex(struct ath_softc *sc); 505 void ath9k_stop_btcoex(struct ath_softc *sc); 506 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 507 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 508 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 509 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 510 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 511 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); 512 #else 513 static inline int ath9k_init_btcoex(struct ath_softc *sc) 514 { 515 return 0; 516 } 517 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 518 { 519 } 520 static inline void ath9k_start_btcoex(struct ath_softc *sc) 521 { 522 } 523 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 524 { 525 } 526 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 527 u32 status) 528 { 529 } 530 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 531 u32 max_4ms_framelen) 532 { 533 return 0; 534 } 535 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 536 { 537 } 538 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) 539 { 540 return 0; 541 } 542 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 543 544 /********************/ 545 /* LED Control */ 546 /********************/ 547 548 #define ATH_LED_PIN_DEF 1 549 #define ATH_LED_PIN_9287 8 550 #define ATH_LED_PIN_9300 10 551 #define ATH_LED_PIN_9485 6 552 #define ATH_LED_PIN_9462 4 553 554 #ifdef CONFIG_MAC80211_LEDS 555 void ath_init_leds(struct ath_softc *sc); 556 void ath_deinit_leds(struct ath_softc *sc); 557 void ath_fill_led_pin(struct ath_softc *sc); 558 #else 559 static inline void ath_init_leds(struct ath_softc *sc) 560 { 561 } 562 563 static inline void ath_deinit_leds(struct ath_softc *sc) 564 { 565 } 566 static inline void ath_fill_led_pin(struct ath_softc *sc) 567 { 568 } 569 #endif 570 571 /************************/ 572 /* Wake on Wireless LAN */ 573 /************************/ 574 575 struct ath9k_wow_pattern { 576 u8 pattern_bytes[MAX_PATTERN_SIZE]; 577 u8 mask_bytes[MAX_PATTERN_SIZE]; 578 u32 pattern_len; 579 }; 580 581 #ifdef CONFIG_ATH9K_WOW 582 void ath9k_init_wow(struct ieee80211_hw *hw); 583 int ath9k_suspend(struct ieee80211_hw *hw, 584 struct cfg80211_wowlan *wowlan); 585 int ath9k_resume(struct ieee80211_hw *hw); 586 void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); 587 #else 588 static inline void ath9k_init_wow(struct ieee80211_hw *hw) 589 { 590 } 591 static inline int ath9k_suspend(struct ieee80211_hw *hw, 592 struct cfg80211_wowlan *wowlan) 593 { 594 return 0; 595 } 596 static inline int ath9k_resume(struct ieee80211_hw *hw) 597 { 598 return 0; 599 } 600 static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 601 { 602 } 603 #endif /* CONFIG_ATH9K_WOW */ 604 605 /*******************************/ 606 /* Antenna diversity/combining */ 607 /*******************************/ 608 609 #define ATH_ANT_RX_CURRENT_SHIFT 4 610 #define ATH_ANT_RX_MAIN_SHIFT 2 611 #define ATH_ANT_RX_MASK 0x3 612 613 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 614 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 615 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 616 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 617 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 618 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 619 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 620 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 621 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 622 623 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 624 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 625 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 626 627 struct ath_ant_comb { 628 u16 count; 629 u16 total_pkt_count; 630 bool scan; 631 bool scan_not_start; 632 int main_total_rssi; 633 int alt_total_rssi; 634 int alt_recv_cnt; 635 int main_recv_cnt; 636 int rssi_lna1; 637 int rssi_lna2; 638 int rssi_add; 639 int rssi_sub; 640 int rssi_first; 641 int rssi_second; 642 int rssi_third; 643 int ant_ratio; 644 int ant_ratio2; 645 bool alt_good; 646 int quick_scan_cnt; 647 enum ath9k_ant_div_comb_lna_conf main_conf; 648 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 649 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 650 bool first_ratio; 651 bool second_ratio; 652 unsigned long scan_start_time; 653 654 /* 655 * Card-specific config values. 656 */ 657 int low_rssi_thresh; 658 int fast_div_bias; 659 }; 660 661 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 662 663 /********************/ 664 /* Main driver core */ 665 /********************/ 666 667 #define ATH9K_PCI_CUS198 0x0001 668 #define ATH9K_PCI_CUS230 0x0002 669 #define ATH9K_PCI_CUS217 0x0004 670 #define ATH9K_PCI_CUS252 0x0008 671 #define ATH9K_PCI_WOW 0x0010 672 #define ATH9K_PCI_BT_ANT_DIV 0x0020 673 #define ATH9K_PCI_D3_L1_WAR 0x0040 674 #define ATH9K_PCI_AR9565_1ANT 0x0080 675 #define ATH9K_PCI_AR9565_2ANT 0x0100 676 #define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 677 #define ATH9K_PCI_KILLER 0x0400 678 679 /* 680 * Default cache line size, in bytes. 681 * Used when PCI device not fully initialized by bootrom/BIOS 682 */ 683 #define DEFAULT_CACHELINE 32 684 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 685 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 686 #define MAX_GTT_CNT 5 687 688 /* Powersave flags */ 689 #define PS_WAIT_FOR_BEACON BIT(0) 690 #define PS_WAIT_FOR_CAB BIT(1) 691 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 692 #define PS_WAIT_FOR_TX_ACK BIT(3) 693 #define PS_BEACON_SYNC BIT(4) 694 #define PS_WAIT_FOR_ANI BIT(5) 695 696 struct ath_softc { 697 struct ieee80211_hw *hw; 698 struct device *dev; 699 700 struct survey_info *cur_survey; 701 struct survey_info survey[ATH9K_NUM_CHANNELS]; 702 703 struct tasklet_struct intr_tq; 704 struct tasklet_struct bcon_tasklet; 705 struct ath_hw *sc_ah; 706 void __iomem *mem; 707 int irq; 708 spinlock_t sc_serial_rw; 709 spinlock_t sc_pm_lock; 710 spinlock_t sc_pcu_lock; 711 struct mutex mutex; 712 struct work_struct paprd_work; 713 struct work_struct hw_reset_work; 714 struct completion paprd_complete; 715 wait_queue_head_t tx_wait; 716 717 unsigned long driver_data; 718 719 u8 gtt_cnt; 720 u32 intrstatus; 721 u16 ps_flags; /* PS_* */ 722 u16 curtxpow; 723 bool ps_enabled; 724 bool ps_idle; 725 short nbcnvifs; 726 short nvifs; 727 unsigned long ps_usecount; 728 729 struct ath_config config; 730 struct ath_rx rx; 731 struct ath_tx tx; 732 struct ath_beacon beacon; 733 734 #ifdef CONFIG_MAC80211_LEDS 735 bool led_registered; 736 char led_name[32]; 737 struct led_classdev led_cdev; 738 #endif 739 740 struct ath9k_hw_cal_data caldata; 741 742 #ifdef CONFIG_ATH9K_DEBUGFS 743 struct ath9k_debug debug; 744 #endif 745 struct ath_beacon_config cur_beacon_conf; 746 struct delayed_work tx_complete_work; 747 struct delayed_work hw_pll_work; 748 struct timer_list sleep_timer; 749 750 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 751 struct ath_btcoex btcoex; 752 struct ath_mci_coex mci_coex; 753 struct work_struct mci_work; 754 #endif 755 756 struct ath_descdma txsdma; 757 758 struct ath_ant_comb ant_comb; 759 u8 ant_tx, ant_rx; 760 struct dfs_pattern_detector *dfs_detector; 761 u32 wow_enabled; 762 /* relay(fs) channel for spectral scan */ 763 struct rchan *rfs_chan_spec_scan; 764 enum spectral_mode spectral_mode; 765 struct ath_spec_scan spec_config; 766 767 struct ieee80211_vif *tx99_vif; 768 struct sk_buff *tx99_skb; 769 bool tx99_state; 770 s16 tx99_power; 771 772 #ifdef CONFIG_ATH9K_WOW 773 atomic_t wow_got_bmiss_intr; 774 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 775 u32 wow_intr_before_sleep; 776 #endif 777 }; 778 779 /********/ 780 /* TX99 */ 781 /********/ 782 783 #ifdef CONFIG_ATH9K_TX99 784 void ath9k_tx99_init_debug(struct ath_softc *sc); 785 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 786 struct ath_tx_control *txctl); 787 #else 788 static inline void ath9k_tx99_init_debug(struct ath_softc *sc) 789 { 790 } 791 static inline int ath9k_tx99_send(struct ath_softc *sc, 792 struct sk_buff *skb, 793 struct ath_tx_control *txctl) 794 { 795 return 0; 796 } 797 #endif /* CONFIG_ATH9K_TX99 */ 798 799 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 800 { 801 common->bus_ops->read_cachesize(common, csz); 802 } 803 804 void ath9k_tasklet(unsigned long data); 805 int ath_cabq_update(struct ath_softc *); 806 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 807 irqreturn_t ath_isr(int irq, void *dev); 808 int ath_reset(struct ath_softc *sc); 809 void ath_cancel_work(struct ath_softc *sc); 810 void ath_restart_work(struct ath_softc *sc); 811 int ath9k_init_device(u16 devid, struct ath_softc *sc, 812 const struct ath_bus_ops *bus_ops); 813 void ath9k_deinit_device(struct ath_softc *sc); 814 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 815 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 816 void ath_start_rfkill_poll(struct ath_softc *sc); 817 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 818 void ath9k_ps_wakeup(struct ath_softc *sc); 819 void ath9k_ps_restore(struct ath_softc *sc); 820 821 #ifdef CONFIG_ATH9K_PCI 822 int ath_pci_init(void); 823 void ath_pci_exit(void); 824 #else 825 static inline int ath_pci_init(void) { return 0; }; 826 static inline void ath_pci_exit(void) {}; 827 #endif 828 829 #ifdef CONFIG_ATH9K_AHB 830 int ath_ahb_init(void); 831 void ath_ahb_exit(void); 832 #else 833 static inline int ath_ahb_init(void) { return 0; }; 834 static inline void ath_ahb_exit(void) {}; 835 #endif 836 837 #endif /* ATH9K_H */ 838