1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 struct ath_buf *dd_bufptr; 113 }; 114 115 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 116 struct list_head *head, const char *name, 117 int nbuf, int ndesc, bool is_tx); 118 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 119 struct list_head *head); 120 121 /***********/ 122 /* RX / TX */ 123 /***********/ 124 125 #define ATH_RXBUF 512 126 #define ATH_TXBUF 512 127 #define ATH_TXBUF_RESERVE 5 128 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 129 #define ATH_TXMAXTRY 13 130 131 #define TID_TO_WME_AC(_tid) \ 132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 135 WME_AC_VO) 136 137 #define ATH_AGGR_DELIM_SZ 4 138 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 139 /* number of delimiters for encryption padding */ 140 #define ATH_AGGR_ENCRYPTDELIM 10 141 /* minimum h/w qdepth to be sustained to maximize aggregation */ 142 #define ATH_AGGR_MIN_QDEPTH 2 143 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 144 145 #define IEEE80211_SEQ_SEQ_SHIFT 4 146 #define IEEE80211_SEQ_MAX 4096 147 #define IEEE80211_WEP_IVLEN 3 148 #define IEEE80211_WEP_KIDLEN 1 149 #define IEEE80211_WEP_CRCLEN 4 150 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 151 (IEEE80211_WEP_IVLEN + \ 152 IEEE80211_WEP_KIDLEN + \ 153 IEEE80211_WEP_CRCLEN)) 154 155 /* return whether a bit at index _n in bitmap _bm is set 156 * _sz is the size of the bitmap */ 157 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 159 160 /* return block-ack bitmap index given sequence and starting sequence */ 161 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 162 163 /* return the seqno for _start + _offset */ 164 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 165 166 /* returns delimiter padding required given the packet length */ 167 #define ATH_AGGR_GET_NDELIM(_len) \ 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 170 171 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 172 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 173 174 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 175 176 #define ATH_TX_COMPLETE_POLL_INT 1000 177 178 enum ATH_AGGR_STATUS { 179 ATH_AGGR_DONE, 180 ATH_AGGR_BAW_CLOSED, 181 ATH_AGGR_LIMITED, 182 }; 183 184 #define ATH_TXFIFO_DEPTH 8 185 struct ath_txq { 186 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 187 u32 axq_qnum; /* ath9k hardware queue number */ 188 void *axq_link; 189 struct list_head axq_q; 190 spinlock_t axq_lock; 191 u32 axq_depth; 192 u32 axq_ampdu_depth; 193 bool stopped; 194 bool axq_tx_inprogress; 195 struct list_head axq_acq; 196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 197 u8 txq_headidx; 198 u8 txq_tailidx; 199 int pending_frames; 200 struct sk_buff_head complete_q; 201 }; 202 203 struct ath_atx_ac { 204 struct ath_txq *txq; 205 int sched; 206 struct list_head list; 207 struct list_head tid_q; 208 bool clear_ps_filter; 209 }; 210 211 struct ath_frame_info { 212 struct ath_buf *bf; 213 int framelen; 214 enum ath9k_key_type keytype; 215 u8 keyix; 216 u8 retries; 217 u8 rtscts_rate; 218 }; 219 220 struct ath_buf_state { 221 u8 bf_type; 222 u8 bfs_paprd; 223 u8 ndelim; 224 u16 seqno; 225 unsigned long bfs_paprd_timestamp; 226 }; 227 228 struct ath_buf { 229 struct list_head list; 230 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 231 an aggregate) */ 232 struct ath_buf *bf_next; /* next subframe in the aggregate */ 233 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 234 void *bf_desc; /* virtual addr of desc */ 235 dma_addr_t bf_daddr; /* physical addr of desc */ 236 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 237 bool bf_stale; 238 struct ath_buf_state bf_state; 239 }; 240 241 struct ath_atx_tid { 242 struct list_head list; 243 struct sk_buff_head buf_q; 244 struct ath_node *an; 245 struct ath_atx_ac *ac; 246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 247 int bar_index; 248 u16 seq_start; 249 u16 seq_next; 250 u16 baw_size; 251 int tidno; 252 int baw_head; /* first un-acked tx buffer */ 253 int baw_tail; /* next unused tx buffer slot */ 254 int sched; 255 int paused; 256 u8 state; 257 }; 258 259 struct ath_node { 260 #ifdef CONFIG_ATH9K_DEBUGFS 261 struct list_head list; /* for sc->nodes */ 262 #endif 263 struct ieee80211_sta *sta; /* station struct we're part of */ 264 struct ieee80211_vif *vif; /* interface with which we're associated */ 265 struct ath_atx_tid tid[WME_NUM_TID]; 266 struct ath_atx_ac ac[WME_NUM_AC]; 267 int ps_key; 268 269 u16 maxampdu; 270 u8 mpdudensity; 271 272 bool sleeping; 273 }; 274 275 #define AGGR_CLEANUP BIT(1) 276 #define AGGR_ADDBA_COMPLETE BIT(2) 277 #define AGGR_ADDBA_PROGRESS BIT(3) 278 279 struct ath_tx_control { 280 struct ath_txq *txq; 281 struct ath_node *an; 282 u8 paprd; 283 }; 284 285 #define ATH_TX_ERROR 0x01 286 287 /** 288 * @txq_map: Index is mac80211 queue number. This is 289 * not necessarily the same as the hardware queue number 290 * (axq_qnum). 291 */ 292 struct ath_tx { 293 u16 seq_no; 294 u32 txqsetup; 295 spinlock_t txbuflock; 296 struct list_head txbuf; 297 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 298 struct ath_descdma txdma; 299 struct ath_txq *txq_map[WME_NUM_AC]; 300 u32 txq_max_pending[WME_NUM_AC]; 301 u16 max_aggr_framelen[WME_NUM_AC][4][32]; 302 }; 303 304 struct ath_rx_edma { 305 struct sk_buff_head rx_fifo; 306 u32 rx_fifo_hwsize; 307 }; 308 309 struct ath_rx { 310 u8 defant; 311 u8 rxotherant; 312 u32 *rxlink; 313 u32 num_pkts; 314 unsigned int rxfilter; 315 spinlock_t rxbuflock; 316 struct list_head rxbuf; 317 struct ath_descdma rxdma; 318 struct ath_buf *rx_bufptr; 319 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 320 321 struct sk_buff *frag; 322 }; 323 324 int ath_startrecv(struct ath_softc *sc); 325 bool ath_stoprecv(struct ath_softc *sc); 326 void ath_flushrecv(struct ath_softc *sc); 327 u32 ath_calcrxfilter(struct ath_softc *sc); 328 int ath_rx_init(struct ath_softc *sc, int nbufs); 329 void ath_rx_cleanup(struct ath_softc *sc); 330 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 331 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 332 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 333 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 334 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 335 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 336 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 337 void ath_draintxq(struct ath_softc *sc, 338 struct ath_txq *txq, bool retry_tx); 339 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 340 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 341 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 342 int ath_tx_init(struct ath_softc *sc, int nbufs); 343 void ath_tx_cleanup(struct ath_softc *sc); 344 int ath_txq_update(struct ath_softc *sc, int qnum, 345 struct ath9k_tx_queue_info *q); 346 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 347 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 348 struct ath_tx_control *txctl); 349 void ath_tx_tasklet(struct ath_softc *sc); 350 void ath_tx_edma_tasklet(struct ath_softc *sc); 351 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 352 u16 tid, u16 *ssn); 353 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 354 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 355 356 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 357 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 358 struct ath_node *an); 359 360 /********/ 361 /* VIFs */ 362 /********/ 363 364 struct ath_vif { 365 int av_bslot; 366 bool primary_sta_vif; 367 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 368 struct ath_buf *av_bcbuf; 369 }; 370 371 /*******************/ 372 /* Beacon Handling */ 373 /*******************/ 374 375 /* 376 * Regardless of the number of beacons we stagger, (i.e. regardless of the 377 * number of BSSIDs) if a given beacon does not go out even after waiting this 378 * number of beacon intervals, the game's up. 379 */ 380 #define BSTUCK_THRESH 9 381 #define ATH_BCBUF 8 382 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 383 #define ATH_DEFAULT_BMISS_LIMIT 10 384 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 385 386 struct ath_beacon_config { 387 int beacon_interval; 388 u16 listen_interval; 389 u16 dtim_period; 390 u16 bmiss_timeout; 391 u8 dtim_count; 392 bool enable_beacon; 393 }; 394 395 struct ath_beacon { 396 enum { 397 OK, /* no change needed */ 398 UPDATE, /* update pending */ 399 COMMIT /* beacon sent, commit change */ 400 } updateslot; /* slot time update fsm */ 401 402 u32 beaconq; 403 u32 bmisscnt; 404 u32 bc_tstamp; 405 struct ieee80211_vif *bslot[ATH_BCBUF]; 406 int slottime; 407 int slotupdate; 408 struct ath9k_tx_queue_info beacon_qi; 409 struct ath_descdma bdma; 410 struct ath_txq *cabq; 411 struct list_head bbuf; 412 413 bool tx_processed; 414 bool tx_last; 415 }; 416 417 void ath9k_beacon_tasklet(unsigned long data); 418 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 419 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 420 u32 changed); 421 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 422 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 423 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 424 void ath9k_set_beacon(struct ath_softc *sc); 425 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); 426 427 /*******************/ 428 /* Link Monitoring */ 429 /*******************/ 430 431 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 432 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 433 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 434 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 435 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 436 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 437 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 438 439 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 440 #define ATH_PLL_WORK_INTERVAL 100 441 442 void ath_tx_complete_poll_work(struct work_struct *work); 443 void ath_reset_work(struct work_struct *work); 444 void ath_hw_check(struct work_struct *work); 445 void ath_hw_pll_work(struct work_struct *work); 446 void ath_rx_poll(unsigned long data); 447 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 448 void ath_paprd_calibrate(struct work_struct *work); 449 void ath_ani_calibrate(unsigned long data); 450 void ath_start_ani(struct ath_softc *sc); 451 void ath_stop_ani(struct ath_softc *sc); 452 void ath_check_ani(struct ath_softc *sc); 453 int ath_update_survey_stats(struct ath_softc *sc); 454 void ath_update_survey_nf(struct ath_softc *sc, int channel); 455 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 456 457 /**********/ 458 /* BTCOEX */ 459 /**********/ 460 461 enum bt_op_flags { 462 BT_OP_PRIORITY_DETECTED, 463 BT_OP_SCAN, 464 }; 465 466 struct ath_btcoex { 467 bool hw_timer_enabled; 468 spinlock_t btcoex_lock; 469 struct timer_list period_timer; /* Timer for BT period */ 470 u32 bt_priority_cnt; 471 unsigned long bt_priority_time; 472 unsigned long op_flags; 473 int bt_stomp_type; /* Types of BT stomping */ 474 u32 btcoex_no_stomp; /* in usec */ 475 u32 btcoex_period; /* in usec */ 476 u32 btscan_no_stomp; /* in usec */ 477 u32 duty_cycle; 478 u32 bt_wait_time; 479 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 480 struct ath_mci_profile mci; 481 }; 482 483 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 484 int ath9k_init_btcoex(struct ath_softc *sc); 485 void ath9k_deinit_btcoex(struct ath_softc *sc); 486 void ath9k_start_btcoex(struct ath_softc *sc); 487 void ath9k_stop_btcoex(struct ath_softc *sc); 488 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 489 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 490 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 491 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 492 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 493 #else 494 static inline int ath9k_init_btcoex(struct ath_softc *sc) 495 { 496 return 0; 497 } 498 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 499 { 500 } 501 static inline void ath9k_start_btcoex(struct ath_softc *sc) 502 { 503 } 504 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 505 { 506 } 507 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 508 u32 status) 509 { 510 } 511 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 512 u32 max_4ms_framelen) 513 { 514 return 0; 515 } 516 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 517 { 518 } 519 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 520 521 struct ath9k_wow_pattern { 522 u8 pattern_bytes[MAX_PATTERN_SIZE]; 523 u8 mask_bytes[MAX_PATTERN_SIZE]; 524 u32 pattern_len; 525 }; 526 527 /********************/ 528 /* LED Control */ 529 /********************/ 530 531 #define ATH_LED_PIN_DEF 1 532 #define ATH_LED_PIN_9287 8 533 #define ATH_LED_PIN_9300 10 534 #define ATH_LED_PIN_9485 6 535 #define ATH_LED_PIN_9462 4 536 537 #ifdef CONFIG_MAC80211_LEDS 538 void ath_init_leds(struct ath_softc *sc); 539 void ath_deinit_leds(struct ath_softc *sc); 540 #else 541 static inline void ath_init_leds(struct ath_softc *sc) 542 { 543 } 544 545 static inline void ath_deinit_leds(struct ath_softc *sc) 546 { 547 } 548 #endif 549 550 /*******************************/ 551 /* Antenna diversity/combining */ 552 /*******************************/ 553 554 #define ATH_ANT_RX_CURRENT_SHIFT 4 555 #define ATH_ANT_RX_MAIN_SHIFT 2 556 #define ATH_ANT_RX_MASK 0x3 557 558 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 559 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 560 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 561 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 562 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 563 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 564 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 565 566 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 567 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 568 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 569 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 570 571 enum ath9k_ant_div_comb_lna_conf { 572 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 573 ATH_ANT_DIV_COMB_LNA2, 574 ATH_ANT_DIV_COMB_LNA1, 575 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 576 }; 577 578 struct ath_ant_comb { 579 u16 count; 580 u16 total_pkt_count; 581 bool scan; 582 bool scan_not_start; 583 int main_total_rssi; 584 int alt_total_rssi; 585 int alt_recv_cnt; 586 int main_recv_cnt; 587 int rssi_lna1; 588 int rssi_lna2; 589 int rssi_add; 590 int rssi_sub; 591 int rssi_first; 592 int rssi_second; 593 int rssi_third; 594 bool alt_good; 595 int quick_scan_cnt; 596 int main_conf; 597 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 598 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 599 int first_bias; 600 int second_bias; 601 bool first_ratio; 602 bool second_ratio; 603 unsigned long scan_start_time; 604 }; 605 606 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 607 void ath_ant_comb_update(struct ath_softc *sc); 608 609 /********************/ 610 /* Main driver core */ 611 /********************/ 612 613 /* 614 * Default cache line size, in bytes. 615 * Used when PCI device not fully initialized by bootrom/BIOS 616 */ 617 #define DEFAULT_CACHELINE 32 618 #define ATH_REGCLASSIDS_MAX 10 619 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 620 #define ATH_MAX_SW_RETRIES 30 621 #define ATH_CHAN_MAX 255 622 623 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 624 #define ATH_RATE_DUMMY_MARKER 0 625 626 enum sc_op_flags { 627 SC_OP_INVALID, 628 SC_OP_BEACONS, 629 SC_OP_RXFLUSH, 630 SC_OP_ANI_RUN, 631 SC_OP_PRIM_STA_VIF, 632 SC_OP_HW_RESET, 633 }; 634 635 /* Powersave flags */ 636 #define PS_WAIT_FOR_BEACON BIT(0) 637 #define PS_WAIT_FOR_CAB BIT(1) 638 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 639 #define PS_WAIT_FOR_TX_ACK BIT(3) 640 #define PS_BEACON_SYNC BIT(4) 641 642 struct ath_rate_table; 643 644 struct ath9k_vif_iter_data { 645 const u8 *hw_macaddr; /* phy's hardware address, set 646 * before starting iteration for 647 * valid bssid mask. 648 */ 649 u8 mask[ETH_ALEN]; /* bssid mask */ 650 int naps; /* number of AP vifs */ 651 int nmeshes; /* number of mesh vifs */ 652 int nstations; /* number of station vifs */ 653 int nwds; /* number of WDS vifs */ 654 int nadhocs; /* number of adhoc vifs */ 655 }; 656 657 struct ath_softc { 658 struct ieee80211_hw *hw; 659 struct device *dev; 660 661 struct survey_info *cur_survey; 662 struct survey_info survey[ATH9K_NUM_CHANNELS]; 663 664 struct tasklet_struct intr_tq; 665 struct tasklet_struct bcon_tasklet; 666 struct ath_hw *sc_ah; 667 void __iomem *mem; 668 int irq; 669 spinlock_t sc_serial_rw; 670 spinlock_t sc_pm_lock; 671 spinlock_t sc_pcu_lock; 672 struct mutex mutex; 673 struct work_struct paprd_work; 674 struct work_struct hw_check_work; 675 struct work_struct hw_reset_work; 676 struct completion paprd_complete; 677 678 unsigned int hw_busy_count; 679 unsigned long sc_flags; 680 681 u32 intrstatus; 682 u16 ps_flags; /* PS_* */ 683 u16 curtxpow; 684 bool ps_enabled; 685 bool ps_idle; 686 short nbcnvifs; 687 short nvifs; 688 unsigned long ps_usecount; 689 690 struct ath_config config; 691 struct ath_rx rx; 692 struct ath_tx tx; 693 struct ath_beacon beacon; 694 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 695 696 #ifdef CONFIG_MAC80211_LEDS 697 bool led_registered; 698 char led_name[32]; 699 struct led_classdev led_cdev; 700 #endif 701 702 struct ath9k_hw_cal_data caldata; 703 int last_rssi; 704 705 #ifdef CONFIG_ATH9K_DEBUGFS 706 struct ath9k_debug debug; 707 spinlock_t nodes_lock; 708 struct list_head nodes; /* basically, stations */ 709 unsigned int tx_complete_poll_work_seen; 710 #endif 711 struct ath_beacon_config cur_beacon_conf; 712 struct delayed_work tx_complete_work; 713 struct delayed_work hw_pll_work; 714 struct timer_list rx_poll_timer; 715 716 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 717 struct ath_btcoex btcoex; 718 struct ath_mci_coex mci_coex; 719 struct work_struct mci_work; 720 #endif 721 722 struct ath_descdma txsdma; 723 724 struct ath_ant_comb ant_comb; 725 u8 ant_tx, ant_rx; 726 struct dfs_pattern_detector *dfs_detector; 727 u32 wow_enabled; 728 729 #ifdef CONFIG_PM_SLEEP 730 atomic_t wow_got_bmiss_intr; 731 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 732 u32 wow_intr_before_sleep; 733 #endif 734 }; 735 736 void ath9k_tasklet(unsigned long data); 737 int ath_cabq_update(struct ath_softc *); 738 739 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 740 { 741 common->bus_ops->read_cachesize(common, csz); 742 } 743 744 extern struct ieee80211_ops ath9k_ops; 745 extern int ath9k_modparam_nohwcrypt; 746 extern int led_blink; 747 extern bool is_ath9k_unloaded; 748 749 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 750 irqreturn_t ath_isr(int irq, void *dev); 751 int ath9k_init_device(u16 devid, struct ath_softc *sc, 752 const struct ath_bus_ops *bus_ops); 753 void ath9k_deinit_device(struct ath_softc *sc); 754 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 755 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 756 757 bool ath9k_uses_beacons(int type); 758 759 #ifdef CONFIG_ATH9K_PCI 760 int ath_pci_init(void); 761 void ath_pci_exit(void); 762 #else 763 static inline int ath_pci_init(void) { return 0; }; 764 static inline void ath_pci_exit(void) {}; 765 #endif 766 767 #ifdef CONFIG_ATH9K_AHB 768 int ath_ahb_init(void); 769 void ath_ahb_exit(void); 770 #else 771 static inline int ath_ahb_init(void) { return 0; }; 772 static inline void ath_ahb_exit(void) {}; 773 #endif 774 775 void ath9k_ps_wakeup(struct ath_softc *sc); 776 void ath9k_ps_restore(struct ath_softc *sc); 777 778 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 779 780 void ath_start_rfkill_poll(struct ath_softc *sc); 781 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 782 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 783 struct ieee80211_vif *vif, 784 struct ath9k_vif_iter_data *iter_data); 785 786 #endif /* ATH9K_H */ 787