1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 }; 113 114 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 115 struct list_head *head, const char *name, 116 int nbuf, int ndesc, bool is_tx); 117 118 /***********/ 119 /* RX / TX */ 120 /***********/ 121 122 #define ATH_RXBUF 512 123 #define ATH_TXBUF 512 124 #define ATH_TXBUF_RESERVE 5 125 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 126 #define ATH_TXMAXTRY 13 127 128 #define TID_TO_WME_AC(_tid) \ 129 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ 130 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ 131 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ 132 IEEE80211_AC_VO) 133 134 #define ATH_AGGR_DELIM_SZ 4 135 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 136 /* number of delimiters for encryption padding */ 137 #define ATH_AGGR_ENCRYPTDELIM 10 138 /* minimum h/w qdepth to be sustained to maximize aggregation */ 139 #define ATH_AGGR_MIN_QDEPTH 2 140 141 #define IEEE80211_SEQ_SEQ_SHIFT 4 142 #define IEEE80211_SEQ_MAX 4096 143 #define IEEE80211_WEP_IVLEN 3 144 #define IEEE80211_WEP_KIDLEN 1 145 #define IEEE80211_WEP_CRCLEN 4 146 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 147 (IEEE80211_WEP_IVLEN + \ 148 IEEE80211_WEP_KIDLEN + \ 149 IEEE80211_WEP_CRCLEN)) 150 151 /* return whether a bit at index _n in bitmap _bm is set 152 * _sz is the size of the bitmap */ 153 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 154 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 155 156 /* return block-ack bitmap index given sequence and starting sequence */ 157 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 158 159 /* return the seqno for _start + _offset */ 160 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 161 162 /* returns delimiter padding required given the packet length */ 163 #define ATH_AGGR_GET_NDELIM(_len) \ 164 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 165 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 166 167 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 168 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 169 170 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 171 172 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 173 174 #define ATH_TX_COMPLETE_POLL_INT 1000 175 176 enum ATH_AGGR_STATUS { 177 ATH_AGGR_DONE, 178 ATH_AGGR_BAW_CLOSED, 179 ATH_AGGR_LIMITED, 180 }; 181 182 #define ATH_TXFIFO_DEPTH 8 183 struct ath_txq { 184 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 185 u32 axq_qnum; /* ath9k hardware queue number */ 186 void *axq_link; 187 struct list_head axq_q; 188 spinlock_t axq_lock; 189 u32 axq_depth; 190 u32 axq_ampdu_depth; 191 bool stopped; 192 bool axq_tx_inprogress; 193 struct list_head axq_acq; 194 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 195 u8 txq_headidx; 196 u8 txq_tailidx; 197 int pending_frames; 198 struct sk_buff_head complete_q; 199 }; 200 201 struct ath_atx_ac { 202 struct ath_txq *txq; 203 int sched; 204 struct list_head list; 205 struct list_head tid_q; 206 bool clear_ps_filter; 207 }; 208 209 struct ath_frame_info { 210 struct ath_buf *bf; 211 int framelen; 212 enum ath9k_key_type keytype; 213 u8 keyix; 214 u8 rtscts_rate; 215 u8 retries : 7; 216 u8 baw_tracked : 1; 217 }; 218 219 struct ath_buf_state { 220 u8 bf_type; 221 u8 bfs_paprd; 222 u8 ndelim; 223 u16 seqno; 224 unsigned long bfs_paprd_timestamp; 225 }; 226 227 struct ath_buf { 228 struct list_head list; 229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 230 an aggregate) */ 231 struct ath_buf *bf_next; /* next subframe in the aggregate */ 232 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 233 void *bf_desc; /* virtual addr of desc */ 234 dma_addr_t bf_daddr; /* physical addr of desc */ 235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 236 bool bf_stale; 237 struct ieee80211_tx_rate rates[4]; 238 struct ath_buf_state bf_state; 239 }; 240 241 struct ath_atx_tid { 242 struct list_head list; 243 struct sk_buff_head buf_q; 244 struct sk_buff_head retry_q; 245 struct ath_node *an; 246 struct ath_atx_ac *ac; 247 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 248 int bar_index; 249 u16 seq_start; 250 u16 seq_next; 251 u16 baw_size; 252 int tidno; 253 int baw_head; /* first un-acked tx buffer */ 254 int baw_tail; /* next unused tx buffer slot */ 255 bool sched; 256 bool paused; 257 bool active; 258 }; 259 260 struct ath_node { 261 struct ath_softc *sc; 262 struct ieee80211_sta *sta; /* station struct we're part of */ 263 struct ieee80211_vif *vif; /* interface with which we're associated */ 264 struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; 265 struct ath_atx_ac ac[IEEE80211_NUM_ACS]; 266 int ps_key; 267 268 u16 maxampdu; 269 u8 mpdudensity; 270 271 bool sleeping; 272 273 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 274 struct dentry *node_stat; 275 #endif 276 }; 277 278 struct ath_tx_control { 279 struct ath_txq *txq; 280 struct ath_node *an; 281 u8 paprd; 282 struct ieee80211_sta *sta; 283 }; 284 285 #define ATH_TX_ERROR 0x01 286 287 /** 288 * @txq_map: Index is mac80211 queue number. This is 289 * not necessarily the same as the hardware queue number 290 * (axq_qnum). 291 */ 292 struct ath_tx { 293 u16 seq_no; 294 u32 txqsetup; 295 spinlock_t txbuflock; 296 struct list_head txbuf; 297 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 298 struct ath_descdma txdma; 299 struct ath_txq *txq_map[IEEE80211_NUM_ACS]; 300 struct ath_txq *uapsdq; 301 u32 txq_max_pending[IEEE80211_NUM_ACS]; 302 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; 303 }; 304 305 struct ath_rx_edma { 306 struct sk_buff_head rx_fifo; 307 u32 rx_fifo_hwsize; 308 }; 309 310 struct ath_rx { 311 u8 defant; 312 u8 rxotherant; 313 bool discard_next; 314 u32 *rxlink; 315 u32 num_pkts; 316 unsigned int rxfilter; 317 struct list_head rxbuf; 318 struct ath_descdma rxdma; 319 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 320 321 struct sk_buff *frag; 322 323 u32 ampdu_ref; 324 }; 325 326 int ath_startrecv(struct ath_softc *sc); 327 bool ath_stoprecv(struct ath_softc *sc); 328 u32 ath_calcrxfilter(struct ath_softc *sc); 329 int ath_rx_init(struct ath_softc *sc, int nbufs); 330 void ath_rx_cleanup(struct ath_softc *sc); 331 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 332 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 333 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 334 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 335 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 336 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 337 bool ath_drain_all_txq(struct ath_softc *sc); 338 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); 339 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 340 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 341 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 342 int ath_tx_init(struct ath_softc *sc, int nbufs); 343 int ath_txq_update(struct ath_softc *sc, int qnum, 344 struct ath9k_tx_queue_info *q); 345 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 346 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 347 struct ath_tx_control *txctl); 348 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 349 struct sk_buff *skb); 350 void ath_tx_tasklet(struct ath_softc *sc); 351 void ath_tx_edma_tasklet(struct ath_softc *sc); 352 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 353 u16 tid, u16 *ssn); 354 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 355 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 356 357 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 358 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 359 struct ath_node *an); 360 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 361 struct ieee80211_sta *sta, 362 u16 tids, int nframes, 363 enum ieee80211_frame_release_type reason, 364 bool more_data); 365 366 /********/ 367 /* VIFs */ 368 /********/ 369 370 struct ath_vif { 371 int av_bslot; 372 bool primary_sta_vif; 373 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 374 struct ath_buf *av_bcbuf; 375 }; 376 377 /*******************/ 378 /* Beacon Handling */ 379 /*******************/ 380 381 /* 382 * Regardless of the number of beacons we stagger, (i.e. regardless of the 383 * number of BSSIDs) if a given beacon does not go out even after waiting this 384 * number of beacon intervals, the game's up. 385 */ 386 #define BSTUCK_THRESH 9 387 #define ATH_BCBUF 8 388 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 389 #define ATH_DEFAULT_BMISS_LIMIT 10 390 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 391 392 struct ath_beacon_config { 393 int beacon_interval; 394 u16 listen_interval; 395 u16 dtim_period; 396 u16 bmiss_timeout; 397 u8 dtim_count; 398 bool enable_beacon; 399 bool ibss_creator; 400 }; 401 402 struct ath_beacon { 403 enum { 404 OK, /* no change needed */ 405 UPDATE, /* update pending */ 406 COMMIT /* beacon sent, commit change */ 407 } updateslot; /* slot time update fsm */ 408 409 u32 beaconq; 410 u32 bmisscnt; 411 u32 bc_tstamp; 412 struct ieee80211_vif *bslot[ATH_BCBUF]; 413 int slottime; 414 int slotupdate; 415 struct ath9k_tx_queue_info beacon_qi; 416 struct ath_descdma bdma; 417 struct ath_txq *cabq; 418 struct list_head bbuf; 419 420 bool tx_processed; 421 bool tx_last; 422 }; 423 424 void ath9k_beacon_tasklet(unsigned long data); 425 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 426 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 427 u32 changed); 428 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 429 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 430 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 431 void ath9k_set_beacon(struct ath_softc *sc); 432 433 /*******************/ 434 /* Link Monitoring */ 435 /*******************/ 436 437 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 438 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 439 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 440 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 441 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 442 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 443 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 444 #define ATH_ANI_MAX_SKIP_COUNT 10 445 446 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 447 #define ATH_PLL_WORK_INTERVAL 100 448 449 void ath_tx_complete_poll_work(struct work_struct *work); 450 void ath_reset_work(struct work_struct *work); 451 void ath_hw_check(struct work_struct *work); 452 void ath_hw_pll_work(struct work_struct *work); 453 void ath_rx_poll(unsigned long data); 454 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 455 void ath_paprd_calibrate(struct work_struct *work); 456 void ath_ani_calibrate(unsigned long data); 457 void ath_start_ani(struct ath_softc *sc); 458 void ath_stop_ani(struct ath_softc *sc); 459 void ath_check_ani(struct ath_softc *sc); 460 int ath_update_survey_stats(struct ath_softc *sc); 461 void ath_update_survey_nf(struct ath_softc *sc, int channel); 462 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 463 464 /**********/ 465 /* BTCOEX */ 466 /**********/ 467 468 #define ATH_DUMP_BTCOEX(_s, _val) \ 469 do { \ 470 len += snprintf(buf + len, size - len, \ 471 "%20s : %10d\n", _s, (_val)); \ 472 } while (0) 473 474 enum bt_op_flags { 475 BT_OP_PRIORITY_DETECTED, 476 BT_OP_SCAN, 477 }; 478 479 struct ath_btcoex { 480 bool hw_timer_enabled; 481 spinlock_t btcoex_lock; 482 struct timer_list period_timer; /* Timer for BT period */ 483 u32 bt_priority_cnt; 484 unsigned long bt_priority_time; 485 unsigned long op_flags; 486 int bt_stomp_type; /* Types of BT stomping */ 487 u32 btcoex_no_stomp; /* in usec */ 488 u32 btcoex_period; /* in msec */ 489 u32 btscan_no_stomp; /* in usec */ 490 u32 duty_cycle; 491 u32 bt_wait_time; 492 int rssi_count; 493 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 494 struct ath_mci_profile mci; 495 u8 stomp_audio; 496 }; 497 498 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 499 int ath9k_init_btcoex(struct ath_softc *sc); 500 void ath9k_deinit_btcoex(struct ath_softc *sc); 501 void ath9k_start_btcoex(struct ath_softc *sc); 502 void ath9k_stop_btcoex(struct ath_softc *sc); 503 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 504 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 505 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 506 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 507 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 508 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); 509 #else 510 static inline int ath9k_init_btcoex(struct ath_softc *sc) 511 { 512 return 0; 513 } 514 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 515 { 516 } 517 static inline void ath9k_start_btcoex(struct ath_softc *sc) 518 { 519 } 520 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 521 { 522 } 523 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 524 u32 status) 525 { 526 } 527 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 528 u32 max_4ms_framelen) 529 { 530 return 0; 531 } 532 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 533 { 534 } 535 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) 536 { 537 return 0; 538 } 539 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 540 541 struct ath9k_wow_pattern { 542 u8 pattern_bytes[MAX_PATTERN_SIZE]; 543 u8 mask_bytes[MAX_PATTERN_SIZE]; 544 u32 pattern_len; 545 }; 546 547 /********************/ 548 /* LED Control */ 549 /********************/ 550 551 #define ATH_LED_PIN_DEF 1 552 #define ATH_LED_PIN_9287 8 553 #define ATH_LED_PIN_9300 10 554 #define ATH_LED_PIN_9485 6 555 #define ATH_LED_PIN_9462 4 556 557 #ifdef CONFIG_MAC80211_LEDS 558 void ath_init_leds(struct ath_softc *sc); 559 void ath_deinit_leds(struct ath_softc *sc); 560 void ath_fill_led_pin(struct ath_softc *sc); 561 #else 562 static inline void ath_init_leds(struct ath_softc *sc) 563 { 564 } 565 566 static inline void ath_deinit_leds(struct ath_softc *sc) 567 { 568 } 569 static inline void ath_fill_led_pin(struct ath_softc *sc) 570 { 571 } 572 #endif 573 574 /*******************************/ 575 /* Antenna diversity/combining */ 576 /*******************************/ 577 578 #define ATH_ANT_RX_CURRENT_SHIFT 4 579 #define ATH_ANT_RX_MAIN_SHIFT 2 580 #define ATH_ANT_RX_MASK 0x3 581 582 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 583 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 584 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 585 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 586 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 587 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 588 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 589 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 590 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 591 592 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 593 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 594 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 595 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 596 597 struct ath_ant_comb { 598 u16 count; 599 u16 total_pkt_count; 600 bool scan; 601 bool scan_not_start; 602 int main_total_rssi; 603 int alt_total_rssi; 604 int alt_recv_cnt; 605 int main_recv_cnt; 606 int rssi_lna1; 607 int rssi_lna2; 608 int rssi_add; 609 int rssi_sub; 610 int rssi_first; 611 int rssi_second; 612 int rssi_third; 613 int ant_ratio; 614 int ant_ratio2; 615 bool alt_good; 616 int quick_scan_cnt; 617 enum ath9k_ant_div_comb_lna_conf main_conf; 618 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 619 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 620 bool first_ratio; 621 bool second_ratio; 622 unsigned long scan_start_time; 623 624 /* 625 * Card-specific config values. 626 */ 627 int low_rssi_thresh; 628 int fast_div_bias; 629 }; 630 631 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 632 633 /********************/ 634 /* Main driver core */ 635 /********************/ 636 637 #define ATH9K_PCI_CUS198 0x0001 638 #define ATH9K_PCI_CUS230 0x0002 639 #define ATH9K_PCI_CUS217 0x0004 640 #define ATH9K_PCI_WOW 0x0008 641 #define ATH9K_PCI_BT_ANT_DIV 0x0010 642 643 /* 644 * Default cache line size, in bytes. 645 * Used when PCI device not fully initialized by bootrom/BIOS 646 */ 647 #define DEFAULT_CACHELINE 32 648 #define ATH_REGCLASSIDS_MAX 10 649 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 650 #define ATH_MAX_SW_RETRIES 30 651 #define ATH_CHAN_MAX 255 652 653 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 654 #define ATH_RATE_DUMMY_MARKER 0 655 656 enum sc_op_flags { 657 SC_OP_INVALID, 658 SC_OP_BEACONS, 659 SC_OP_ANI_RUN, 660 SC_OP_PRIM_STA_VIF, 661 SC_OP_HW_RESET, 662 SC_OP_SCANNING, 663 }; 664 665 /* Powersave flags */ 666 #define PS_WAIT_FOR_BEACON BIT(0) 667 #define PS_WAIT_FOR_CAB BIT(1) 668 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 669 #define PS_WAIT_FOR_TX_ACK BIT(3) 670 #define PS_BEACON_SYNC BIT(4) 671 #define PS_WAIT_FOR_ANI BIT(5) 672 673 struct ath_rate_table; 674 675 struct ath9k_vif_iter_data { 676 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ 677 u8 mask[ETH_ALEN]; /* bssid mask */ 678 bool has_hw_macaddr; 679 680 int naps; /* number of AP vifs */ 681 int nmeshes; /* number of mesh vifs */ 682 int nstations; /* number of station vifs */ 683 int nwds; /* number of WDS vifs */ 684 int nadhocs; /* number of adhoc vifs */ 685 }; 686 687 /* enum spectral_mode: 688 * 689 * @SPECTRAL_DISABLED: spectral mode is disabled 690 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with 691 * something else. 692 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples 693 * is performed manually. 694 * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels 695 * during a channel scan. 696 */ 697 enum spectral_mode { 698 SPECTRAL_DISABLED = 0, 699 SPECTRAL_BACKGROUND, 700 SPECTRAL_MANUAL, 701 SPECTRAL_CHANSCAN, 702 }; 703 704 struct ath_softc { 705 struct ieee80211_hw *hw; 706 struct device *dev; 707 708 struct survey_info *cur_survey; 709 struct survey_info survey[ATH9K_NUM_CHANNELS]; 710 711 struct tasklet_struct intr_tq; 712 struct tasklet_struct bcon_tasklet; 713 struct ath_hw *sc_ah; 714 void __iomem *mem; 715 int irq; 716 spinlock_t sc_serial_rw; 717 spinlock_t sc_pm_lock; 718 spinlock_t sc_pcu_lock; 719 struct mutex mutex; 720 struct work_struct paprd_work; 721 struct work_struct hw_check_work; 722 struct work_struct hw_reset_work; 723 struct completion paprd_complete; 724 725 unsigned int hw_busy_count; 726 unsigned long sc_flags; 727 unsigned long driver_data; 728 729 u32 intrstatus; 730 u16 ps_flags; /* PS_* */ 731 u16 curtxpow; 732 bool ps_enabled; 733 bool ps_idle; 734 short nbcnvifs; 735 short nvifs; 736 unsigned long ps_usecount; 737 738 struct ath_config config; 739 struct ath_rx rx; 740 struct ath_tx tx; 741 struct ath_beacon beacon; 742 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 743 744 #ifdef CONFIG_MAC80211_LEDS 745 bool led_registered; 746 char led_name[32]; 747 struct led_classdev led_cdev; 748 #endif 749 750 struct ath9k_hw_cal_data caldata; 751 int last_rssi; 752 753 #ifdef CONFIG_ATH9K_DEBUGFS 754 struct ath9k_debug debug; 755 #endif 756 struct ath_beacon_config cur_beacon_conf; 757 struct delayed_work tx_complete_work; 758 struct delayed_work hw_pll_work; 759 struct timer_list rx_poll_timer; 760 761 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 762 struct ath_btcoex btcoex; 763 struct ath_mci_coex mci_coex; 764 struct work_struct mci_work; 765 #endif 766 767 struct ath_descdma txsdma; 768 769 struct ath_ant_comb ant_comb; 770 u8 ant_tx, ant_rx; 771 struct dfs_pattern_detector *dfs_detector; 772 u32 wow_enabled; 773 /* relay(fs) channel for spectral scan */ 774 struct rchan *rfs_chan_spec_scan; 775 enum spectral_mode spectral_mode; 776 struct ath_spec_scan spec_config; 777 778 #ifdef CONFIG_PM_SLEEP 779 atomic_t wow_got_bmiss_intr; 780 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 781 u32 wow_intr_before_sleep; 782 #endif 783 }; 784 785 #define SPECTRAL_SCAN_BITMASK 0x10 786 /* Radar info packet format, used for DFS and spectral formats. */ 787 struct ath_radar_info { 788 u8 pulse_length_pri; 789 u8 pulse_length_ext; 790 u8 pulse_bw_info; 791 } __packed; 792 793 /* The HT20 spectral data has 4 bytes of additional information at it's end. 794 * 795 * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]} 796 * [7:0]: all bins max_magnitude[9:2] 797 * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]} 798 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) 799 */ 800 struct ath_ht20_mag_info { 801 u8 all_bins[3]; 802 u8 max_exp; 803 } __packed; 804 805 #define SPECTRAL_HT20_NUM_BINS 56 806 807 /* WARNING: don't actually use this struct! MAC may vary the amount of 808 * data by -1/+2. This struct is for reference only. 809 */ 810 struct ath_ht20_fft_packet { 811 u8 data[SPECTRAL_HT20_NUM_BINS]; 812 struct ath_ht20_mag_info mag_info; 813 struct ath_radar_info radar_info; 814 } __packed; 815 816 #define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet)) 817 818 /* Dynamic 20/40 mode: 819 * 820 * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]} 821 * [7:0]: lower bins max_magnitude[9:2] 822 * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]} 823 * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]} 824 * [7:0]: upper bins max_magnitude[9:2] 825 * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]} 826 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) 827 */ 828 struct ath_ht20_40_mag_info { 829 u8 lower_bins[3]; 830 u8 upper_bins[3]; 831 u8 max_exp; 832 } __packed; 833 834 #define SPECTRAL_HT20_40_NUM_BINS 128 835 836 /* WARNING: don't actually use this struct! MAC may vary the amount of 837 * data. This struct is for reference only. 838 */ 839 struct ath_ht20_40_fft_packet { 840 u8 data[SPECTRAL_HT20_40_NUM_BINS]; 841 struct ath_ht20_40_mag_info mag_info; 842 struct ath_radar_info radar_info; 843 } __packed; 844 845 846 #define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet)) 847 848 /* grabs the max magnitude from the all/upper/lower bins */ 849 static inline u16 spectral_max_magnitude(u8 *bins) 850 { 851 return (bins[0] & 0xc0) >> 6 | 852 (bins[1] & 0xff) << 2 | 853 (bins[2] & 0x03) << 10; 854 } 855 856 /* return the max magnitude from the all/upper/lower bins */ 857 static inline u8 spectral_max_index(u8 *bins) 858 { 859 s8 m = (bins[2] & 0xfc) >> 2; 860 861 /* TODO: this still doesn't always report the right values ... */ 862 if (m > 32) 863 m |= 0xe0; 864 else 865 m &= ~0xe0; 866 867 return m + 29; 868 } 869 870 /* return the bitmap weight from the all/upper/lower bins */ 871 static inline u8 spectral_bitmap_weight(u8 *bins) 872 { 873 return bins[0] & 0x3f; 874 } 875 876 /* FFT sample format given to userspace via debugfs. 877 * 878 * Please keep the type/length at the front position and change 879 * other fields after adding another sample type 880 * 881 * TODO: this might need rework when switching to nl80211-based 882 * interface. 883 */ 884 enum ath_fft_sample_type { 885 ATH_FFT_SAMPLE_HT20 = 1, 886 }; 887 888 struct fft_sample_tlv { 889 u8 type; /* see ath_fft_sample */ 890 __be16 length; 891 /* type dependent data follows */ 892 } __packed; 893 894 struct fft_sample_ht20 { 895 struct fft_sample_tlv tlv; 896 897 u8 max_exp; 898 899 __be16 freq; 900 s8 rssi; 901 s8 noise; 902 903 __be16 max_magnitude; 904 u8 max_index; 905 u8 bitmap_weight; 906 907 __be64 tsf; 908 909 u8 data[SPECTRAL_HT20_NUM_BINS]; 910 } __packed; 911 912 void ath9k_tasklet(unsigned long data); 913 int ath_cabq_update(struct ath_softc *); 914 915 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 916 { 917 common->bus_ops->read_cachesize(common, csz); 918 } 919 920 extern struct ieee80211_ops ath9k_ops; 921 extern int ath9k_modparam_nohwcrypt; 922 extern int led_blink; 923 extern bool is_ath9k_unloaded; 924 925 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 926 irqreturn_t ath_isr(int irq, void *dev); 927 int ath9k_init_device(u16 devid, struct ath_softc *sc, 928 const struct ath_bus_ops *bus_ops); 929 void ath9k_deinit_device(struct ath_softc *sc); 930 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 931 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 932 933 bool ath9k_uses_beacons(int type); 934 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw); 935 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 936 enum spectral_mode spectral_mode); 937 938 939 #ifdef CONFIG_ATH9K_PCI 940 int ath_pci_init(void); 941 void ath_pci_exit(void); 942 #else 943 static inline int ath_pci_init(void) { return 0; }; 944 static inline void ath_pci_exit(void) {}; 945 #endif 946 947 #ifdef CONFIG_ATH9K_AHB 948 int ath_ahb_init(void); 949 void ath_ahb_exit(void); 950 #else 951 static inline int ath_ahb_init(void) { return 0; }; 952 static inline void ath_ahb_exit(void) {}; 953 #endif 954 955 void ath9k_ps_wakeup(struct ath_softc *sc); 956 void ath9k_ps_restore(struct ath_softc *sc); 957 958 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 959 960 void ath_start_rfkill_poll(struct ath_softc *sc); 961 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 962 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 963 struct ieee80211_vif *vif, 964 struct ath9k_vif_iter_data *iter_data); 965 966 #endif /* ATH9K_H */ 967