1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/leds.h> 23 #include <linux/completion.h> 24 25 #include "debug.h" 26 #include "common.h" 27 28 /* 29 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 30 * should rely on this file or its contents. 31 */ 32 33 struct ath_node; 34 35 /* Macro to expand scalars to 64-bit objects */ 36 37 #define ito64(x) (sizeof(x) == 1) ? \ 38 (((unsigned long long int)(x)) & (0xff)) : \ 39 (sizeof(x) == 2) ? \ 40 (((unsigned long long int)(x)) & 0xffff) : \ 41 ((sizeof(x) == 4) ? \ 42 (((unsigned long long int)(x)) & 0xffffffff) : \ 43 (unsigned long long int)(x)) 44 45 /* increment with wrap-around */ 46 #define INCR(_l, _sz) do { \ 47 (_l)++; \ 48 (_l) &= ((_sz) - 1); \ 49 } while (0) 50 51 /* decrement with wrap-around */ 52 #define DECR(_l, _sz) do { \ 53 (_l)--; \ 54 (_l) &= ((_sz) - 1); \ 55 } while (0) 56 57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 58 59 #define TSF_TO_TU(_h,_l) \ 60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 61 62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 63 64 struct ath_config { 65 u32 ath_aggr_prot; 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 * @BUF_XRETRY: To denote excessive retries of the buffer 93 */ 94 enum buffer_type { 95 BUF_AMPDU = BIT(2), 96 BUF_AGGR = BIT(3), 97 BUF_XRETRY = BIT(5), 98 }; 99 100 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 101 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 102 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 103 104 #define ATH_TXSTATUS_RING_SIZE 64 105 106 struct ath_descdma { 107 void *dd_desc; 108 dma_addr_t dd_desc_paddr; 109 u32 dd_desc_len; 110 struct ath_buf *dd_bufptr; 111 }; 112 113 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 114 struct list_head *head, const char *name, 115 int nbuf, int ndesc, bool is_tx); 116 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 117 struct list_head *head); 118 119 /***********/ 120 /* RX / TX */ 121 /***********/ 122 123 #define ATH_MAX_ANTENNA 3 124 #define ATH_RXBUF 512 125 #define ATH_TXBUF 512 126 #define ATH_TXBUF_RESERVE 5 127 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 128 #define ATH_TXMAXTRY 13 129 #define ATH_MGT_TXMAXTRY 4 130 131 #define TID_TO_WME_AC(_tid) \ 132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 135 WME_AC_VO) 136 137 #define ADDBA_EXCHANGE_ATTEMPTS 10 138 #define ATH_AGGR_DELIM_SZ 4 139 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 140 /* number of delimiters for encryption padding */ 141 #define ATH_AGGR_ENCRYPTDELIM 10 142 /* minimum h/w qdepth to be sustained to maximize aggregation */ 143 #define ATH_AGGR_MIN_QDEPTH 2 144 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 145 146 #define IEEE80211_SEQ_SEQ_SHIFT 4 147 #define IEEE80211_SEQ_MAX 4096 148 #define IEEE80211_WEP_IVLEN 3 149 #define IEEE80211_WEP_KIDLEN 1 150 #define IEEE80211_WEP_CRCLEN 4 151 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 152 (IEEE80211_WEP_IVLEN + \ 153 IEEE80211_WEP_KIDLEN + \ 154 IEEE80211_WEP_CRCLEN)) 155 156 /* return whether a bit at index _n in bitmap _bm is set 157 * _sz is the size of the bitmap */ 158 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 159 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 160 161 /* return block-ack bitmap index given sequence and starting sequence */ 162 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 163 164 /* returns delimiter padding required given the packet length */ 165 #define ATH_AGGR_GET_NDELIM(_len) \ 166 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 167 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 168 169 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 170 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 171 172 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 173 174 #define ATH_TX_COMPLETE_POLL_INT 1000 175 176 enum ATH_AGGR_STATUS { 177 ATH_AGGR_DONE, 178 ATH_AGGR_BAW_CLOSED, 179 ATH_AGGR_LIMITED, 180 }; 181 182 #define ATH_TXFIFO_DEPTH 8 183 struct ath_txq { 184 u32 axq_qnum; 185 u32 *axq_link; 186 struct list_head axq_q; 187 spinlock_t axq_lock; 188 u32 axq_depth; 189 u32 axq_ampdu_depth; 190 bool stopped; 191 bool axq_tx_inprogress; 192 struct list_head axq_acq; 193 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 194 struct list_head txq_fifo_pending; 195 u8 txq_headidx; 196 u8 txq_tailidx; 197 int pending_frames; 198 }; 199 200 struct ath_atx_ac { 201 struct ath_txq *txq; 202 int sched; 203 struct list_head list; 204 struct list_head tid_q; 205 }; 206 207 struct ath_frame_info { 208 int framelen; 209 u32 keyix; 210 enum ath9k_key_type keytype; 211 u8 retries; 212 u16 seqno; 213 }; 214 215 struct ath_buf_state { 216 u8 bf_type; 217 u8 bfs_paprd; 218 unsigned long bfs_paprd_timestamp; 219 enum ath9k_internal_frame_type bfs_ftype; 220 }; 221 222 struct ath_buf { 223 struct list_head list; 224 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 225 an aggregate) */ 226 struct ath_buf *bf_next; /* next subframe in the aggregate */ 227 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 228 void *bf_desc; /* virtual addr of desc */ 229 dma_addr_t bf_daddr; /* physical addr of desc */ 230 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 231 bool bf_stale; 232 u16 bf_flags; 233 struct ath_buf_state bf_state; 234 struct ath_wiphy *aphy; 235 }; 236 237 struct ath_atx_tid { 238 struct list_head list; 239 struct list_head buf_q; 240 struct ath_node *an; 241 struct ath_atx_ac *ac; 242 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 243 u16 seq_start; 244 u16 seq_next; 245 u16 baw_size; 246 int tidno; 247 int baw_head; /* first un-acked tx buffer */ 248 int baw_tail; /* next unused tx buffer slot */ 249 int sched; 250 int paused; 251 u8 state; 252 }; 253 254 struct ath_node { 255 struct ath_common *common; 256 struct ath_atx_tid tid[WME_NUM_TID]; 257 struct ath_atx_ac ac[WME_NUM_AC]; 258 u16 maxampdu; 259 u8 mpdudensity; 260 }; 261 262 #define AGGR_CLEANUP BIT(1) 263 #define AGGR_ADDBA_COMPLETE BIT(2) 264 #define AGGR_ADDBA_PROGRESS BIT(3) 265 266 struct ath_tx_control { 267 struct ath_txq *txq; 268 struct ath_node *an; 269 int if_id; 270 enum ath9k_internal_frame_type frame_type; 271 u8 paprd; 272 }; 273 274 #define ATH_TX_ERROR 0x01 275 #define ATH_TX_XRETRY 0x02 276 #define ATH_TX_BAR 0x04 277 278 struct ath_tx { 279 u16 seq_no; 280 u32 txqsetup; 281 spinlock_t txbuflock; 282 struct list_head txbuf; 283 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 284 struct ath_descdma txdma; 285 struct ath_txq *txq_map[WME_NUM_AC]; 286 }; 287 288 struct ath_rx_edma { 289 struct sk_buff_head rx_fifo; 290 struct sk_buff_head rx_buffers; 291 u32 rx_fifo_hwsize; 292 }; 293 294 struct ath_rx { 295 u8 defant; 296 u8 rxotherant; 297 u32 *rxlink; 298 unsigned int rxfilter; 299 spinlock_t rxbuflock; 300 struct list_head rxbuf; 301 struct ath_descdma rxdma; 302 struct ath_buf *rx_bufptr; 303 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 304 }; 305 306 int ath_startrecv(struct ath_softc *sc); 307 bool ath_stoprecv(struct ath_softc *sc); 308 void ath_flushrecv(struct ath_softc *sc); 309 u32 ath_calcrxfilter(struct ath_softc *sc); 310 int ath_rx_init(struct ath_softc *sc, int nbufs); 311 void ath_rx_cleanup(struct ath_softc *sc); 312 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 313 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 314 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 315 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 316 void ath_draintxq(struct ath_softc *sc, 317 struct ath_txq *txq, bool retry_tx); 318 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 319 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 320 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 321 int ath_tx_init(struct ath_softc *sc, int nbufs); 322 void ath_tx_cleanup(struct ath_softc *sc); 323 int ath_txq_update(struct ath_softc *sc, int qnum, 324 struct ath9k_tx_queue_info *q); 325 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 326 struct ath_tx_control *txctl); 327 void ath_tx_tasklet(struct ath_softc *sc); 328 void ath_tx_edma_tasklet(struct ath_softc *sc); 329 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 330 u16 tid, u16 *ssn); 331 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 332 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 333 334 /********/ 335 /* VIFs */ 336 /********/ 337 338 struct ath_vif { 339 int av_bslot; 340 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 341 enum nl80211_iftype av_opmode; 342 struct ath_buf *av_bcbuf; 343 struct ath_tx_control av_btxctl; 344 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ 345 }; 346 347 /*******************/ 348 /* Beacon Handling */ 349 /*******************/ 350 351 /* 352 * Regardless of the number of beacons we stagger, (i.e. regardless of the 353 * number of BSSIDs) if a given beacon does not go out even after waiting this 354 * number of beacon intervals, the game's up. 355 */ 356 #define BSTUCK_THRESH (9 * ATH_BCBUF) 357 #define ATH_BCBUF 4 358 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 359 #define ATH_DEFAULT_BMISS_LIMIT 10 360 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 361 362 struct ath_beacon_config { 363 u16 beacon_interval; 364 u16 listen_interval; 365 u16 dtim_period; 366 u16 bmiss_timeout; 367 u8 dtim_count; 368 }; 369 370 struct ath_beacon { 371 enum { 372 OK, /* no change needed */ 373 UPDATE, /* update pending */ 374 COMMIT /* beacon sent, commit change */ 375 } updateslot; /* slot time update fsm */ 376 377 u32 beaconq; 378 u32 bmisscnt; 379 u32 ast_be_xmit; 380 u64 bc_tstamp; 381 struct ieee80211_vif *bslot[ATH_BCBUF]; 382 struct ath_wiphy *bslot_aphy[ATH_BCBUF]; 383 int slottime; 384 int slotupdate; 385 struct ath9k_tx_queue_info beacon_qi; 386 struct ath_descdma bdma; 387 struct ath_txq *cabq; 388 struct list_head bbuf; 389 }; 390 391 void ath_beacon_tasklet(unsigned long data); 392 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 393 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 394 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 395 int ath_beaconq_config(struct ath_softc *sc); 396 397 /*******/ 398 /* ANI */ 399 /*******/ 400 401 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 402 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 403 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 404 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 405 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 406 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 407 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 408 409 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 410 411 void ath_hw_check(struct work_struct *work); 412 void ath_paprd_calibrate(struct work_struct *work); 413 void ath_ani_calibrate(unsigned long data); 414 415 /**********/ 416 /* BTCOEX */ 417 /**********/ 418 419 struct ath_btcoex { 420 bool hw_timer_enabled; 421 spinlock_t btcoex_lock; 422 struct timer_list period_timer; /* Timer for BT period */ 423 u32 bt_priority_cnt; 424 unsigned long bt_priority_time; 425 int bt_stomp_type; /* Types of BT stomping */ 426 u32 btcoex_no_stomp; /* in usec */ 427 u32 btcoex_period; /* in usec */ 428 u32 btscan_no_stomp; /* in usec */ 429 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 430 }; 431 432 int ath_init_btcoex_timer(struct ath_softc *sc); 433 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 434 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 435 436 /********************/ 437 /* LED Control */ 438 /********************/ 439 440 #define ATH_LED_PIN_DEF 1 441 #define ATH_LED_PIN_9287 8 442 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ 443 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ 444 445 enum ath_led_type { 446 ATH_LED_RADIO, 447 ATH_LED_ASSOC, 448 ATH_LED_TX, 449 ATH_LED_RX 450 }; 451 452 struct ath_led { 453 struct ath_softc *sc; 454 struct led_classdev led_cdev; 455 enum ath_led_type led_type; 456 char name[32]; 457 bool registered; 458 }; 459 460 void ath_init_leds(struct ath_softc *sc); 461 void ath_deinit_leds(struct ath_softc *sc); 462 463 /* Antenna diversity/combining */ 464 #define ATH_ANT_RX_CURRENT_SHIFT 4 465 #define ATH_ANT_RX_MAIN_SHIFT 2 466 #define ATH_ANT_RX_MASK 0x3 467 468 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 469 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 470 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 471 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 472 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 473 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 474 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 475 476 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3 477 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 478 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 479 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 480 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 481 482 enum ath9k_ant_div_comb_lna_conf { 483 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 484 ATH_ANT_DIV_COMB_LNA2, 485 ATH_ANT_DIV_COMB_LNA1, 486 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 487 }; 488 489 struct ath_ant_comb { 490 u16 count; 491 u16 total_pkt_count; 492 bool scan; 493 bool scan_not_start; 494 int main_total_rssi; 495 int alt_total_rssi; 496 int alt_recv_cnt; 497 int main_recv_cnt; 498 int rssi_lna1; 499 int rssi_lna2; 500 int rssi_add; 501 int rssi_sub; 502 int rssi_first; 503 int rssi_second; 504 int rssi_third; 505 bool alt_good; 506 int quick_scan_cnt; 507 int main_conf; 508 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 509 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 510 int first_bias; 511 int second_bias; 512 bool first_ratio; 513 bool second_ratio; 514 unsigned long scan_start_time; 515 }; 516 517 /********************/ 518 /* Main driver core */ 519 /********************/ 520 521 /* 522 * Default cache line size, in bytes. 523 * Used when PCI device not fully initialized by bootrom/BIOS 524 */ 525 #define DEFAULT_CACHELINE 32 526 #define ATH_REGCLASSIDS_MAX 10 527 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 528 #define ATH_MAX_SW_RETRIES 10 529 #define ATH_CHAN_MAX 255 530 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 531 532 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 533 #define ATH_RATE_DUMMY_MARKER 0 534 535 #define SC_OP_INVALID BIT(0) 536 #define SC_OP_BEACONS BIT(1) 537 #define SC_OP_RXAGGR BIT(2) 538 #define SC_OP_TXAGGR BIT(3) 539 #define SC_OP_OFFCHANNEL BIT(4) 540 #define SC_OP_PREAMBLE_SHORT BIT(5) 541 #define SC_OP_PROTECT_ENABLE BIT(6) 542 #define SC_OP_RXFLUSH BIT(7) 543 #define SC_OP_LED_ASSOCIATED BIT(8) 544 #define SC_OP_LED_ON BIT(9) 545 #define SC_OP_TSF_RESET BIT(11) 546 #define SC_OP_BT_PRIORITY_DETECTED BIT(12) 547 #define SC_OP_BT_SCAN BIT(13) 548 #define SC_OP_ANI_RUN BIT(14) 549 #define SC_OP_ENABLE_APM BIT(15) 550 551 /* Powersave flags */ 552 #define PS_WAIT_FOR_BEACON BIT(0) 553 #define PS_WAIT_FOR_CAB BIT(1) 554 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 555 #define PS_WAIT_FOR_TX_ACK BIT(3) 556 #define PS_BEACON_SYNC BIT(4) 557 558 struct ath_wiphy; 559 struct ath_rate_table; 560 561 struct ath_softc { 562 struct ieee80211_hw *hw; 563 struct device *dev; 564 565 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 566 struct ath_wiphy *pri_wiphy; 567 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 568 * have NULL entries */ 569 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ 570 int chan_idx; 571 int chan_is_ht; 572 struct ath_wiphy *next_wiphy; 573 struct work_struct chan_work; 574 int wiphy_select_failures; 575 unsigned long wiphy_select_first_fail; 576 struct delayed_work wiphy_work; 577 unsigned long wiphy_scheduler_int; 578 int wiphy_scheduler_index; 579 struct survey_info *cur_survey; 580 struct survey_info survey[ATH9K_NUM_CHANNELS]; 581 582 struct tasklet_struct intr_tq; 583 struct tasklet_struct bcon_tasklet; 584 struct ath_hw *sc_ah; 585 void __iomem *mem; 586 int irq; 587 spinlock_t sc_serial_rw; 588 spinlock_t sc_pm_lock; 589 spinlock_t sc_pcu_lock; 590 struct mutex mutex; 591 struct work_struct paprd_work; 592 struct work_struct hw_check_work; 593 struct completion paprd_complete; 594 595 u32 intrstatus; 596 u32 sc_flags; /* SC_OP_* */ 597 u16 ps_flags; /* PS_* */ 598 u16 curtxpow; 599 u8 nbcnvifs; 600 u16 nvifs; 601 bool ps_enabled; 602 bool ps_idle; 603 unsigned long ps_usecount; 604 605 struct ath_config config; 606 struct ath_rx rx; 607 struct ath_tx tx; 608 struct ath_beacon beacon; 609 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 610 611 struct ath_led radio_led; 612 struct ath_led assoc_led; 613 struct ath_led tx_led; 614 struct ath_led rx_led; 615 struct delayed_work ath_led_blink_work; 616 int led_on_duration; 617 int led_off_duration; 618 int led_on_cnt; 619 int led_off_cnt; 620 621 int beacon_interval; 622 623 #ifdef CONFIG_ATH9K_DEBUGFS 624 struct ath9k_debug debug; 625 #endif 626 struct ath_beacon_config cur_beacon_conf; 627 struct delayed_work tx_complete_work; 628 struct ath_btcoex btcoex; 629 630 struct ath_descdma txsdma; 631 632 struct ath_ant_comb ant_comb; 633 }; 634 635 struct ath_wiphy { 636 struct ath_softc *sc; /* shared for all virtual wiphys */ 637 struct ieee80211_hw *hw; 638 struct ath9k_hw_cal_data caldata; 639 enum ath_wiphy_state { 640 ATH_WIPHY_INACTIVE, 641 ATH_WIPHY_ACTIVE, 642 ATH_WIPHY_PAUSING, 643 ATH_WIPHY_PAUSED, 644 ATH_WIPHY_SCAN, 645 } state; 646 bool idle; 647 int chan_idx; 648 int chan_is_ht; 649 int last_rssi; 650 }; 651 652 void ath9k_tasklet(unsigned long data); 653 int ath_reset(struct ath_softc *sc, bool retry_tx); 654 int ath_cabq_update(struct ath_softc *); 655 656 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 657 { 658 common->bus_ops->read_cachesize(common, csz); 659 } 660 661 extern struct ieee80211_ops ath9k_ops; 662 extern int ath9k_modparam_nohwcrypt; 663 extern int led_blink; 664 extern bool is_ath9k_unloaded; 665 666 irqreturn_t ath_isr(int irq, void *dev); 667 void ath9k_init_crypto(struct ath_softc *sc); 668 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, 669 const struct ath_bus_ops *bus_ops); 670 void ath9k_deinit_device(struct ath_softc *sc); 671 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 672 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 673 struct ath9k_channel *ichan); 674 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 675 struct ath9k_channel *hchan); 676 677 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); 678 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); 679 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); 680 681 #ifdef CONFIG_PCI 682 int ath_pci_init(void); 683 void ath_pci_exit(void); 684 #else 685 static inline int ath_pci_init(void) { return 0; }; 686 static inline void ath_pci_exit(void) {}; 687 #endif 688 689 #ifdef CONFIG_ATHEROS_AR71XX 690 int ath_ahb_init(void); 691 void ath_ahb_exit(void); 692 #else 693 static inline int ath_ahb_init(void) { return 0; }; 694 static inline void ath_ahb_exit(void) {}; 695 #endif 696 697 void ath9k_ps_wakeup(struct ath_softc *sc); 698 void ath9k_ps_restore(struct ath_softc *sc); 699 700 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 701 702 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 703 int ath9k_wiphy_add(struct ath_softc *sc); 704 int ath9k_wiphy_del(struct ath_wiphy *aphy); 705 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype); 706 int ath9k_wiphy_pause(struct ath_wiphy *aphy); 707 int ath9k_wiphy_unpause(struct ath_wiphy *aphy); 708 int ath9k_wiphy_select(struct ath_wiphy *aphy); 709 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); 710 void ath9k_wiphy_chan_work(struct work_struct *work); 711 bool ath9k_wiphy_started(struct ath_softc *sc); 712 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, 713 struct ath_wiphy *selected); 714 bool ath9k_wiphy_scanning(struct ath_softc *sc); 715 void ath9k_wiphy_work(struct work_struct *work); 716 bool ath9k_all_wiphys_idle(struct ath_softc *sc); 717 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); 718 719 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); 720 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); 721 722 void ath_start_rfkill_poll(struct ath_softc *sc); 723 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 724 725 #endif /* ATH9K_H */ 726