1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 }; 113 114 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 115 struct list_head *head, const char *name, 116 int nbuf, int ndesc, bool is_tx); 117 118 /***********/ 119 /* RX / TX */ 120 /***********/ 121 122 #define ATH_RXBUF 512 123 #define ATH_TXBUF 512 124 #define ATH_TXBUF_RESERVE 5 125 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 126 #define ATH_TXMAXTRY 13 127 128 #define TID_TO_WME_AC(_tid) \ 129 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ 130 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ 131 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ 132 IEEE80211_AC_VO) 133 134 #define ATH_AGGR_DELIM_SZ 4 135 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 136 /* number of delimiters for encryption padding */ 137 #define ATH_AGGR_ENCRYPTDELIM 10 138 /* minimum h/w qdepth to be sustained to maximize aggregation */ 139 #define ATH_AGGR_MIN_QDEPTH 2 140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 141 142 #define IEEE80211_SEQ_SEQ_SHIFT 4 143 #define IEEE80211_SEQ_MAX 4096 144 #define IEEE80211_WEP_IVLEN 3 145 #define IEEE80211_WEP_KIDLEN 1 146 #define IEEE80211_WEP_CRCLEN 4 147 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 148 (IEEE80211_WEP_IVLEN + \ 149 IEEE80211_WEP_KIDLEN + \ 150 IEEE80211_WEP_CRCLEN)) 151 152 /* return whether a bit at index _n in bitmap _bm is set 153 * _sz is the size of the bitmap */ 154 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 155 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 156 157 /* return block-ack bitmap index given sequence and starting sequence */ 158 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 159 160 /* return the seqno for _start + _offset */ 161 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 162 163 /* returns delimiter padding required given the packet length */ 164 #define ATH_AGGR_GET_NDELIM(_len) \ 165 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 166 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 167 168 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 169 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 170 171 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 172 173 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 174 175 #define ATH_TX_COMPLETE_POLL_INT 1000 176 177 enum ATH_AGGR_STATUS { 178 ATH_AGGR_DONE, 179 ATH_AGGR_BAW_CLOSED, 180 ATH_AGGR_LIMITED, 181 }; 182 183 #define ATH_TXFIFO_DEPTH 8 184 struct ath_txq { 185 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 186 u32 axq_qnum; /* ath9k hardware queue number */ 187 void *axq_link; 188 struct list_head axq_q; 189 spinlock_t axq_lock; 190 u32 axq_depth; 191 u32 axq_ampdu_depth; 192 bool stopped; 193 bool axq_tx_inprogress; 194 struct list_head axq_acq; 195 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 196 u8 txq_headidx; 197 u8 txq_tailidx; 198 int pending_frames; 199 struct sk_buff_head complete_q; 200 }; 201 202 struct ath_atx_ac { 203 struct ath_txq *txq; 204 int sched; 205 struct list_head list; 206 struct list_head tid_q; 207 bool clear_ps_filter; 208 }; 209 210 struct ath_frame_info { 211 struct ath_buf *bf; 212 int framelen; 213 enum ath9k_key_type keytype; 214 u8 keyix; 215 u8 retries; 216 u8 rtscts_rate; 217 }; 218 219 struct ath_buf_state { 220 u8 bf_type; 221 u8 bfs_paprd; 222 u8 ndelim; 223 u16 seqno; 224 unsigned long bfs_paprd_timestamp; 225 }; 226 227 struct ath_buf { 228 struct list_head list; 229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 230 an aggregate) */ 231 struct ath_buf *bf_next; /* next subframe in the aggregate */ 232 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 233 void *bf_desc; /* virtual addr of desc */ 234 dma_addr_t bf_daddr; /* physical addr of desc */ 235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 236 bool bf_stale; 237 struct ieee80211_tx_rate rates[4]; 238 struct ath_buf_state bf_state; 239 }; 240 241 struct ath_atx_tid { 242 struct list_head list; 243 struct sk_buff_head buf_q; 244 struct ath_node *an; 245 struct ath_atx_ac *ac; 246 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 247 int bar_index; 248 u16 seq_start; 249 u16 seq_next; 250 u16 baw_size; 251 int tidno; 252 int baw_head; /* first un-acked tx buffer */ 253 int baw_tail; /* next unused tx buffer slot */ 254 bool sched; 255 bool paused; 256 bool active; 257 }; 258 259 struct ath_node { 260 struct ath_softc *sc; 261 struct ieee80211_sta *sta; /* station struct we're part of */ 262 struct ieee80211_vif *vif; /* interface with which we're associated */ 263 struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; 264 struct ath_atx_ac ac[IEEE80211_NUM_ACS]; 265 int ps_key; 266 267 u16 maxampdu; 268 u8 mpdudensity; 269 270 bool sleeping; 271 272 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 273 struct dentry *node_stat; 274 #endif 275 }; 276 277 struct ath_tx_control { 278 struct ath_txq *txq; 279 struct ath_node *an; 280 u8 paprd; 281 struct ieee80211_sta *sta; 282 }; 283 284 #define ATH_TX_ERROR 0x01 285 286 /** 287 * @txq_map: Index is mac80211 queue number. This is 288 * not necessarily the same as the hardware queue number 289 * (axq_qnum). 290 */ 291 struct ath_tx { 292 u16 seq_no; 293 u32 txqsetup; 294 spinlock_t txbuflock; 295 struct list_head txbuf; 296 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 297 struct ath_descdma txdma; 298 struct ath_txq *txq_map[IEEE80211_NUM_ACS]; 299 struct ath_txq *uapsdq; 300 u32 txq_max_pending[IEEE80211_NUM_ACS]; 301 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; 302 }; 303 304 struct ath_rx_edma { 305 struct sk_buff_head rx_fifo; 306 u32 rx_fifo_hwsize; 307 }; 308 309 struct ath_rx { 310 u8 defant; 311 u8 rxotherant; 312 bool discard_next; 313 u32 *rxlink; 314 u32 num_pkts; 315 unsigned int rxfilter; 316 struct list_head rxbuf; 317 struct ath_descdma rxdma; 318 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 319 320 struct sk_buff *frag; 321 322 u32 ampdu_ref; 323 }; 324 325 int ath_startrecv(struct ath_softc *sc); 326 bool ath_stoprecv(struct ath_softc *sc); 327 u32 ath_calcrxfilter(struct ath_softc *sc); 328 int ath_rx_init(struct ath_softc *sc, int nbufs); 329 void ath_rx_cleanup(struct ath_softc *sc); 330 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 331 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 332 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 333 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 334 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 335 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 336 bool ath_drain_all_txq(struct ath_softc *sc); 337 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); 338 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 339 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 340 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 341 int ath_tx_init(struct ath_softc *sc, int nbufs); 342 int ath_txq_update(struct ath_softc *sc, int qnum, 343 struct ath9k_tx_queue_info *q); 344 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 345 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 346 struct ath_tx_control *txctl); 347 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 348 struct sk_buff *skb); 349 void ath_tx_tasklet(struct ath_softc *sc); 350 void ath_tx_edma_tasklet(struct ath_softc *sc); 351 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 352 u16 tid, u16 *ssn); 353 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 354 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 355 356 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 357 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 358 struct ath_node *an); 359 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 360 struct ieee80211_sta *sta, 361 u16 tids, int nframes, 362 enum ieee80211_frame_release_type reason, 363 bool more_data); 364 365 /********/ 366 /* VIFs */ 367 /********/ 368 369 struct ath_vif { 370 int av_bslot; 371 bool primary_sta_vif; 372 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 373 struct ath_buf *av_bcbuf; 374 }; 375 376 /*******************/ 377 /* Beacon Handling */ 378 /*******************/ 379 380 /* 381 * Regardless of the number of beacons we stagger, (i.e. regardless of the 382 * number of BSSIDs) if a given beacon does not go out even after waiting this 383 * number of beacon intervals, the game's up. 384 */ 385 #define BSTUCK_THRESH 9 386 #define ATH_BCBUF 8 387 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 388 #define ATH_DEFAULT_BMISS_LIMIT 10 389 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 390 391 struct ath_beacon_config { 392 int beacon_interval; 393 u16 listen_interval; 394 u16 dtim_period; 395 u16 bmiss_timeout; 396 u8 dtim_count; 397 bool enable_beacon; 398 bool ibss_creator; 399 }; 400 401 struct ath_beacon { 402 enum { 403 OK, /* no change needed */ 404 UPDATE, /* update pending */ 405 COMMIT /* beacon sent, commit change */ 406 } updateslot; /* slot time update fsm */ 407 408 u32 beaconq; 409 u32 bmisscnt; 410 u32 bc_tstamp; 411 struct ieee80211_vif *bslot[ATH_BCBUF]; 412 int slottime; 413 int slotupdate; 414 struct ath9k_tx_queue_info beacon_qi; 415 struct ath_descdma bdma; 416 struct ath_txq *cabq; 417 struct list_head bbuf; 418 419 bool tx_processed; 420 bool tx_last; 421 }; 422 423 void ath9k_beacon_tasklet(unsigned long data); 424 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 425 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 426 u32 changed); 427 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 428 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 429 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 430 void ath9k_set_beacon(struct ath_softc *sc); 431 432 /*******************/ 433 /* Link Monitoring */ 434 /*******************/ 435 436 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 437 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 438 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 439 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 440 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 441 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 442 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 443 #define ATH_ANI_MAX_SKIP_COUNT 10 444 445 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 446 #define ATH_PLL_WORK_INTERVAL 100 447 448 void ath_tx_complete_poll_work(struct work_struct *work); 449 void ath_reset_work(struct work_struct *work); 450 void ath_hw_check(struct work_struct *work); 451 void ath_hw_pll_work(struct work_struct *work); 452 void ath_rx_poll(unsigned long data); 453 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 454 void ath_paprd_calibrate(struct work_struct *work); 455 void ath_ani_calibrate(unsigned long data); 456 void ath_start_ani(struct ath_softc *sc); 457 void ath_stop_ani(struct ath_softc *sc); 458 void ath_check_ani(struct ath_softc *sc); 459 int ath_update_survey_stats(struct ath_softc *sc); 460 void ath_update_survey_nf(struct ath_softc *sc, int channel); 461 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 462 463 /**********/ 464 /* BTCOEX */ 465 /**********/ 466 467 #define ATH_DUMP_BTCOEX(_s, _val) \ 468 do { \ 469 len += snprintf(buf + len, size - len, \ 470 "%20s : %10d\n", _s, (_val)); \ 471 } while (0) 472 473 enum bt_op_flags { 474 BT_OP_PRIORITY_DETECTED, 475 BT_OP_SCAN, 476 }; 477 478 struct ath_btcoex { 479 bool hw_timer_enabled; 480 spinlock_t btcoex_lock; 481 struct timer_list period_timer; /* Timer for BT period */ 482 u32 bt_priority_cnt; 483 unsigned long bt_priority_time; 484 unsigned long op_flags; 485 int bt_stomp_type; /* Types of BT stomping */ 486 u32 btcoex_no_stomp; /* in usec */ 487 u32 btcoex_period; /* in msec */ 488 u32 btscan_no_stomp; /* in usec */ 489 u32 duty_cycle; 490 u32 bt_wait_time; 491 int rssi_count; 492 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 493 struct ath_mci_profile mci; 494 u8 stomp_audio; 495 }; 496 497 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 498 int ath9k_init_btcoex(struct ath_softc *sc); 499 void ath9k_deinit_btcoex(struct ath_softc *sc); 500 void ath9k_start_btcoex(struct ath_softc *sc); 501 void ath9k_stop_btcoex(struct ath_softc *sc); 502 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 503 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 504 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 505 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 506 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 507 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); 508 #else 509 static inline int ath9k_init_btcoex(struct ath_softc *sc) 510 { 511 return 0; 512 } 513 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 514 { 515 } 516 static inline void ath9k_start_btcoex(struct ath_softc *sc) 517 { 518 } 519 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 520 { 521 } 522 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 523 u32 status) 524 { 525 } 526 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 527 u32 max_4ms_framelen) 528 { 529 return 0; 530 } 531 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 532 { 533 } 534 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) 535 { 536 return 0; 537 } 538 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 539 540 struct ath9k_wow_pattern { 541 u8 pattern_bytes[MAX_PATTERN_SIZE]; 542 u8 mask_bytes[MAX_PATTERN_SIZE]; 543 u32 pattern_len; 544 }; 545 546 /********************/ 547 /* LED Control */ 548 /********************/ 549 550 #define ATH_LED_PIN_DEF 1 551 #define ATH_LED_PIN_9287 8 552 #define ATH_LED_PIN_9300 10 553 #define ATH_LED_PIN_9485 6 554 #define ATH_LED_PIN_9462 4 555 556 #ifdef CONFIG_MAC80211_LEDS 557 void ath_init_leds(struct ath_softc *sc); 558 void ath_deinit_leds(struct ath_softc *sc); 559 void ath_fill_led_pin(struct ath_softc *sc); 560 #else 561 static inline void ath_init_leds(struct ath_softc *sc) 562 { 563 } 564 565 static inline void ath_deinit_leds(struct ath_softc *sc) 566 { 567 } 568 static inline void ath_fill_led_pin(struct ath_softc *sc) 569 { 570 } 571 #endif 572 573 /*******************************/ 574 /* Antenna diversity/combining */ 575 /*******************************/ 576 577 #define ATH_ANT_RX_CURRENT_SHIFT 4 578 #define ATH_ANT_RX_MAIN_SHIFT 2 579 #define ATH_ANT_RX_MASK 0x3 580 581 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 582 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 583 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 584 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 585 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 586 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 587 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 588 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 589 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 590 591 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 592 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 593 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 594 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 595 596 struct ath_ant_comb { 597 u16 count; 598 u16 total_pkt_count; 599 bool scan; 600 bool scan_not_start; 601 int main_total_rssi; 602 int alt_total_rssi; 603 int alt_recv_cnt; 604 int main_recv_cnt; 605 int rssi_lna1; 606 int rssi_lna2; 607 int rssi_add; 608 int rssi_sub; 609 int rssi_first; 610 int rssi_second; 611 int rssi_third; 612 int ant_ratio; 613 int ant_ratio2; 614 bool alt_good; 615 int quick_scan_cnt; 616 enum ath9k_ant_div_comb_lna_conf main_conf; 617 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 618 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 619 bool first_ratio; 620 bool second_ratio; 621 unsigned long scan_start_time; 622 623 /* 624 * Card-specific config values. 625 */ 626 int low_rssi_thresh; 627 int fast_div_bias; 628 }; 629 630 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 631 void ath_ant_comb_update(struct ath_softc *sc); 632 633 /********************/ 634 /* Main driver core */ 635 /********************/ 636 637 #define ATH9K_PCI_CUS198 0x0001 638 #define ATH9K_PCI_CUS230 0x0002 639 #define ATH9K_PCI_CUS217 0x0004 640 #define ATH9K_PCI_WOW 0x0008 641 642 /* 643 * Default cache line size, in bytes. 644 * Used when PCI device not fully initialized by bootrom/BIOS 645 */ 646 #define DEFAULT_CACHELINE 32 647 #define ATH_REGCLASSIDS_MAX 10 648 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 649 #define ATH_MAX_SW_RETRIES 30 650 #define ATH_CHAN_MAX 255 651 652 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 653 #define ATH_RATE_DUMMY_MARKER 0 654 655 enum sc_op_flags { 656 SC_OP_INVALID, 657 SC_OP_BEACONS, 658 SC_OP_ANI_RUN, 659 SC_OP_PRIM_STA_VIF, 660 SC_OP_HW_RESET, 661 SC_OP_SCANNING, 662 }; 663 664 /* Powersave flags */ 665 #define PS_WAIT_FOR_BEACON BIT(0) 666 #define PS_WAIT_FOR_CAB BIT(1) 667 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 668 #define PS_WAIT_FOR_TX_ACK BIT(3) 669 #define PS_BEACON_SYNC BIT(4) 670 #define PS_WAIT_FOR_ANI BIT(5) 671 672 struct ath_rate_table; 673 674 struct ath9k_vif_iter_data { 675 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ 676 u8 mask[ETH_ALEN]; /* bssid mask */ 677 bool has_hw_macaddr; 678 679 int naps; /* number of AP vifs */ 680 int nmeshes; /* number of mesh vifs */ 681 int nstations; /* number of station vifs */ 682 int nwds; /* number of WDS vifs */ 683 int nadhocs; /* number of adhoc vifs */ 684 }; 685 686 /* enum spectral_mode: 687 * 688 * @SPECTRAL_DISABLED: spectral mode is disabled 689 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with 690 * something else. 691 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples 692 * is performed manually. 693 * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels 694 * during a channel scan. 695 */ 696 enum spectral_mode { 697 SPECTRAL_DISABLED = 0, 698 SPECTRAL_BACKGROUND, 699 SPECTRAL_MANUAL, 700 SPECTRAL_CHANSCAN, 701 }; 702 703 struct ath_softc { 704 struct ieee80211_hw *hw; 705 struct device *dev; 706 707 struct survey_info *cur_survey; 708 struct survey_info survey[ATH9K_NUM_CHANNELS]; 709 710 struct tasklet_struct intr_tq; 711 struct tasklet_struct bcon_tasklet; 712 struct ath_hw *sc_ah; 713 void __iomem *mem; 714 int irq; 715 spinlock_t sc_serial_rw; 716 spinlock_t sc_pm_lock; 717 spinlock_t sc_pcu_lock; 718 struct mutex mutex; 719 struct work_struct paprd_work; 720 struct work_struct hw_check_work; 721 struct work_struct hw_reset_work; 722 struct completion paprd_complete; 723 724 unsigned int hw_busy_count; 725 unsigned long sc_flags; 726 unsigned long driver_data; 727 728 u32 intrstatus; 729 u16 ps_flags; /* PS_* */ 730 u16 curtxpow; 731 bool ps_enabled; 732 bool ps_idle; 733 short nbcnvifs; 734 short nvifs; 735 unsigned long ps_usecount; 736 737 struct ath_config config; 738 struct ath_rx rx; 739 struct ath_tx tx; 740 struct ath_beacon beacon; 741 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 742 743 #ifdef CONFIG_MAC80211_LEDS 744 bool led_registered; 745 char led_name[32]; 746 struct led_classdev led_cdev; 747 #endif 748 749 struct ath9k_hw_cal_data caldata; 750 int last_rssi; 751 752 #ifdef CONFIG_ATH9K_DEBUGFS 753 struct ath9k_debug debug; 754 #endif 755 struct ath_beacon_config cur_beacon_conf; 756 struct delayed_work tx_complete_work; 757 struct delayed_work hw_pll_work; 758 struct timer_list rx_poll_timer; 759 760 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 761 struct ath_btcoex btcoex; 762 struct ath_mci_coex mci_coex; 763 struct work_struct mci_work; 764 #endif 765 766 struct ath_descdma txsdma; 767 768 struct ath_ant_comb ant_comb; 769 u8 ant_tx, ant_rx; 770 struct dfs_pattern_detector *dfs_detector; 771 u32 wow_enabled; 772 /* relay(fs) channel for spectral scan */ 773 struct rchan *rfs_chan_spec_scan; 774 enum spectral_mode spectral_mode; 775 struct ath_spec_scan spec_config; 776 777 #ifdef CONFIG_PM_SLEEP 778 atomic_t wow_got_bmiss_intr; 779 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 780 u32 wow_intr_before_sleep; 781 #endif 782 }; 783 784 #define SPECTRAL_SCAN_BITMASK 0x10 785 /* Radar info packet format, used for DFS and spectral formats. */ 786 struct ath_radar_info { 787 u8 pulse_length_pri; 788 u8 pulse_length_ext; 789 u8 pulse_bw_info; 790 } __packed; 791 792 /* The HT20 spectral data has 4 bytes of additional information at it's end. 793 * 794 * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]} 795 * [7:0]: all bins max_magnitude[9:2] 796 * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]} 797 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) 798 */ 799 struct ath_ht20_mag_info { 800 u8 all_bins[3]; 801 u8 max_exp; 802 } __packed; 803 804 #define SPECTRAL_HT20_NUM_BINS 56 805 806 /* WARNING: don't actually use this struct! MAC may vary the amount of 807 * data by -1/+2. This struct is for reference only. 808 */ 809 struct ath_ht20_fft_packet { 810 u8 data[SPECTRAL_HT20_NUM_BINS]; 811 struct ath_ht20_mag_info mag_info; 812 struct ath_radar_info radar_info; 813 } __packed; 814 815 #define SPECTRAL_HT20_TOTAL_DATA_LEN (sizeof(struct ath_ht20_fft_packet)) 816 817 /* Dynamic 20/40 mode: 818 * 819 * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]} 820 * [7:0]: lower bins max_magnitude[9:2] 821 * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]} 822 * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]} 823 * [7:0]: upper bins max_magnitude[9:2] 824 * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]} 825 * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned) 826 */ 827 struct ath_ht20_40_mag_info { 828 u8 lower_bins[3]; 829 u8 upper_bins[3]; 830 u8 max_exp; 831 } __packed; 832 833 #define SPECTRAL_HT20_40_NUM_BINS 128 834 835 /* WARNING: don't actually use this struct! MAC may vary the amount of 836 * data. This struct is for reference only. 837 */ 838 struct ath_ht20_40_fft_packet { 839 u8 data[SPECTRAL_HT20_40_NUM_BINS]; 840 struct ath_ht20_40_mag_info mag_info; 841 struct ath_radar_info radar_info; 842 } __packed; 843 844 845 #define SPECTRAL_HT20_40_TOTAL_DATA_LEN (sizeof(struct ath_ht20_40_fft_packet)) 846 847 /* grabs the max magnitude from the all/upper/lower bins */ 848 static inline u16 spectral_max_magnitude(u8 *bins) 849 { 850 return (bins[0] & 0xc0) >> 6 | 851 (bins[1] & 0xff) << 2 | 852 (bins[2] & 0x03) << 10; 853 } 854 855 /* return the max magnitude from the all/upper/lower bins */ 856 static inline u8 spectral_max_index(u8 *bins) 857 { 858 s8 m = (bins[2] & 0xfc) >> 2; 859 860 /* TODO: this still doesn't always report the right values ... */ 861 if (m > 32) 862 m |= 0xe0; 863 else 864 m &= ~0xe0; 865 866 return m + 29; 867 } 868 869 /* return the bitmap weight from the all/upper/lower bins */ 870 static inline u8 spectral_bitmap_weight(u8 *bins) 871 { 872 return bins[0] & 0x3f; 873 } 874 875 /* FFT sample format given to userspace via debugfs. 876 * 877 * Please keep the type/length at the front position and change 878 * other fields after adding another sample type 879 * 880 * TODO: this might need rework when switching to nl80211-based 881 * interface. 882 */ 883 enum ath_fft_sample_type { 884 ATH_FFT_SAMPLE_HT20 = 1, 885 }; 886 887 struct fft_sample_tlv { 888 u8 type; /* see ath_fft_sample */ 889 __be16 length; 890 /* type dependent data follows */ 891 } __packed; 892 893 struct fft_sample_ht20 { 894 struct fft_sample_tlv tlv; 895 896 u8 max_exp; 897 898 __be16 freq; 899 s8 rssi; 900 s8 noise; 901 902 __be16 max_magnitude; 903 u8 max_index; 904 u8 bitmap_weight; 905 906 __be64 tsf; 907 908 u8 data[SPECTRAL_HT20_NUM_BINS]; 909 } __packed; 910 911 void ath9k_tasklet(unsigned long data); 912 int ath_cabq_update(struct ath_softc *); 913 914 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 915 { 916 common->bus_ops->read_cachesize(common, csz); 917 } 918 919 extern struct ieee80211_ops ath9k_ops; 920 extern int ath9k_modparam_nohwcrypt; 921 extern int led_blink; 922 extern bool is_ath9k_unloaded; 923 924 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 925 irqreturn_t ath_isr(int irq, void *dev); 926 int ath9k_init_device(u16 devid, struct ath_softc *sc, 927 const struct ath_bus_ops *bus_ops); 928 void ath9k_deinit_device(struct ath_softc *sc); 929 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 930 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 931 932 bool ath9k_uses_beacons(int type); 933 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw); 934 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 935 enum spectral_mode spectral_mode); 936 937 938 #ifdef CONFIG_ATH9K_PCI 939 int ath_pci_init(void); 940 void ath_pci_exit(void); 941 #else 942 static inline int ath_pci_init(void) { return 0; }; 943 static inline void ath_pci_exit(void) {}; 944 #endif 945 946 #ifdef CONFIG_ATH9K_AHB 947 int ath_ahb_init(void); 948 void ath_ahb_exit(void); 949 #else 950 static inline int ath_ahb_init(void) { return 0; }; 951 static inline void ath_ahb_exit(void) {}; 952 #endif 953 954 void ath9k_ps_wakeup(struct ath_softc *sc); 955 void ath9k_ps_restore(struct ath_softc *sc); 956 957 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 958 959 void ath_start_rfkill_poll(struct ath_softc *sc); 960 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 961 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 962 struct ieee80211_vif *vif, 963 struct ath9k_vif_iter_data *iter_data); 964 965 #endif /* ATH9K_H */ 966