1 /*
2  * Copyright (c) 2010-2011 Atheros Communications, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef AR9003_PHY_H
18 #define AR9003_PHY_H
19 
20 /*
21  * Channel Register Map
22  */
23 #define AR_CHAN_BASE	0x9800
24 
25 #define AR_PHY_TIMING1      (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2      (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3      (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4      (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5      (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6      (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11     (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG     (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0    (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3  (AR_CHAN_BASE + 0xb0)
35 #define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 16
36 
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD    0x3FF00000
38 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S  20
39 
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
41 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
42 
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
44 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
45 
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
47 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
48 
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT         0x4000000
50 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S       26
51 
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM                         0x20000     /* bins move with freq offset */
53 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S                       17
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH            0x000000FF
55 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S          0
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI                        0x00000100
57 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S                      8
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL                          0x03FC0000
59 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S			18
60 
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN   0x20000000
62 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S         29
63 
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN   0x80000000
65 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S         31
66 
67 #define AR_PHY_FIND_SIG_LOW  (AR_CHAN_BASE + 0x20)
68 
69 #define AR_PHY_SFCORR           (AR_CHAN_BASE + 0x24)
70 #define AR_PHY_SFCORR_LOW       (AR_CHAN_BASE + 0x28)
71 #define AR_PHY_SFCORR_EXT       (AR_CHAN_BASE + 0x2c)
72 
73 #define AR_PHY_EXT_CCA              (AR_CHAN_BASE + 0x30)
74 #define AR_PHY_RADAR_0              (AR_CHAN_BASE + 0x34)
75 #define AR_PHY_RADAR_1              (AR_CHAN_BASE + 0x38)
76 #define AR_PHY_RADAR_EXT            (AR_CHAN_BASE + 0x3c)
77 #define AR_PHY_MULTICHAIN_CTRL      (AR_CHAN_BASE + 0x80)
78 #define AR_PHY_PERCHAIN_CSD         (AR_CHAN_BASE + 0x84)
79 
80 #define AR_PHY_TX_PHASE_RAMP_0      (AR_CHAN_BASE + 0xd0)
81 #define AR_PHY_ADC_GAIN_DC_CORR_0   (AR_CHAN_BASE + 0xd4)
82 #define AR_PHY_IQ_ADC_MEAS_0_B0     (AR_CHAN_BASE + 0xc0)
83 #define AR_PHY_IQ_ADC_MEAS_1_B0     (AR_CHAN_BASE + 0xc4)
84 #define AR_PHY_IQ_ADC_MEAS_2_B0     (AR_CHAN_BASE + 0xc8)
85 #define AR_PHY_IQ_ADC_MEAS_3_B0     (AR_CHAN_BASE + 0xcc)
86 
87 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
88 #define AR_PHY_TX_PHASE_RAMP_0_9300_10      (AR_CHAN_BASE + 0xd0 - 0x10)
89 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10   (AR_CHAN_BASE + 0xd4 - 0x10)
90 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10     (AR_CHAN_BASE + 0xc0 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10     (AR_CHAN_BASE + 0xc4 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10     (AR_CHAN_BASE + 0xc8 + 0x8)
93 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10     (AR_CHAN_BASE + 0xcc + 0x8)
94 
95 #define AR_PHY_TX_CRC               (AR_CHAN_BASE + 0xa0)
96 #define AR_PHY_TST_DAC_CONST        (AR_CHAN_BASE + 0xa4)
97 #define AR_PHY_SPUR_REPORT_0        (AR_CHAN_BASE + 0xa8)
98 #define AR_PHY_CHAN_INFO_TAB_0      (AR_CHAN_BASE + 0x300)
99 
100 /*
101  * Channel Field Definitions
102  */
103 #define AR_PHY_TIMING2_USE_FORCE_PPM    0x00001000
104 #define AR_PHY_TIMING2_FORCE_PPM_VAL    0x00000fff
105 #define AR_PHY_TIMING3_DSC_MAN      0xFFFE0000
106 #define AR_PHY_TIMING3_DSC_MAN_S    17
107 #define AR_PHY_TIMING3_DSC_EXP      0x0001E000
108 #define AR_PHY_TIMING3_DSC_EXP_S    13
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
110 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S   12
111 #define AR_PHY_TIMING4_DO_CAL    0x10000
112 
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK        0x10000000
114 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S      28
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK         0x20000000
116 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S       29
117 
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
119 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
121 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
122 
123 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
124 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
125 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW  0x00000001
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW    0x00003F00
127 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S  8
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW      0x001FC000
129 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S    14
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW      0x0FE00000
131 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S    21
132 #define AR_PHY_SFCORR_M2COUNT_THR    0x0000001F
133 #define AR_PHY_SFCORR_M2COUNT_THR_S  0
134 #define AR_PHY_SFCORR_M1_THRESH      0x00FE0000
135 #define AR_PHY_SFCORR_M1_THRESH_S    17
136 #define AR_PHY_SFCORR_M2_THRESH      0x7F000000
137 #define AR_PHY_SFCORR_M2_THRESH_S    24
138 #define AR_PHY_SFCORR_EXT_M1_THRESH       0x0000007F
139 #define AR_PHY_SFCORR_EXT_M1_THRESH_S     0
140 #define AR_PHY_SFCORR_EXT_M2_THRESH       0x00003F80
141 #define AR_PHY_SFCORR_EXT_M2_THRESH_S     7
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW   0x001FC000
143 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW   0x0FE00000
145 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
147 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
148 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S   28
149 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
150 #define AR_PHY_EXT_CCA_THRESH62_S       16
151 #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX    0x0000FF00
152 #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S  8
153 #define AR_PHY_EXT_MINCCA_PWR   0x01FF0000
154 #define AR_PHY_EXT_MINCCA_PWR_S 16
155 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
156 #define AR_PHY_EXT_CYCPWR_THR1_S 9
157 #define AR_PHY_TIMING5_CYCPWR_THR1  0x000000FE
158 #define AR_PHY_TIMING5_CYCPWR_THR1_S    1
159 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE  0x00000001
160 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S    0
161 #define AR_PHY_TIMING5_CYCPWR_THR1A  0x007F0000
162 #define AR_PHY_TIMING5_CYCPWR_THR1A_S    16
163 #define AR_PHY_TIMING5_RSSI_THR1A     (0x7F << 16)
164 #define AR_PHY_TIMING5_RSSI_THR1A_S   16
165 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
166 #define AR_PHY_RADAR_0_ENA  0x00000001
167 #define AR_PHY_RADAR_0_FFT_ENA  0x80000000
168 #define AR_PHY_RADAR_0_INBAND   0x0000003e
169 #define AR_PHY_RADAR_0_INBAND_S 1
170 #define AR_PHY_RADAR_0_PRSSI    0x00000FC0
171 #define AR_PHY_RADAR_0_PRSSI_S  6
172 #define AR_PHY_RADAR_0_HEIGHT   0x0003F000
173 #define AR_PHY_RADAR_0_HEIGHT_S 12
174 #define AR_PHY_RADAR_0_RRSSI    0x00FC0000
175 #define AR_PHY_RADAR_0_RRSSI_S  18
176 #define AR_PHY_RADAR_0_FIRPWR   0x7F000000
177 #define AR_PHY_RADAR_0_FIRPWR_S 24
178 #define AR_PHY_RADAR_1_RELPWR_ENA       0x00800000
179 #define AR_PHY_RADAR_1_USE_FIR128       0x00400000
180 #define AR_PHY_RADAR_1_RELPWR_THRESH    0x003F0000
181 #define AR_PHY_RADAR_1_RELPWR_THRESH_S  16
182 #define AR_PHY_RADAR_1_BLOCK_CHECK      0x00008000
183 #define AR_PHY_RADAR_1_MAX_RRSSI        0x00004000
184 #define AR_PHY_RADAR_1_RELSTEP_CHECK    0x00002000
185 #define AR_PHY_RADAR_1_RELSTEP_THRESH   0x00001F00
186 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
187 #define AR_PHY_RADAR_1_MAXLEN           0x000000FF
188 #define AR_PHY_RADAR_1_MAXLEN_S         0
189 #define AR_PHY_RADAR_EXT_ENA            0x00004000
190 #define AR_PHY_RADAR_DC_PWR_THRESH      0x007f8000
191 #define AR_PHY_RADAR_DC_PWR_THRESH_S    15
192 #define AR_PHY_RADAR_LB_DC_CAP          0x7f800000
193 #define AR_PHY_RADAR_LB_DC_CAP_S        23
194 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
195 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S   6
196 #define AR_PHY_FIND_SIG_LOW_FIRPWR      (0x7f << 12)
197 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S    12
198 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
199 #define AR_PHY_FIND_SIG_LOW_RELSTEP     0x1f
200 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S   0
201 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
202 #define AR_PHY_CHAN_INFO_TAB_S2_READ    0x00000008
203 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S           3
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S   0
206 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
207 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S   7
208 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE   0x00004000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF   0x003f8000
210 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
211 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF   0x1fc00000
212 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
213 
214 /*
215  * MRC Register Map
216  */
217 #define AR_MRC_BASE	0x9c00
218 
219 #define AR_PHY_TIMING_3A       (AR_MRC_BASE + 0x0)
220 #define AR_PHY_LDPC_CNTL1      (AR_MRC_BASE + 0x4)
221 #define AR_PHY_LDPC_CNTL2      (AR_MRC_BASE + 0x8)
222 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
223 #define AR_PHY_CHAN_SPUR_MASK  (AR_MRC_BASE + 0x10)
224 #define AR_PHY_SGI_DELTA       (AR_MRC_BASE + 0x14)
225 #define AR_PHY_ML_CNTL_1       (AR_MRC_BASE + 0x18)
226 #define AR_PHY_ML_CNTL_2       (AR_MRC_BASE + 0x1c)
227 #define AR_PHY_TST_ADC         (AR_MRC_BASE + 0x20)
228 
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A      0x00000FE0
230 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S    5
231 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A          0x1F
232 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S        0
233 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B      0x00FE0000
234 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S    17
235 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B          0x0001F000
236 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S        12
237 
238 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A        0x00000FE0
239 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S      5
240 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A            0x1F
241 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S		0
242 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B	0x00FE0000
243 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S	17
244 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B		0x0001F000
245 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S		12
246 
247 
248 /*
249  * MRC Feild Definitions
250  */
251 #define AR_PHY_SGI_DSC_MAN   0x0007FFF0
252 #define AR_PHY_SGI_DSC_MAN_S 4
253 #define AR_PHY_SGI_DSC_EXP   0x0000000F
254 #define AR_PHY_SGI_DSC_EXP_S 0
255 /*
256  * BBB Register Map
257  */
258 #define AR_BBB_BASE	0x9d00
259 
260 /*
261  * AGC Register Map
262  */
263 #define AR_AGC_BASE	0x9e00
264 
265 #define AR_PHY_SETTLING         (AR_AGC_BASE + 0x0)
266 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
267 #define AR_PHY_GAINS_MINOFF0    (AR_AGC_BASE + 0x8)
268 #define AR_PHY_DESIRED_SZ       (AR_AGC_BASE + 0xc)
269 #define AR_PHY_FIND_SIG         (AR_AGC_BASE + 0x10)
270 #define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
271 #define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
272 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
273 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
274 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
275 
276 /*
277  * Antenna Diversity  settings
278  */
279 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
280 #define AR_ANT_DIV_CTRL_ALL	0x7e000000
281 #define AR_ANT_DIV_CTRL_ALL_S	25
282 #define AR_ANT_DIV_ENABLE	0x1000000
283 #define AR_ANT_DIV_ENABLE_S	24
284 
285 
286 #define AR_PHY_ANT_FAST_DIV_BIAS                0x00007e00
287 #define AR_PHY_ANT_FAST_DIV_BIAS_S              9
288 #define AR_PHY_ANT_SW_RX_PROT                   0x00800000
289 #define AR_PHY_ANT_SW_RX_PROT_S                 23
290 #define AR_PHY_ANT_DIV_LNADIV                   0x01000000
291 #define AR_PHY_ANT_DIV_LNADIV_S                 24
292 #define AR_PHY_ANT_DIV_ALT_LNACONF              0x06000000
293 #define AR_PHY_ANT_DIV_ALT_LNACONF_S            25
294 #define AR_PHY_ANT_DIV_MAIN_LNACONF             0x18000000
295 #define AR_PHY_ANT_DIV_MAIN_LNACONF_S           27
296 #define AR_PHY_ANT_DIV_ALT_GAINTB               0x20000000
297 #define AR_PHY_ANT_DIV_ALT_GAINTB_S             29
298 #define AR_PHY_ANT_DIV_MAIN_GAINTB              0x40000000
299 #define AR_PHY_ANT_DIV_MAIN_GAINTB_S            30
300 
301 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
302 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
303 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
304 #define AR_PHY_RIFS_SRCH        (AR_AGC_BASE + 0x38)
305 #define AR_PHY_PEAK_DET_CTRL_1  (AR_AGC_BASE + 0x3c)
306 #define AR_PHY_PEAK_DET_CTRL_2  (AR_AGC_BASE + 0x40)
307 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
308 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
309 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
310 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
311 
312 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
313 #define AR_FAST_DIV_ENABLE	0x2000
314 #define AR_FAST_DIV_ENABLE_S	13
315 
316 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
317 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
318 
319 #define AR_PHY_CCK_SPUR_MIT     (AR_AGC_BASE + 0x1cc)
320 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR                           0x000001fe
321 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S                                  1
322 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE                        0x60000000
323 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S                              29
324 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT                        0x00000001
325 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S                               0
326 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ                           0x1ffffe00
327 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S                                  9
328 
329 #define AR_PHY_MRC_CCK_CTRL         (AR_AGC_BASE + 0x1d0)
330 #define AR_PHY_MRC_CCK_ENABLE       0x00000001
331 #define AR_PHY_MRC_CCK_ENABLE_S              0
332 #define AR_PHY_MRC_CCK_MUX_REG      0x00000002
333 #define AR_PHY_MRC_CCK_MUX_REG_S             1
334 
335 #define AR_PHY_RX_OCGAIN        (AR_AGC_BASE + 0x200)
336 
337 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ          -110
338 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ          -115
339 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ     -125
340 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ     -125
341 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
342 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
343 
344 #define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
345 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
346 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ     -60
347 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
348 #define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
349 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
350 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ     -60
351 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
352 
353 #define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
354 
355 #define AR9300_EXT_LNA_CTL_GPIO_AR9485 9
356 
357 /*
358  * AGC Field Definitions
359  */
360 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN    0x00FC0000
361 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S  18
362 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN     0x00003C00
363 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S   10
364 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN      0x0000001F
365 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S    0
366 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN     0x003E0000
367 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S   17
368 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN     0x0001F000
369 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S   12
370 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB         0x00000FC0
371 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S       6
372 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB         0x0000003F
373 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S       0
374 #define AR_PHY_RXGAIN_TXRX_ATTEN    0x0003F000
375 #define AR_PHY_RXGAIN_TXRX_ATTEN_S  12
376 #define AR_PHY_RXGAIN_TXRX_RF_MAX   0x007C0000
377 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
378 #define AR9280_PHY_RXGAIN_TXRX_ATTEN    0x00003F80
379 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S  7
380 #define AR9280_PHY_RXGAIN_TXRX_MARGIN   0x001FC000
381 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
382 #define AR_PHY_SETTLING_SWITCH  0x00003F80
383 #define AR_PHY_SETTLING_SWITCH_S    7
384 #define AR_PHY_DESIRED_SZ_ADC       0x000000FF
385 #define AR_PHY_DESIRED_SZ_ADC_S     0
386 #define AR_PHY_DESIRED_SZ_PGA       0x0000FF00
387 #define AR_PHY_DESIRED_SZ_PGA_S     8
388 #define AR_PHY_DESIRED_SZ_TOT_DES   0x0FF00000
389 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
390 #define AR_PHY_MINCCA_PWR       0x1FF00000
391 #define AR_PHY_MINCCA_PWR_S     20
392 #define AR_PHY_CCA_THRESH62     0x0007F000
393 #define AR_PHY_CCA_THRESH62_S   12
394 #define AR9280_PHY_MINCCA_PWR       0x1FF00000
395 #define AR9280_PHY_MINCCA_PWR_S     20
396 #define AR9280_PHY_CCA_THRESH62     0x000FF000
397 #define AR9280_PHY_CCA_THRESH62_S   12
398 #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
399 #define AR_PHY_EXT_CCA0_THRESH62_S  0
400 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
401 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
402 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
403 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
404 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
405 
406 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR  0x00000200
407 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S  9
408 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
409 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S   10
410 
411 #define AR_PHY_RIFS_INIT_DELAY         0x3ff0000
412 #define AR_PHY_AGC_QUICK_DROP       0x03c00000
413 #define AR_PHY_AGC_QUICK_DROP_S     22
414 #define AR_PHY_AGC_COARSE_LOW       0x00007F80
415 #define AR_PHY_AGC_COARSE_LOW_S     7
416 #define AR_PHY_AGC_COARSE_HIGH      0x003F8000
417 #define AR_PHY_AGC_COARSE_HIGH_S    15
418 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
419 #define AR_PHY_AGC_COARSE_PWR_CONST_S   0
420 #define AR_PHY_FIND_SIG_FIRSTEP  0x0003F000
421 #define AR_PHY_FIND_SIG_FIRSTEP_S        12
422 #define AR_PHY_FIND_SIG_FIRPWR   0x03FC0000
423 #define AR_PHY_FIND_SIG_FIRPWR_S         18
424 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT  25
425 #define AR_PHY_FIND_SIG_RELPWR   (0x1f << 6)
426 #define AR_PHY_FIND_SIG_RELPWR_S          6
427 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT  11
428 #define AR_PHY_FIND_SIG_RELSTEP        0x1f
429 #define AR_PHY_FIND_SIG_RELSTEP_S         0
430 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT  5
431 #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000
432 #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S 21
433 #define AR_PHY_RESTART_DIV_GC   0x001C0000
434 #define AR_PHY_RESTART_DIV_GC_S 18
435 #define AR_PHY_RESTART_ENA      0x01
436 #define AR_PHY_DC_RESTART_DIS   0x40000000
437 
438 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON       0xFF000000
439 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S     24
440 #define AR_PHY_TPC_OLPC_GAIN_DELTA              0x00FF0000
441 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S            16
442 
443 #define AR_PHY_TPC_6_ERROR_EST_MODE             0x03000000
444 #define AR_PHY_TPC_6_ERROR_EST_MODE_S           24
445 
446 /*
447  * SM Register Map
448  */
449 #define AR_SM_BASE	0xa200
450 
451 #define AR_PHY_D2_CHIP_ID        (AR_SM_BASE + 0x0)
452 #define AR_PHY_GEN_CTRL          (AR_SM_BASE + 0x4)
453 #define AR_PHY_MODE              (AR_SM_BASE + 0x8)
454 #define AR_PHY_ACTIVE            (AR_SM_BASE + 0xc)
455 #define AR_PHY_SPUR_MASK_A       (AR_SM_BASE + 0x20)
456 #define AR_PHY_SPUR_MASK_B       (AR_SM_BASE + 0x24)
457 #define AR_PHY_SPECTRAL_SCAN     (AR_SM_BASE + 0x28)
458 #define AR_PHY_RADAR_BW_FILTER   (AR_SM_BASE + 0x2c)
459 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
460 #define AR_PHY_MAX_RX_LEN        (AR_SM_BASE + 0x34)
461 #define AR_PHY_FRAME_CTL         (AR_SM_BASE + 0x38)
462 #define AR_PHY_RFBUS_REQ         (AR_SM_BASE + 0x3c)
463 #define AR_PHY_RFBUS_GRANT       (AR_SM_BASE + 0x40)
464 #define AR_PHY_RIFS              (AR_SM_BASE + 0x44)
465 #define AR_PHY_RX_CLR_DELAY      (AR_SM_BASE + 0x50)
466 #define AR_PHY_RX_DELAY          (AR_SM_BASE + 0x54)
467 
468 #define AR_PHY_XPA_TIMING_CTL    (AR_SM_BASE + 0x64)
469 #define AR_PHY_MISC_PA_CTL       (AR_SM_BASE + 0x80)
470 #define AR_PHY_SWITCH_CHAIN_0    (AR_SM_BASE + 0x84)
471 #define AR_PHY_SWITCH_COM        (AR_SM_BASE + 0x88)
472 #define AR_PHY_SWITCH_COM_2      (AR_SM_BASE + 0x8c)
473 #define AR_PHY_RX_CHAINMASK      (AR_SM_BASE + 0xa0)
474 #define AR_PHY_CAL_CHAINMASK     (AR_SM_BASE + 0xc0)
475 #define AR_PHY_CALMODE           (AR_SM_BASE + 0xc8)
476 #define AR_PHY_FCAL_1            (AR_SM_BASE + 0xcc)
477 #define AR_PHY_FCAL_2_0          (AR_SM_BASE + 0xd0)
478 #define AR_PHY_DFT_TONE_CTL_0    (AR_SM_BASE + 0xd4)
479 #define AR_PHY_CL_CAL_CTL        (AR_SM_BASE + 0xd8)
480 #define AR_PHY_CL_TAB_0          (AR_SM_BASE + 0x100)
481 #define AR_PHY_SYNTH_CONTROL     (AR_SM_BASE + 0x140)
482 #define AR_PHY_ADDAC_CLK_SEL     (AR_SM_BASE + 0x144)
483 #define AR_PHY_PLL_CTL           (AR_SM_BASE + 0x148)
484 #define AR_PHY_ANALOG_SWAP       (AR_SM_BASE + 0x14c)
485 #define AR_PHY_ADDAC_PARA_CTL    (AR_SM_BASE + 0x150)
486 #define AR_PHY_XPA_CFG           (AR_SM_BASE + 0x158)
487 
488 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW  3
489 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S    0
490 
491 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A           0x0001FC00
492 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S         10
493 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A                       0x3FF
494 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S                     0
495 
496 #define AR_PHY_TEST              (AR_SM_BASE + 0x160)
497 
498 #define AR_PHY_TEST_BBB_OBS_SEL       0x780000
499 #define AR_PHY_TEST_BBB_OBS_SEL_S     19
500 
501 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
502 #define AR_PHY_TEST_RX_OBS_SEL_BIT5   (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
503 
504 #define AR_PHY_TEST_CHAIN_SEL      0xC0000000
505 #define AR_PHY_TEST_CHAIN_SEL_S    30
506 
507 #define AR_PHY_TEST_CTL_STATUS   (AR_SM_BASE + 0x164)
508 #define AR_PHY_TEST_CTL_TSTDAC_EN         0x1
509 #define AR_PHY_TEST_CTL_TSTDAC_EN_S       0
510 #define AR_PHY_TEST_CTL_TX_OBS_SEL        0x1C
511 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S      2
512 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL    0x60
513 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S  5
514 #define AR_PHY_TEST_CTL_TSTADC_EN         0x100
515 #define AR_PHY_TEST_CTL_TSTADC_EN_S       8
516 #define AR_PHY_TEST_CTL_RX_OBS_SEL        0x3C00
517 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S      10
518 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL	  0xe0000000
519 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S	  29
520 
521 
522 #define AR_PHY_TSTDAC            (AR_SM_BASE + 0x168)
523 
524 #define AR_PHY_CHAN_STATUS       (AR_SM_BASE + 0x16c)
525 
526 #define AR_PHY_CHAN_INFO_MEMORY				(AR_SM_BASE + 0x170)
527 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ	0x00000008
528 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S	3
529 
530 #define AR_PHY_CHNINFO_NOISEPWR  (AR_SM_BASE + 0x174)
531 #define AR_PHY_CHNINFO_GAINDIFF  (AR_SM_BASE + 0x178)
532 #define AR_PHY_CHNINFO_FINETIM   (AR_SM_BASE + 0x17c)
533 #define AR_PHY_CHAN_INFO_GAIN_0  (AR_SM_BASE + 0x180)
534 #define AR_PHY_SCRAMBLER_SEED    (AR_SM_BASE + 0x190)
535 #define AR_PHY_CCK_TX_CTRL       (AR_SM_BASE + 0x194)
536 
537 #define AR_PHY_HEAVYCLIP_CTL     (AR_SM_BASE + 0x1a4)
538 #define AR_PHY_HEAVYCLIP_20      (AR_SM_BASE + 0x1a8)
539 #define AR_PHY_HEAVYCLIP_40      (AR_SM_BASE + 0x1ac)
540 #define AR_PHY_ILLEGAL_TXRATE    (AR_SM_BASE + 0x1b0)
541 
542 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
543 
544 #define AR_PHY_PWRTX_MAX         (AR_SM_BASE + 0x1f0)
545 #define AR_PHY_POWER_TX_SUB      (AR_SM_BASE + 0x1f4)
546 
547 #define AR_PHY_TPC_1				(AR_SM_BASE + 0x1f8)
548 #define AR_PHY_TPC_1_FORCED_DAC_GAIN		0x0000003e
549 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S		1
550 #define AR_PHY_TPC_1_FORCE_DAC_GAIN		0x00000001
551 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S		0
552 
553 #define AR_PHY_TPC_4_B0				(AR_SM_BASE + 0x204)
554 #define AR_PHY_TPC_5_B0				(AR_SM_BASE + 0x208)
555 #define AR_PHY_TPC_6_B0				(AR_SM_BASE + 0x20c)
556 
557 #define AR_PHY_TPC_11_B0			(AR_SM_BASE + 0x220)
558 #define AR_PHY_TPC_11_B1			(AR_SM1_BASE + 0x220)
559 #define AR_PHY_TPC_11_B2			(AR_SM2_BASE + 0x220)
560 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA		0x00ff0000
561 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S		16
562 
563 #define AR_PHY_TPC_12				(AR_SM_BASE + 0x224)
564 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5	0x3e000000
565 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S	25
566 
567 #define AR_PHY_TPC_18				(AR_SM_BASE + 0x23c)
568 #define AR_PHY_TPC_18_THERM_CAL_VALUE           0x000000ff
569 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S         0
570 #define AR_PHY_TPC_18_VOLT_CAL_VALUE		0x0000ff00
571 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S		8
572 
573 #define AR_PHY_TPC_19				(AR_SM_BASE + 0x240)
574 #define AR_PHY_TPC_19_ALPHA_VOLT		0x001f0000
575 #define AR_PHY_TPC_19_ALPHA_VOLT_S		16
576 #define AR_PHY_TPC_19_ALPHA_THERM		0xff
577 #define AR_PHY_TPC_19_ALPHA_THERM_S		0
578 
579 #define AR_PHY_TX_FORCED_GAIN				(AR_SM_BASE + 0x258)
580 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN		0x00000001
581 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S		0
582 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN	0x0000000e
583 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S	1
584 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN	0x00000030
585 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S	4
586 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN		0x000003c0
587 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S	6
588 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA		0x00003c00
589 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S		10
590 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB		0x0003c000
591 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S		14
592 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC		0x003c0000
593 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S		18
594 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND		0x00c00000
595 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S		22
596 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL		0x01000000
597 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S	24
598 
599 
600 #define AR_PHY_PDADC_TAB_0       (AR_SM_BASE + 0x280)
601 
602 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
603 
604 #define AR_PHY_TX_IQCAL_CONTROL_0   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
605 						 0x3c4 : 0x444))
606 #define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
607 						 0x3c8 : 0x448))
608 #define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + (AR_SREV_9485(ah) ? \
609 						 0x3c4 : 0x440))
610 #define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + (AR_SREV_9485(ah) ? \
611 						 0x3f0 : 0x48c))
612 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
613 					     (AR_SREV_9485(ah) ? \
614 					      0x3d0 : 0x450) + ((_i) << 2))
615 #define AR_PHY_RTT_CTRL			(AR_SM_BASE + 0x380)
616 
617 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
618 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
619 #define AR_PHY_WATCHDOG_CTL_2       (AR_SM_BASE + 0x5c8)
620 #define AR_PHY_WATCHDOG_CTL         (AR_SM_BASE + 0x5cc)
621 #define AR_PHY_ONLY_WARMRESET       (AR_SM_BASE + 0x5d0)
622 #define AR_PHY_ONLY_CTL             (AR_SM_BASE + 0x5d4)
623 #define AR_PHY_ECO_CTRL             (AR_SM_BASE + 0x5dc)
624 
625 #define AR_PHY_BB_THERM_ADC_1				(AR_SM_BASE + 0x248)
626 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM		0x000000ff
627 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S		0
628 
629 #define AR_PHY_BB_THERM_ADC_3				(AR_SM_BASE + 0x250)
630 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN	0x0001ff00
631 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S	8
632 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET		0x000000ff
633 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S	0
634 
635 #define AR_PHY_BB_THERM_ADC_4				(AR_SM_BASE + 0x254)
636 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE	0x000000ff
637 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S	0
638 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE		0x0000ff00
639 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S	8
640 
641 /* AIC Registers */
642 #define AR_PHY_AIC_CTRL_0_B0	(AR_SM_BASE + 0x4b0)
643 #define AR_PHY_AIC_CTRL_1_B0	(AR_SM_BASE + 0x4b4)
644 #define AR_PHY_AIC_CTRL_2_B0	(AR_SM_BASE + 0x4b8)
645 #define AR_PHY_AIC_CTRL_3_B0	(AR_SM_BASE + 0x4bc)
646 #define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + 0x4c4))
647 #define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + 0x4c8))
648 #define AR_PHY_AIC_CTRL_4_B0	(AR_SM_BASE + 0x4c0)
649 #define AR_PHY_AIC_STAT_2_B0	(AR_SM_BASE + 0x4cc)
650 
651 #define AR_PHY_65NM_CH0_TXRF3       0x16048
652 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G		0x0000001e
653 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S	1
654 
655 #define AR_PHY_65NM_CH0_SYNTH4      0x1608c
656 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
657 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
658 #define AR_PHY_65NM_CH0_SYNTH7      0x16098
659 #define AR_PHY_65NM_CH0_SYNTH12     0x160ac
660 #define AR_PHY_65NM_CH0_BIAS1       0x160c0
661 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
662 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
663 #define AR_PHY_65NM_CH0_RXTX2       0x16104
664 #define AR_PHY_65NM_CH1_RXTX2       0x16504
665 #define AR_PHY_65NM_CH2_RXTX2       0x16904
666 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
667 #define AR_PHY_65NM_CH1_RXTX4       0x1650c
668 #define AR_PHY_65NM_CH2_RXTX4       0x1690c
669 
670 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3           0x00780000
671 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S         19
672 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK         0x00000004
673 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S       2
674 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK        0x00000008
675 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S      3
676 
677 #define AR_CH0_TOP	(AR_SREV_9300(ah) ? 0x16288 : \
678 			 (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
679 #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
680 #define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
681 
682 #define AR_CH0_THERM	(AR_SREV_9300(ah) ? 0x16290 : \
683 				((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
684 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
685 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
686 #define AR_CH0_THERM_XPASHORT2GND 0x4
687 #define AR_CH0_THERM_XPASHORT2GND_S 2
688 
689 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
690 #define AR_SWITCH_TABLE_COM_ALL_S (0)
691 #define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
692 #define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
693 #define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)
694 #define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)
695 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
696 #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
697 #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
698 
699 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
700 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
701 
702 #define AR_SWITCH_TABLE_ALL (0xfff)
703 #define AR_SWITCH_TABLE_ALL_S (0)
704 
705 #define AR_PHY_65NM_CH0_THERM       (AR_SREV_9300(ah) ? 0x16290 :\
706 				     ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c))
707 
708 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
709 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
710 #define AR_PHY_65NM_CH0_THERM_START   0x20000000
711 #define AR_PHY_65NM_CH0_THERM_START_S 29
712 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT   0x0000ff00
713 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
714 
715 #define AR_CH0_TOP2		(AR_SREV_9300(ah) ? 0x1628c : \
716 					(AR_SREV_9462(ah) ? 0x16290 : 0x16284))
717 #define AR_CH0_TOP2_XPABIASLVL		0xf000
718 #define AR_CH0_TOP2_XPABIASLVL_S	12
719 
720 #define AR_CH0_XTAL		(AR_SREV_9300(ah) ? 0x16294 : \
721 				 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290))
722 #define AR_CH0_XTAL_CAPINDAC	0x7f000000
723 #define AR_CH0_XTAL_CAPINDAC_S	24
724 #define AR_CH0_XTAL_CAPOUTDAC	0x00fe0000
725 #define AR_CH0_XTAL_CAPOUTDAC_S	17
726 
727 #define AR_PHY_PMU1		((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40)
728 #define AR_PHY_PMU1_PWD		0x1
729 #define AR_PHY_PMU1_PWD_S	0
730 
731 #define AR_PHY_PMU2		((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44)
732 #define AR_PHY_PMU2_PGM		0x00200000
733 #define AR_PHY_PMU2_PGM_S	21
734 
735 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT		0x00380000
736 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S	19
737 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT		0x00c00000
738 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S	22
739 #define AR_PHY_LNAGAIN_LONG_SHIFT		0xe0000000
740 #define AR_PHY_LNAGAIN_LONG_SHIFT_S		29
741 #define AR_PHY_MXRGAIN_LONG_SHIFT		0x03000000
742 #define AR_PHY_MXRGAIN_LONG_SHIFT_S		24
743 #define AR_PHY_VGAGAIN_LONG_SHIFT		0x1c000000
744 #define AR_PHY_VGAGAIN_LONG_SHIFT_S		26
745 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT		0x00000001
746 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S		0
747 #define AR_PHY_MANRXGAIN_LONG_SHIFT		0x00000002
748 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S		1
749 
750 /*
751  * SM Field Definitions
752  */
753 #define AR_PHY_CL_CAL_ENABLE          0x00000002
754 #define AR_PHY_PARALLEL_CAL_ENABLE    0x00000001
755 #define AR_PHY_TPCRG1_PD_CAL_ENABLE   0x00400000
756 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
757 
758 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
759 
760 #define AR_PHY_FCAL20_CAP_STATUS_0    0x01f00000
761 #define AR_PHY_FCAL20_CAP_STATUS_0_S  20
762 
763 #define AR_PHY_RFBUS_REQ_EN     0x00000001  /* request for RF bus */
764 #define AR_PHY_RFBUS_GRANT_EN   0x00000001  /* RF bus granted */
765 #define AR_PHY_GC_TURBO_MODE       0x00000001  /* set turbo mode bits */
766 #define AR_PHY_GC_TURBO_SHORT      0x00000002  /* set short symbols to turbo mode setting */
767 #define AR_PHY_GC_DYN2040_EN       0x00000004  /* enable dyn 20/40 mode */
768 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008  /* dyn 20/40 - primary only */
769 #define AR_PHY_GC_DYN2040_PRI_CH   0x00000010  /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
770 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
771 #define AR_PHY_GC_DYN2040_EXT_CH   0x00000020  /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
772 #define AR_PHY_GC_HT_EN            0x00000040  /* ht enable */
773 #define AR_PHY_GC_SHORT_GI_40      0x00000080  /* allow short GI for HT 40 */
774 #define AR_PHY_GC_WALSH            0x00000100  /* walsh spatial spreading for 2 chains,2 streams TX */
775 #define AR_PHY_GC_SINGLE_HT_LTF1   0x00000200  /* single length (4us) 1st HT long training symbol */
776 #define AR_PHY_GC_GF_DETECT_EN     0x00000400  /* enable Green Field detection. Only affects rx, not tx */
777 #define AR_PHY_GC_ENABLE_DAC_FIFO  0x00000800  /* fifo between bb and dac */
778 #define AR_PHY_RX_DELAY_DELAY      0x00003FFF  /* delay from wakeup to rx ena */
779 
780 #define AR_PHY_CALMODE_IQ           0x00000000
781 #define AR_PHY_CALMODE_ADC_GAIN     0x00000001
782 #define AR_PHY_CALMODE_ADC_DC_PER   0x00000002
783 #define AR_PHY_CALMODE_ADC_DC_INIT  0x00000003
784 #define AR_PHY_SWAP_ALT_CHAIN       0x00000040
785 #define AR_PHY_MODE_OFDM            0x00000000
786 #define AR_PHY_MODE_CCK             0x00000001
787 #define AR_PHY_MODE_DYNAMIC         0x00000004
788 #define AR_PHY_MODE_DYNAMIC_S       2
789 #define AR_PHY_MODE_HALF            0x00000020
790 #define AR_PHY_MODE_QUARTER         0x00000040
791 #define AR_PHY_MAC_CLK_MODE         0x00000080
792 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
793 #define AR_PHY_MODE_SVD_HALF        0x00000200
794 #define AR_PHY_ACTIVE_EN    0x00000001
795 #define AR_PHY_ACTIVE_DIS   0x00000000
796 #define AR_PHY_FORCE_XPA_CFG    0x000000001
797 #define AR_PHY_FORCE_XPA_CFG_S  0
798 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF    0xFF000000
799 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S  24
800 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF    0x00FF0000
801 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S  16
802 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON      0x0000FF00
803 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S    8
804 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON      0x000000FF
805 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S    0
806 #define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
807 #define AR_PHY_TX_END_TO_A2_RX_ON_S     16
808 #define AR_PHY_TX_END_DATA_START  0x000000FF
809 #define AR_PHY_TX_END_DATA_START_S  0
810 #define AR_PHY_TX_END_PA_ON       0x0000FF00
811 #define AR_PHY_TX_END_PA_ON_S       8
812 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP   0x0000000F
813 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
814 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003F0
815 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
816 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000FC00
817 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
818 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003F0000
819 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
820 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0FC00000
821 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
822 #define AR_PHY_TPCRG1_NUM_PD_GAIN   0x0000c000
823 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
824 #define AR_PHY_TPCRG1_PD_GAIN_1    0x00030000
825 #define AR_PHY_TPCRG1_PD_GAIN_1_S  16
826 #define AR_PHY_TPCRG1_PD_GAIN_2    0x000C0000
827 #define AR_PHY_TPCRG1_PD_GAIN_2_S  18
828 #define AR_PHY_TPCRG1_PD_GAIN_3    0x00300000
829 #define AR_PHY_TPCRG1_PD_GAIN_3_S  20
830 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN   0x0000003e
831 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
832 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
833 #define AR_PHY_TXGAIN_FORCE               0x00000001
834 #define AR_PHY_TXGAIN_FORCE_S		  0
835 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
836 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
837 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
838 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S   14
839 #define AR_PHY_TXGAIN_FORCED_PADVGNRD     0x00c00000
840 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S   22
841 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN    0x000003c0
842 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S  6
843 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN  0x0000000e
844 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
845 
846 #define AR_PHY_POWER_TX_RATE1   0x9934
847 #define AR_PHY_POWER_TX_RATE2   0x9938
848 #define AR_PHY_POWER_TX_RATE_MAX    0x993c
849 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
850 #define PHY_AGC_CLR             0x10000000
851 #define RFSILENT_BB             0x00002000
852 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK          0xFFF
853 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT    0x800
854 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT         320
855 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK         0x0001
856 #define AR_PHY_RX_DELAY_DELAY   0x00003FFF
857 #define AR_PHY_CCK_TX_CTRL_JAPAN    0x00000010
858 
859 #define AR_PHY_SPECTRAL_SCAN_ENABLE           0x00000001
860 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S         0
861 #define AR_PHY_SPECTRAL_SCAN_ACTIVE           0x00000002
862 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S         1
863 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD       0x000000F0
864 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S     4
865 #define AR_PHY_SPECTRAL_SCAN_PERIOD           0x0000FF00
866 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S         8
867 #define AR_PHY_SPECTRAL_SCAN_COUNT            0x0FFF0000
868 #define AR_PHY_SPECTRAL_SCAN_COUNT_S          16
869 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT     0x10000000
870 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S   28
871 #define AR_PHY_SPECTRAL_SCAN_PRIORITY         0x20000000
872 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_S       29
873 #define AR_PHY_SPECTRAL_SCAN_USE_ERR5         0x40000000
874 #define AR_PHY_SPECTRAL_SCAN_USE_ERR5_S       30
875 #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT   0x80000000
876 #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S 31
877 
878 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR      0x00000004
879 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION     0x00000001
880 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S   0
881 #define AR_PHY_RTT_CTRL_RESTORE_MASK            0x0000007E
882 #define AR_PHY_RTT_CTRL_RESTORE_MASK_S          1
883 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE     0x00000080
884 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S   7
885 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS          0x00000001
886 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S        0
887 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE           0x00000002
888 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S         1
889 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR            0x0000001C
890 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S          2
891 #define AR_PHY_RTT_SW_RTT_TABLE_DATA            0xFFFFFFF0
892 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_S          4
893 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL                   0x80000000
894 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S                         31
895 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT             0x01fc0000
896 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S                   18
897 #define AR_PHY_TX_IQCAL_START_DO_CAL	    0x00000001
898 #define AR_PHY_TX_IQCAL_START_DO_CAL_S	    0
899 
900 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
901 #define AR_PHY_CALIBRATED_GAINS_0	 0x3e
902 #define AR_PHY_CALIBRATED_GAINS_0_S	 1
903 
904 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
905 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
906 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
907 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
908 
909 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
910 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
911 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR      0x20000000
912 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S    29
913 
914 #define AR_PHY_65NM_RXTX4_XLNA_BIAS		0xC0000000
915 #define AR_PHY_65NM_RXTX4_XLNA_BIAS_S		30
916 
917 /*
918  * Channel 1 Register Map
919  */
920 #define AR_CHAN1_BASE	0xa800
921 
922 #define AR_PHY_EXT_CCA_1            (AR_CHAN1_BASE + 0x30)
923 #define AR_PHY_TX_PHASE_RAMP_1      (AR_CHAN1_BASE + 0xd0)
924 #define AR_PHY_ADC_GAIN_DC_CORR_1   (AR_CHAN1_BASE + 0xd4)
925 
926 #define AR_PHY_SPUR_REPORT_1        (AR_CHAN1_BASE + 0xa8)
927 #define AR_PHY_CHAN_INFO_TAB_1      (AR_CHAN1_BASE + 0x300)
928 #define AR_PHY_RX_IQCAL_CORR_B1     (AR_CHAN1_BASE + 0xdc)
929 
930 /*
931  * Channel 1 Field Definitions
932  */
933 #define AR_PHY_CH1_EXT_MINCCA_PWR   0x01FF0000
934 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
935 
936 /*
937  * AGC 1 Register Map
938  */
939 #define AR_AGC1_BASE	0xae00
940 
941 #define AR_PHY_FORCEMAX_GAINS_1      (AR_AGC1_BASE + 0x4)
942 #define AR_PHY_EXT_ATTEN_CTL_1       (AR_AGC1_BASE + 0x18)
943 #define AR_PHY_CCA_1                 (AR_AGC1_BASE + 0x1c)
944 #define AR_PHY_CCA_CTRL_1            (AR_AGC1_BASE + 0x20)
945 #define AR_PHY_RSSI_1                (AR_AGC1_BASE + 0x180)
946 #define AR_PHY_SPUR_CCK_REP_1        (AR_AGC1_BASE + 0x184)
947 #define AR_PHY_RX_OCGAIN_2           (AR_AGC1_BASE + 0x200)
948 
949 /*
950  * AGC 1 Field Definitions
951  */
952 #define AR_PHY_CH1_MINCCA_PWR   0x1FF00000
953 #define AR_PHY_CH1_MINCCA_PWR_S 20
954 
955 /*
956  * SM 1 Register Map
957  */
958 #define AR_SM1_BASE	0xb200
959 
960 #define AR_PHY_SWITCH_CHAIN_1   (AR_SM1_BASE + 0x84)
961 #define AR_PHY_FCAL_2_1         (AR_SM1_BASE + 0xd0)
962 #define AR_PHY_DFT_TONE_CTL_1   (AR_SM1_BASE + 0xd4)
963 #define AR_PHY_CL_TAB_1         (AR_SM1_BASE + 0x100)
964 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
965 #define AR_PHY_TPC_4_B1         (AR_SM1_BASE + 0x204)
966 #define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
967 #define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
968 #define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
969 #define AR_PHY_PDADC_TAB_1	(AR_SM1_BASE + (AR_SREV_9462_20_OR_LATER(ah) ? \
970 					0x280 : 0x240))
971 #define AR_PHY_TPC_19_B1	(AR_SM1_BASE + 0x240)
972 #define AR_PHY_TPC_19_B1_ALPHA_THERM		0xff
973 #define AR_PHY_TPC_19_B1_ALPHA_THERM_S		0
974 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
975 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM1_BASE + 0x450 + ((_i) << 2))
976 
977 /* SM 1 AIC Registers */
978 
979 #define AR_PHY_AIC_CTRL_0_B1	(AR_SM1_BASE + 0x4b0)
980 #define AR_PHY_AIC_CTRL_1_B1	(AR_SM1_BASE + 0x4b4)
981 #define AR_PHY_AIC_CTRL_2_B1	(AR_SM1_BASE + 0x4b8)
982 #define AR_PHY_AIC_STAT_0_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
983 					0x4c0 : 0x4c4))
984 #define AR_PHY_AIC_STAT_1_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
985 					0x4c4 : 0x4c8))
986 #define AR_PHY_AIC_CTRL_4_B1	(AR_SM1_BASE + 0x4c0)
987 #define AR_PHY_AIC_STAT_2_B1	(AR_SM1_BASE + 0x4cc)
988 
989 #define AR_PHY_AIC_SRAM_ADDR_B1	(AR_SM1_BASE + 0x5f0)
990 #define AR_PHY_AIC_SRAM_DATA_B1	(AR_SM1_BASE + 0x5f4)
991 
992 #define AR_PHY_RTT_TABLE_SW_INTF_B(i)	(0x384 + ((i) ? \
993 					AR_SM1_BASE : AR_SM_BASE))
994 #define AR_PHY_RTT_TABLE_SW_INTF_1_B(i)	(0x388 + ((i) ? \
995 					AR_SM1_BASE : AR_SM_BASE))
996 /*
997  * Channel 2 Register Map
998  */
999 #define AR_CHAN2_BASE	0xb800
1000 
1001 #define AR_PHY_EXT_CCA_2            (AR_CHAN2_BASE + 0x30)
1002 #define AR_PHY_TX_PHASE_RAMP_2      (AR_CHAN2_BASE + 0xd0)
1003 #define AR_PHY_ADC_GAIN_DC_CORR_2   (AR_CHAN2_BASE + 0xd4)
1004 
1005 #define AR_PHY_SPUR_REPORT_2        (AR_CHAN2_BASE + 0xa8)
1006 #define AR_PHY_CHAN_INFO_TAB_2      (AR_CHAN2_BASE + 0x300)
1007 #define AR_PHY_RX_IQCAL_CORR_B2     (AR_CHAN2_BASE + 0xdc)
1008 
1009 /*
1010  * Channel 2 Field Definitions
1011  */
1012 #define AR_PHY_CH2_EXT_MINCCA_PWR   0x01FF0000
1013 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
1014 /*
1015  * AGC 2 Register Map
1016  */
1017 #define AR_AGC2_BASE	0xbe00
1018 
1019 #define AR_PHY_FORCEMAX_GAINS_2      (AR_AGC2_BASE + 0x4)
1020 #define AR_PHY_EXT_ATTEN_CTL_2       (AR_AGC2_BASE + 0x18)
1021 #define AR_PHY_CCA_2                 (AR_AGC2_BASE + 0x1c)
1022 #define AR_PHY_CCA_CTRL_2            (AR_AGC2_BASE + 0x20)
1023 #define AR_PHY_RSSI_2                (AR_AGC2_BASE + 0x180)
1024 
1025 /*
1026  * AGC 2 Field Definitions
1027  */
1028 #define AR_PHY_CH2_MINCCA_PWR   0x1FF00000
1029 #define AR_PHY_CH2_MINCCA_PWR_S 20
1030 
1031 /*
1032  * SM 2 Register Map
1033  */
1034 #define AR_SM2_BASE	0xc200
1035 
1036 #define AR_PHY_SWITCH_CHAIN_2    (AR_SM2_BASE + 0x84)
1037 #define AR_PHY_FCAL_2_2          (AR_SM2_BASE + 0xd0)
1038 #define AR_PHY_DFT_TONE_CTL_2    (AR_SM2_BASE + 0xd4)
1039 #define AR_PHY_CL_TAB_2          (AR_SM2_BASE + 0x100)
1040 #define AR_PHY_CHAN_INFO_GAIN_2  (AR_SM2_BASE + 0x180)
1041 #define AR_PHY_TPC_4_B2          (AR_SM2_BASE + 0x204)
1042 #define AR_PHY_TPC_5_B2          (AR_SM2_BASE + 0x208)
1043 #define AR_PHY_TPC_6_B2          (AR_SM2_BASE + 0x20c)
1044 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
1045 #define AR_PHY_TPC_19_B2         (AR_SM2_BASE + 0x240)
1046 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
1047 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
1048 
1049 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
1050 
1051 /*
1052  * AGC 3 Register Map
1053  */
1054 #define AR_AGC3_BASE	0xce00
1055 
1056 #define AR_PHY_RSSI_3            (AR_AGC3_BASE + 0x180)
1057 
1058 /* GLB Registers */
1059 #define AR_GLB_BASE	0x20000
1060 #define AR_GLB_GPIO_CONTROL	(AR_GLB_BASE)
1061 #define AR_PHY_GLB_CONTROL	(AR_GLB_BASE + 0x44)
1062 #define AR_GLB_SCRATCH(_ah)	(AR_GLB_BASE + \
1063 					(AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))
1064 #define AR_GLB_STATUS		(AR_GLB_BASE + 0x48)
1065 
1066 /*
1067  * Misc helper defines
1068  */
1069 #define AR_PHY_CHAIN_OFFSET     (AR_CHAN1_BASE - AR_CHAN_BASE)
1070 
1071 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1072 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1073 #define AR_PHY_SWITCH_CHAIN(_i)     (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1074 #define AR_PHY_EXT_ATTEN_CTL(_i)    (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1075 
1076 #define AR_PHY_RXGAIN(_i)           (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1077 #define AR_PHY_TPCRG5(_i)           (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1078 #define AR_PHY_PDADC_TAB(_i)        (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1079 
1080 #define AR_PHY_CAL_MEAS_0(_i)       (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1081 #define AR_PHY_CAL_MEAS_1(_i)       (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1082 #define AR_PHY_CAL_MEAS_2(_i)       (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1083 #define AR_PHY_CAL_MEAS_3(_i)       (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1084 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1085 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1086 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1087 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1088 
1089 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE    0x00000001
1090 #define AR_PHY_WATCHDOG_IDLE_ENABLE        0x00000002
1091 #define AR_PHY_WATCHDOG_IDLE_MASK          0xFFFF0000
1092 #define AR_PHY_WATCHDOG_NON_IDLE_MASK      0x0000FFFC
1093 
1094 #define AR_PHY_WATCHDOG_RST_ENABLE         0x00000002
1095 #define AR_PHY_WATCHDOG_IRQ_ENABLE         0x00000004
1096 #define AR_PHY_WATCHDOG_CNTL2_MASK         0xFFFFFFF9
1097 
1098 #define AR_PHY_WATCHDOG_INFO               0x00000007
1099 #define AR_PHY_WATCHDOG_INFO_S             0
1100 #define AR_PHY_WATCHDOG_DET_HANG           0x00000008
1101 #define AR_PHY_WATCHDOG_DET_HANG_S         3
1102 #define AR_PHY_WATCHDOG_RADAR_SM           0x000000F0
1103 #define AR_PHY_WATCHDOG_RADAR_SM_S         4
1104 #define AR_PHY_WATCHDOG_RX_OFDM_SM         0x00000F00
1105 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S       8
1106 #define AR_PHY_WATCHDOG_RX_CCK_SM          0x0000F000
1107 #define AR_PHY_WATCHDOG_RX_CCK_SM_S        12
1108 #define AR_PHY_WATCHDOG_TX_OFDM_SM         0x000F0000
1109 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S       16
1110 #define AR_PHY_WATCHDOG_TX_CCK_SM          0x00F00000
1111 #define AR_PHY_WATCHDOG_TX_CCK_SM_S        20
1112 #define AR_PHY_WATCHDOG_AGC_SM             0x0F000000
1113 #define AR_PHY_WATCHDOG_AGC_SM_S           24
1114 #define AR_PHY_WATCHDOG_SRCH_SM            0xF0000000
1115 #define AR_PHY_WATCHDOG_SRCH_SM_S          28
1116 
1117 #define AR_PHY_WATCHDOG_STATUS_CLR         0x00000008
1118 
1119 /*
1120  * PAPRD registers
1121  */
1122 #define AR_PHY_XPA_TIMING_CTL		(AR_SM_BASE + 0x64)
1123 
1124 #define AR_PHY_PAPRD_AM2AM		(AR_CHAN_BASE + 0xe4)
1125 #define AR_PHY_PAPRD_AM2AM_MASK		0x01ffffff
1126 #define AR_PHY_PAPRD_AM2AM_MASK_S	0
1127 
1128 #define AR_PHY_PAPRD_AM2PM		(AR_CHAN_BASE + 0xe8)
1129 #define AR_PHY_PAPRD_AM2PM_MASK		0x01ffffff
1130 #define AR_PHY_PAPRD_AM2PM_MASK_S	0
1131 
1132 #define AR_PHY_PAPRD_HT40		(AR_CHAN_BASE + 0xec)
1133 #define AR_PHY_PAPRD_HT40_MASK		0x01ffffff
1134 #define AR_PHY_PAPRD_HT40_MASK_S	0
1135 
1136 #define AR_PHY_PAPRD_CTRL0_B0				(AR_CHAN_BASE + 0xf0)
1137 #define AR_PHY_PAPRD_CTRL0_B1				(AR_CHAN1_BASE + 0xf0)
1138 #define AR_PHY_PAPRD_CTRL0_B2				(AR_CHAN2_BASE + 0xf0)
1139 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE			0x00000001
1140 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S		0
1141 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK	0x00000002
1142 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S	1
1143 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH		0xf8000000
1144 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S		27
1145 
1146 #define AR_PHY_PAPRD_CTRL1_B0				(AR_CHAN_BASE + 0xf4)
1147 #define AR_PHY_PAPRD_CTRL1_B1				(AR_CHAN1_BASE + 0xf4)
1148 #define AR_PHY_PAPRD_CTRL1_B2				(AR_CHAN2_BASE + 0xf4)
1149 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA		0x00000001
1150 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S	0
1151 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE	0x00000002
1152 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S	1
1153 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE	0x00000004
1154 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S	2
1155 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL	0x000001f8
1156 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S	3
1157 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK	0x0001fe00
1158 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S	9
1159 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT		0x0ffe0000
1160 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S	17
1161 
1162 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x580 : 0x490))
1163 
1164 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE	0x00000001
1165 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S	0
1166 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING	0x0000007e
1167 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S	1
1168 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE	0x00000100
1169 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S	8
1170 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE	0x00000200
1171 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S	9
1172 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE	0x00000400
1173 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S	10
1174 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE		0x00000800
1175 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S		11
1176 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP		0x0003f000
1177 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S		12
1178 
1179 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x584 : 0x494))
1180 
1181 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN	0xFFFFFFFF
1182 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S	0
1183 
1184 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x588 : 0x498))
1185 
1186 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE	0x0000003f
1187 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S	0
1188 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP		0x00000fc0
1189 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S	6
1190 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL	0x0001f000
1191 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S	12
1192 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES	0x000e0000
1193 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S	17
1194 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN	0x00f00000
1195 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S	20
1196 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN	0x0f000000
1197 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S	24
1198 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE	0x20000000
1199 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S	29
1200 
1201 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x58c : 0x49c))
1202 
1203 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES	0x03ff0000
1204 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S	16
1205 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA	0x0000f000
1206 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S	12
1207 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR		0x00000fff
1208 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S		0
1209 
1210 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0			(AR_CHAN_BASE + 0x100)
1211 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0			(AR_CHAN_BASE + 0x104)
1212 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0			(AR_CHAN_BASE + 0x108)
1213 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0			(AR_CHAN_BASE + 0x10c)
1214 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0			(AR_CHAN_BASE + 0x110)
1215 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0			(AR_CHAN_BASE + 0x114)
1216 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0			(AR_CHAN_BASE + 0x118)
1217 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0			(AR_CHAN_BASE + 0x11c)
1218 #define AR_PHY_PAPRD_PRE_POST_SCALING				0x3FFFF
1219 #define AR_PHY_PAPRD_PRE_POST_SCALING_S				0
1220 
1221 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x590 : 0x4a0))
1222 
1223 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE		0x00000001
1224 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S		0
1225 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE	0x00000002
1226 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S	1
1227 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR		0x00000004
1228 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S		2
1229 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE		0x00000008
1230 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S		3
1231 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX		0x000001f0
1232 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S		4
1233 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR		0x0001fe00
1234 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S		9
1235 
1236 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x594 : 0x4a4))
1237 
1238 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL		0x0000ffff
1239 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S		0
1240 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX		0x001f0000
1241 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S		16
1242 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX		0x00600000
1243 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S		21
1244 
1245 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x598 : 0x4a8))
1246 
1247 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT	0x000fffff
1248 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S	0
1249 
1250 #define AR_PHY_PAPRD_MEM_TAB_B0			(AR_CHAN_BASE + 0x120)
1251 #define AR_PHY_PAPRD_MEM_TAB_B1			(AR_CHAN1_BASE + 0x120)
1252 #define AR_PHY_PAPRD_MEM_TAB_B2			(AR_CHAN2_BASE + 0x120)
1253 
1254 #define AR_PHY_PA_GAIN123_B0			(AR_CHAN_BASE + 0xf8)
1255 #define AR_PHY_PA_GAIN123_B1			(AR_CHAN1_BASE + 0xf8)
1256 #define AR_PHY_PA_GAIN123_B2			(AR_CHAN2_BASE + 0xf8)
1257 #define AR_PHY_PA_GAIN123_PA_GAIN1		0x3FF
1258 #define AR_PHY_PA_GAIN123_PA_GAIN1_S		0
1259 
1260 #define AR_PHY_POWERTX_RATE5			(AR_SM_BASE + 0x1d0)
1261 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0	0x3F
1262 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S	0
1263 
1264 #define AR_PHY_POWERTX_RATE6			(AR_SM_BASE + 0x1d4)
1265 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5	0x3F00
1266 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S	8
1267 
1268 #define AR_PHY_POWERTX_RATE8			(AR_SM_BASE + 0x1dc)
1269 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5	0x3F00
1270 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S	8
1271 
1272 #define AR_PHY_CL_TAB_CL_GAIN_MOD		0x1f
1273 #define AR_PHY_CL_TAB_CL_GAIN_MOD_S		0
1274 
1275 #define AR_BTCOEX_WL_LNADIV                                0x1a64
1276 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD               0x00003FFF
1277 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S             0
1278 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY           0x00004000
1279 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S         14
1280 #define AR_BTCOEX_WL_LNADIV_FORCE_ON                       0x00008000
1281 #define AR_BTCOEX_WL_LNADIV_FORCE_ON_S                     15
1282 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION                    0x00030000
1283 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S                  16
1284 #define AR_BTCOEX_WL_LNADIV_MODE                           0x007c0000
1285 #define AR_BTCOEX_WL_LNADIV_MODE_S                         18
1286 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ    0x00800000
1287 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S  23
1288 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE       0x01000000
1289 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S     24
1290 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT   0x02000000
1291 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25
1292 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD          0xFC000000
1293 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S        26
1294 
1295 /* Manual Peak detector calibration */
1296 #define AR_PHY_65NM_BASE                               0x16000
1297 #define AR_PHY_65NM_RXRF_GAINSTAGES(i)                 (AR_PHY_65NM_BASE + \
1298 							(i * 0x400) + 0x8)
1299 #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE        0x80000000
1300 #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE_S      31
1301 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC        0x00000002
1302 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC_S      1
1303 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR     0x70000000
1304 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_S   28
1305 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR     0x03800000
1306 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_S   23
1307 
1308 #define AR_PHY_65NM_RXTX2(i)                           (AR_PHY_65NM_BASE + \
1309 							(i * 0x400) + 0x104)
1310 #define AR_PHY_65NM_RXTX2_RXON_OVR                     0x00001000
1311 #define AR_PHY_65NM_RXTX2_RXON_OVR_S                   12
1312 #define AR_PHY_65NM_RXTX2_RXON                         0x00000800
1313 #define AR_PHY_65NM_RXTX2_RXON_S                       11
1314 
1315 #define AR_PHY_65NM_RXRF_AGC(i)                        (AR_PHY_65NM_BASE + \
1316 							(i * 0x400) + 0xc)
1317 #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE              0x80000000
1318 #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE_S            31
1319 #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR                0x40000000
1320 #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR_S              30
1321 #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR               0x20000000
1322 #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR_S             29
1323 #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR           0x1E000000
1324 #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR_S         25
1325 #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR           0x00078000
1326 #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR_S         15
1327 #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR          0x01F80000
1328 #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR_S        19
1329 #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR          0x00007e00
1330 #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR_S        9
1331 #define AR_PHY_65NM_RXRF_AGC_AGC_OUT                   0x00000004
1332 #define AR_PHY_65NM_RXRF_AGC_AGC_OUT_S                 2
1333 
1334 #endif  /* AR9003_PHY_H */
1335