1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21 
22 #define AR9300_OFDM_RATES	8
23 #define AR9300_HT_SS_RATES	8
24 #define AR9300_HT_DS_RATES	8
25 #define AR9300_HT_TS_RATES	8
26 
27 #define AR9300_11NA_OFDM_SHIFT		0
28 #define AR9300_11NA_HT_SS_SHIFT		8
29 #define AR9300_11NA_HT_DS_SHIFT		16
30 #define AR9300_11NA_HT_TS_SHIFT		24
31 
32 #define AR9300_11NG_OFDM_SHIFT		4
33 #define AR9300_11NG_HT_SS_SHIFT		12
34 #define AR9300_11NG_HT_DS_SHIFT		20
35 #define AR9300_11NG_HT_TS_SHIFT		28
36 
37 static const int firstep_table[] =
38 /* level:  0   1   2   3   4   5   6   7   8  */
39 	{ -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
40 
41 static const int cycpwrThr1_table[] =
42 /* level:  0   1   2   3   4   5   6   7   8  */
43 	{ -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
44 
45 /*
46  * register values to turn OFDM weak signal detection OFF
47  */
48 static const int m1ThreshLow_off = 127;
49 static const int m2ThreshLow_off = 127;
50 static const int m1Thresh_off = 127;
51 static const int m2Thresh_off = 127;
52 static const int m2CountThr_off =  31;
53 static const int m2CountThrLow_off =  63;
54 static const int m1ThreshLowExt_off = 127;
55 static const int m2ThreshLowExt_off = 127;
56 static const int m1ThreshExt_off = 127;
57 static const int m2ThreshExt_off = 127;
58 
59 static const u8 ofdm2pwr[] = {
60 	ALL_TARGET_LEGACY_6_24,
61 	ALL_TARGET_LEGACY_6_24,
62 	ALL_TARGET_LEGACY_6_24,
63 	ALL_TARGET_LEGACY_6_24,
64 	ALL_TARGET_LEGACY_6_24,
65 	ALL_TARGET_LEGACY_36,
66 	ALL_TARGET_LEGACY_48,
67 	ALL_TARGET_LEGACY_54
68 };
69 
70 static const u8 mcs2pwr_ht20[] = {
71 	ALL_TARGET_HT20_0_8_16,
72 	ALL_TARGET_HT20_1_3_9_11_17_19,
73 	ALL_TARGET_HT20_1_3_9_11_17_19,
74 	ALL_TARGET_HT20_1_3_9_11_17_19,
75 	ALL_TARGET_HT20_4,
76 	ALL_TARGET_HT20_5,
77 	ALL_TARGET_HT20_6,
78 	ALL_TARGET_HT20_7,
79 	ALL_TARGET_HT20_0_8_16,
80 	ALL_TARGET_HT20_1_3_9_11_17_19,
81 	ALL_TARGET_HT20_1_3_9_11_17_19,
82 	ALL_TARGET_HT20_1_3_9_11_17_19,
83 	ALL_TARGET_HT20_12,
84 	ALL_TARGET_HT20_13,
85 	ALL_TARGET_HT20_14,
86 	ALL_TARGET_HT20_15,
87 	ALL_TARGET_HT20_0_8_16,
88 	ALL_TARGET_HT20_1_3_9_11_17_19,
89 	ALL_TARGET_HT20_1_3_9_11_17_19,
90 	ALL_TARGET_HT20_1_3_9_11_17_19,
91 	ALL_TARGET_HT20_20,
92 	ALL_TARGET_HT20_21,
93 	ALL_TARGET_HT20_22,
94 	ALL_TARGET_HT20_23
95 };
96 
97 static const u8 mcs2pwr_ht40[] = {
98 	ALL_TARGET_HT40_0_8_16,
99 	ALL_TARGET_HT40_1_3_9_11_17_19,
100 	ALL_TARGET_HT40_1_3_9_11_17_19,
101 	ALL_TARGET_HT40_1_3_9_11_17_19,
102 	ALL_TARGET_HT40_4,
103 	ALL_TARGET_HT40_5,
104 	ALL_TARGET_HT40_6,
105 	ALL_TARGET_HT40_7,
106 	ALL_TARGET_HT40_0_8_16,
107 	ALL_TARGET_HT40_1_3_9_11_17_19,
108 	ALL_TARGET_HT40_1_3_9_11_17_19,
109 	ALL_TARGET_HT40_1_3_9_11_17_19,
110 	ALL_TARGET_HT40_12,
111 	ALL_TARGET_HT40_13,
112 	ALL_TARGET_HT40_14,
113 	ALL_TARGET_HT40_15,
114 	ALL_TARGET_HT40_0_8_16,
115 	ALL_TARGET_HT40_1_3_9_11_17_19,
116 	ALL_TARGET_HT40_1_3_9_11_17_19,
117 	ALL_TARGET_HT40_1_3_9_11_17_19,
118 	ALL_TARGET_HT40_20,
119 	ALL_TARGET_HT40_21,
120 	ALL_TARGET_HT40_22,
121 	ALL_TARGET_HT40_23,
122 };
123 
124 /**
125  * ar9003_hw_set_channel - set channel on single-chip device
126  * @ah: atheros hardware structure
127  * @chan:
128  *
129  * This is the function to change channel on single-chip devices, that is
130  * for AR9300 family of chipsets.
131  *
132  * This function takes the channel value in MHz and sets
133  * hardware channel value. Assumes writes have been enabled to analog bus.
134  *
135  * Actual Expression,
136  *
137  * For 2GHz channel,
138  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
139  * (freq_ref = 40MHz)
140  *
141  * For 5GHz channel,
142  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
143  * (freq_ref = 40MHz/(24>>amodeRefSel))
144  *
145  * For 5GHz channels which are 5MHz spaced,
146  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
147  * (freq_ref = 40MHz)
148  */
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
150 {
151 	u16 bMode, fracMode = 0, aModeRefSel = 0;
152 	u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
153 	struct chan_centers centers;
154 	int loadSynthChannel;
155 
156 	ath9k_hw_get_channel_centers(ah, chan, &centers);
157 	freq = centers.synth_center;
158 
159 	if (freq < 4800) {     /* 2 GHz, fractional mode */
160 		if (AR_SREV_9330(ah)) {
161 			if (ah->is_clk_25mhz)
162 				div = 75;
163 			else
164 				div = 120;
165 
166 			channelSel = (freq * 4) / div;
167 			chan_frac = (((freq * 4) % div) * 0x20000) / div;
168 			channelSel = (channelSel << 17) | chan_frac;
169 		} else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
170 			/*
171 			 * freq_ref = 40 / (refdiva >> amoderefsel);
172 			 * where refdiva=1 and amoderefsel=0
173 			 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
174 			 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
175 			 */
176 			channelSel = (freq * 4) / 120;
177 			chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
178 			channelSel = (channelSel << 17) | chan_frac;
179 		} else if (AR_SREV_9340(ah)) {
180 			if (ah->is_clk_25mhz) {
181 				channelSel = (freq * 2) / 75;
182 				chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
183 				channelSel = (channelSel << 17) | chan_frac;
184 			} else {
185 				channelSel = CHANSEL_2G(freq) >> 1;
186 			}
187 		} else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
188 			   AR_SREV_9561(ah)) {
189 			if (ah->is_clk_25mhz)
190 				div = 75;
191 			else
192 				div = 120;
193 
194 			channelSel = (freq * 4) / div;
195 			chan_frac = (((freq * 4) % div) * 0x20000) / div;
196 			channelSel = (channelSel << 17) | chan_frac;
197 		} else {
198 			channelSel = CHANSEL_2G(freq);
199 		}
200 		/* Set to 2G mode */
201 		bMode = 1;
202 	} else {
203 		if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
204 		     AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
205 		    ah->is_clk_25mhz) {
206 			channelSel = freq / 75;
207 			chan_frac = ((freq % 75) * 0x20000) / 75;
208 			channelSel = (channelSel << 17) | chan_frac;
209 		} else {
210 			channelSel = CHANSEL_5G(freq);
211 			/* Doubler is ON, so, divide channelSel by 2. */
212 			channelSel >>= 1;
213 		}
214 		/* Set to 5G mode */
215 		bMode = 0;
216 	}
217 
218 	/* Enable fractional mode for all channels */
219 	fracMode = 1;
220 	aModeRefSel = 0;
221 	loadSynthChannel = 0;
222 
223 	reg32 = (bMode << 29);
224 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
225 
226 	/* Enable Long shift Select for Synthesizer */
227 	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
228 		      AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
229 
230 	/* Program Synth. setting */
231 	reg32 = (channelSel << 2) | (fracMode << 30) |
232 		(aModeRefSel << 28) | (loadSynthChannel << 31);
233 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
234 
235 	/* Toggle Load Synth channel bit */
236 	loadSynthChannel = 1;
237 	reg32 = (channelSel << 2) | (fracMode << 30) |
238 		(aModeRefSel << 28) | (loadSynthChannel << 31);
239 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
240 
241 	ah->curchan = chan;
242 
243 	return 0;
244 }
245 
246 /**
247  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
248  * @ah: atheros hardware structure
249  * @chan:
250  *
251  * For single-chip solutions. Converts to baseband spur frequency given the
252  * input channel frequency and compute register settings below.
253  *
254  * Spur mitigation for MRC CCK
255  */
256 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
257 					    struct ath9k_channel *chan)
258 {
259 	static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
260 	int cur_bb_spur, negative = 0, cck_spur_freq;
261 	int i;
262 	int range, max_spur_cnts, synth_freq;
263 	u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
264 
265 	/*
266 	 * Need to verify range +/- 10 MHz in control channel, otherwise spur
267 	 * is out-of-band and can be ignored.
268 	 */
269 
270 	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
271 	    AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
272 		if (spur_fbin_ptr[0] == 0) /* No spur */
273 			return;
274 		max_spur_cnts = 5;
275 		if (IS_CHAN_HT40(chan)) {
276 			range = 19;
277 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
278 					   AR_PHY_GC_DYN2040_PRI_CH) == 0)
279 				synth_freq = chan->channel + 10;
280 			else
281 				synth_freq = chan->channel - 10;
282 		} else {
283 			range = 10;
284 			synth_freq = chan->channel;
285 		}
286 	} else {
287 		range = AR_SREV_9462(ah) ? 5 : 10;
288 		max_spur_cnts = 4;
289 		synth_freq = chan->channel;
290 	}
291 
292 	for (i = 0; i < max_spur_cnts; i++) {
293 		if (AR_SREV_9462(ah) && (i == 0 || i == 3))
294 			continue;
295 
296 		negative = 0;
297 		if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
298 		    AR_SREV_9550(ah) || AR_SREV_9561(ah))
299 			cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
300 							 IS_CHAN_2GHZ(chan));
301 		else
302 			cur_bb_spur = spur_freq[i];
303 
304 		cur_bb_spur -= synth_freq;
305 		if (cur_bb_spur < 0) {
306 			negative = 1;
307 			cur_bb_spur = -cur_bb_spur;
308 		}
309 		if (cur_bb_spur < range) {
310 			cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
311 
312 			if (negative == 1)
313 				cck_spur_freq = -cck_spur_freq;
314 
315 			cck_spur_freq = cck_spur_freq & 0xfffff;
316 
317 			REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
318 				      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
319 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
320 				      AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
321 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
322 				      AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
323 				      0x2);
324 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
325 				      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
326 				      0x1);
327 			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
328 				      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
329 				      cck_spur_freq);
330 
331 			return;
332 		}
333 	}
334 
335 	REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
336 		      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
337 	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
338 		      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
339 	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
340 		      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
341 }
342 
343 /* Clean all spur register fields */
344 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
345 {
346 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
347 		      AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
348 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
349 		      AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
350 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
351 		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
352 	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
353 		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
354 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
355 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
356 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
357 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
358 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
359 		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
360 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
361 		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
362 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
363 		      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
364 
365 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
366 		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
367 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
368 		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
369 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
370 		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
371 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
372 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
373 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
374 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
375 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
376 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
377 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
378 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
379 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
380 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
381 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
382 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
383 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
384 		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
385 }
386 
387 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
388 				int freq_offset,
389 				int spur_freq_sd,
390 				int spur_delta_phase,
391 				int spur_subchannel_sd,
392 				int range,
393 				int synth_freq)
394 {
395 	int mask_index = 0;
396 
397 	/* OFDM Spur mitigation */
398 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
399 		 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
400 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
401 		      AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
402 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
403 		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
404 	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
405 		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
406 	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
407 		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
408 
409 	if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
410 		REG_RMW_FIELD(ah, AR_PHY_TIMING11,
411 			      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
412 
413 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
414 		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
415 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
416 		      AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
417 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
418 		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
419 
420 	if (!AR_SREV_9340(ah) &&
421 	    REG_READ_FIELD(ah, AR_PHY_MODE,
422 			   AR_PHY_MODE_DYNAMIC) == 0x1)
423 		REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
424 			      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
425 
426 	mask_index = (freq_offset << 4) / 5;
427 	if (mask_index < 0)
428 		mask_index = mask_index - 1;
429 
430 	mask_index = mask_index & 0x7f;
431 
432 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
433 		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
434 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
435 		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
436 	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
437 		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
438 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
439 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
440 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
441 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
442 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
443 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
444 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
445 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
446 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
447 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
448 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
449 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
450 	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
451 		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
452 }
453 
454 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
455 				     int freq_offset)
456 {
457 	int mask_index = 0;
458 
459 	mask_index = (freq_offset << 4) / 5;
460 	if (mask_index < 0)
461 		mask_index = mask_index - 1;
462 
463 	mask_index = mask_index & 0x7f;
464 
465 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
466 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
467 		      mask_index);
468 
469 	/* A == B */
470 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
471 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
472 		      mask_index);
473 
474 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
475 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
476 		      mask_index);
477 	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
478 		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
479 	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
480 		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
481 
482 	/* A == B */
483 	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
484 		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
485 }
486 
487 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
488 				     struct ath9k_channel *chan,
489 				     int freq_offset,
490 				     int range,
491 				     int synth_freq)
492 {
493 	int spur_freq_sd = 0;
494 	int spur_subchannel_sd = 0;
495 	int spur_delta_phase = 0;
496 
497 	if (IS_CHAN_HT40(chan)) {
498 		if (freq_offset < 0) {
499 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
500 					   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
501 				spur_subchannel_sd = 1;
502 			else
503 				spur_subchannel_sd = 0;
504 
505 			spur_freq_sd = ((freq_offset + 10) << 9) / 11;
506 
507 		} else {
508 			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
509 			    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
510 				spur_subchannel_sd = 0;
511 			else
512 				spur_subchannel_sd = 1;
513 
514 			spur_freq_sd = ((freq_offset - 10) << 9) / 11;
515 
516 		}
517 
518 		spur_delta_phase = (freq_offset << 17) / 5;
519 
520 	} else {
521 		spur_subchannel_sd = 0;
522 		spur_freq_sd = (freq_offset << 9) /11;
523 		spur_delta_phase = (freq_offset << 18) / 5;
524 	}
525 
526 	spur_freq_sd = spur_freq_sd & 0x3ff;
527 	spur_delta_phase = spur_delta_phase & 0xfffff;
528 
529 	ar9003_hw_spur_ofdm(ah,
530 			    freq_offset,
531 			    spur_freq_sd,
532 			    spur_delta_phase,
533 			    spur_subchannel_sd,
534 			    range, synth_freq);
535 }
536 
537 /* Spur mitigation for OFDM */
538 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
539 					 struct ath9k_channel *chan)
540 {
541 	int synth_freq;
542 	int range = 10;
543 	int freq_offset = 0;
544 	int mode;
545 	u8* spurChansPtr;
546 	unsigned int i;
547 	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
548 
549 	if (IS_CHAN_5GHZ(chan)) {
550 		spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
551 		mode = 0;
552 	}
553 	else {
554 		spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
555 		mode = 1;
556 	}
557 
558 	if (spurChansPtr[0] == 0)
559 		return; /* No spur in the mode */
560 
561 	if (IS_CHAN_HT40(chan)) {
562 		range = 19;
563 		if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
564 				   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
565 			synth_freq = chan->channel - 10;
566 		else
567 			synth_freq = chan->channel + 10;
568 	} else {
569 		range = 10;
570 		synth_freq = chan->channel;
571 	}
572 
573 	ar9003_hw_spur_ofdm_clear(ah);
574 
575 	for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
576 		freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
577 		freq_offset -= synth_freq;
578 		if (abs(freq_offset) < range) {
579 			ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
580 						 range, synth_freq);
581 
582 			if (AR_SREV_9565(ah) && (i < 4)) {
583 				freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
584 								 mode);
585 				freq_offset -= synth_freq;
586 				if (abs(freq_offset) < range)
587 					ar9003_hw_spur_ofdm_9565(ah, freq_offset);
588 			}
589 
590 			break;
591 		}
592 	}
593 }
594 
595 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
596 				    struct ath9k_channel *chan)
597 {
598 	if (!AR_SREV_9565(ah))
599 		ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
600 	ar9003_hw_spur_mitigate_ofdm(ah, chan);
601 }
602 
603 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
604 					     struct ath9k_channel *chan)
605 {
606 	u32 pll;
607 
608 	pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
609 
610 	if (chan && IS_CHAN_HALF_RATE(chan))
611 		pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
612 	else if (chan && IS_CHAN_QUARTER_RATE(chan))
613 		pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
614 
615 	pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
616 
617 	return pll;
618 }
619 
620 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
621 					 struct ath9k_channel *chan)
622 {
623 	u32 pll;
624 
625 	pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
626 
627 	if (chan && IS_CHAN_HALF_RATE(chan))
628 		pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
629 	else if (chan && IS_CHAN_QUARTER_RATE(chan))
630 		pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
631 
632 	pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
633 
634 	return pll;
635 }
636 
637 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
638 				       struct ath9k_channel *chan)
639 {
640 	u32 phymode;
641 	u32 enableDacFifo = 0;
642 
643 	enableDacFifo =
644 		(REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
645 
646 	/* Enable 11n HT, 20 MHz */
647 	phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
648 
649 	if (!AR_SREV_9561(ah))
650 		phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
651 
652 	/* Configure baseband for dynamic 20/40 operation */
653 	if (IS_CHAN_HT40(chan)) {
654 		phymode |= AR_PHY_GC_DYN2040_EN;
655 		/* Configure control (primary) channel at +-10MHz */
656 		if (IS_CHAN_HT40PLUS(chan))
657 			phymode |= AR_PHY_GC_DYN2040_PRI_CH;
658 
659 	}
660 
661 	/* make sure we preserve INI settings */
662 	phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
663 	/* turn off Green Field detection for STA for now */
664 	phymode &= ~AR_PHY_GC_GF_DETECT_EN;
665 
666 	REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
667 
668 	/* Configure MAC for 20/40 operation */
669 	ath9k_hw_set11nmac2040(ah, chan);
670 
671 	/* global transmit timeout (25 TUs default)*/
672 	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
673 	/* carrier sense timeout */
674 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
675 }
676 
677 static void ar9003_hw_init_bb(struct ath_hw *ah,
678 			      struct ath9k_channel *chan)
679 {
680 	u32 synthDelay;
681 
682 	/*
683 	 * Wait for the frequency synth to settle (synth goes on
684 	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
685 	 * Value is in 100ns increments.
686 	 */
687 	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
688 
689 	/* Activate the PHY (includes baseband activate + synthesizer on) */
690 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
691 	ath9k_hw_synth_delay(ah, chan, synthDelay);
692 }
693 
694 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
695 {
696 	if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
697 		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
698 			    AR_PHY_SWAP_ALT_CHAIN);
699 
700 	REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
701 	REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
702 
703 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
704 		tx = 3;
705 
706 	REG_WRITE(ah, AR_SELFGEN_MASK, tx);
707 }
708 
709 /*
710  * Override INI values with chip specific configuration.
711  */
712 static void ar9003_hw_override_ini(struct ath_hw *ah)
713 {
714 	u32 val;
715 
716 	/*
717 	 * Set the RX_ABORT and RX_DIS and clear it only after
718 	 * RXE is set for MAC. This prevents frames with
719 	 * corrupted descriptor status.
720 	 */
721 	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
722 
723 	/*
724 	 * For AR9280 and above, there is a new feature that allows
725 	 * Multicast search based on both MAC Address and Key ID. By default,
726 	 * this feature is enabled. But since the driver is not using this
727 	 * feature, we switch it off; otherwise multicast search based on
728 	 * MAC addr only will fail.
729 	 */
730 	val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
731 	val |= AR_AGG_WEP_ENABLE_FIX |
732 	       AR_AGG_WEP_ENABLE |
733 	       AR_PCU_MISC_MODE2_CFP_IGNORE;
734 	REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
735 
736 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
737 		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
738 			  AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
739 
740 		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
741 				   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
742 			ah->enabled_cals |= TX_IQ_CAL;
743 		else
744 			ah->enabled_cals &= ~TX_IQ_CAL;
745 
746 	}
747 
748 	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
749 		ah->enabled_cals |= TX_CL_CAL;
750 	else
751 		ah->enabled_cals &= ~TX_CL_CAL;
752 
753 	if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
754 	    AR_SREV_9561(ah)) {
755 		if (ah->is_clk_25mhz) {
756 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
757 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
758 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
759 		} else {
760 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
761 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
762 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
763 		}
764 		udelay(100);
765 	}
766 }
767 
768 static void ar9003_hw_prog_ini(struct ath_hw *ah,
769 			       struct ar5416IniArray *iniArr,
770 			       int column)
771 {
772 	unsigned int i, regWrites = 0;
773 
774 	/* New INI format: Array may be undefined (pre, core, post arrays) */
775 	if (!iniArr->ia_array)
776 		return;
777 
778 	/*
779 	 * New INI format: Pre, core, and post arrays for a given subsystem
780 	 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
781 	 * the array is non-modal and force the column to 1.
782 	 */
783 	if (column >= iniArr->ia_columns)
784 		column = 1;
785 
786 	for (i = 0; i < iniArr->ia_rows; i++) {
787 		u32 reg = INI_RA(iniArr, i, 0);
788 		u32 val = INI_RA(iniArr, i, column);
789 
790 		REG_WRITE(ah, reg, val);
791 
792 		DO_DELAY(regWrites);
793 	}
794 }
795 
796 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
797 					    struct ath9k_channel *chan)
798 {
799 	int ret;
800 
801 	if (IS_CHAN_2GHZ(chan)) {
802 		if (IS_CHAN_HT40(chan))
803 			return 7;
804 		else
805 			return 8;
806 	}
807 
808 	if (chan->channel <= 5350)
809 		ret = 1;
810 	else if ((chan->channel > 5350) && (chan->channel <= 5600))
811 		ret = 3;
812 	else
813 		ret = 5;
814 
815 	if (IS_CHAN_HT40(chan))
816 		ret++;
817 
818 	return ret;
819 }
820 
821 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
822 					    struct ath9k_channel *chan)
823 {
824 	if (IS_CHAN_2GHZ(chan)) {
825 		if (IS_CHAN_HT40(chan))
826 			return 1;
827 		else
828 			return 2;
829 	}
830 
831 	return 0;
832 }
833 
834 static void ar9003_doubler_fix(struct ath_hw *ah)
835 {
836 	if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
837 		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
838 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
839 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
840 		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
841 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
842 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
843 		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
844 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
845 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
846 
847 		udelay(200);
848 
849 		REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
850 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
851 		REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
852 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
853 		REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
854 			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
855 
856 		udelay(1);
857 
858 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
859 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
860 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
861 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
862 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
863 			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
864 
865 		udelay(200);
866 
867 		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
868 			      AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
869 
870 		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
871 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
872 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
873 		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
874 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
875 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
876 		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
877 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
878 			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
879 	}
880 }
881 
882 static int ar9003_hw_process_ini(struct ath_hw *ah,
883 				 struct ath9k_channel *chan)
884 {
885 	unsigned int regWrites = 0, i;
886 	u32 modesIndex;
887 
888 	if (IS_CHAN_5GHZ(chan))
889 		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
890 	else
891 		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
892 
893 	/*
894 	 * SOC, MAC, BB, RADIO initvals.
895 	 */
896 	for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
897 		ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
898 		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
899 		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
900 		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
901 		if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
902 			ar9003_hw_prog_ini(ah,
903 					   &ah->ini_radio_post_sys2ant,
904 					   modesIndex);
905 	}
906 
907 	ar9003_doubler_fix(ah);
908 
909 	/*
910 	 * RXGAIN initvals.
911 	 */
912 	REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
913 
914 	if (AR_SREV_9462_20_OR_LATER(ah)) {
915 		/*
916 		 * CUS217 mix LNA mode.
917 		 */
918 		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
919 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
920 					1, regWrites);
921 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
922 					modesIndex, regWrites);
923 		}
924 
925 		/*
926 		 * 5G-XLNA
927 		 */
928 		if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
929 		    (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
930 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
931 					modesIndex, regWrites);
932 		}
933 	}
934 
935 	if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
936 		REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
937 				regWrites);
938 
939 	if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
940 		REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
941 				modesIndex, regWrites);
942 	/*
943 	 * TXGAIN initvals.
944 	 */
945 	if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
946 		int modes_txgain_index = 1;
947 
948 		if (AR_SREV_9550(ah))
949 			modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
950 
951 		if (AR_SREV_9561(ah))
952 			modes_txgain_index =
953 				ar9561_hw_get_modes_txgain_index(ah, chan);
954 
955 		if (modes_txgain_index < 0)
956 			return -EINVAL;
957 
958 		REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
959 				regWrites);
960 	} else {
961 		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
962 	}
963 
964 	/*
965 	 * For 5GHz channels requiring Fast Clock, apply
966 	 * different modal values.
967 	 */
968 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
969 		REG_WRITE_ARRAY(&ah->iniModesFastClock,
970 				modesIndex, regWrites);
971 
972 	/*
973 	 * Clock frequency initvals.
974 	 */
975 	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
976 
977 	/*
978 	 * JAPAN regulatory.
979 	 */
980 	if (chan->channel == 2484) {
981 		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
982 
983 		if (AR_SREV_9531(ah))
984 			REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
985 				      AR_PHY_FLC_PWR_THRESH, 0);
986 	}
987 
988 	ah->modes_index = modesIndex;
989 	ar9003_hw_override_ini(ah);
990 	ar9003_hw_set_channel_regs(ah, chan);
991 	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
992 	ath9k_hw_apply_txpower(ah, chan, false);
993 
994 	return 0;
995 }
996 
997 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
998 				 struct ath9k_channel *chan)
999 {
1000 	u32 rfMode = 0;
1001 
1002 	if (chan == NULL)
1003 		return;
1004 
1005 	if (IS_CHAN_2GHZ(chan))
1006 		rfMode |= AR_PHY_MODE_DYNAMIC;
1007 	else
1008 		rfMode |= AR_PHY_MODE_OFDM;
1009 
1010 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1011 		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1012 
1013 	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1014 		REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1015 			      AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
1016 
1017 	REG_WRITE(ah, AR_PHY_MODE, rfMode);
1018 }
1019 
1020 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
1021 {
1022 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1023 }
1024 
1025 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1026 				      struct ath9k_channel *chan)
1027 {
1028 	u32 coef_scaled, ds_coef_exp, ds_coef_man;
1029 	u32 clockMhzScaled = 0x64000000;
1030 	struct chan_centers centers;
1031 
1032 	/*
1033 	 * half and quarter rate can divide the scaled clock by 2 or 4
1034 	 * scale for selected channel bandwidth
1035 	 */
1036 	if (IS_CHAN_HALF_RATE(chan))
1037 		clockMhzScaled = clockMhzScaled >> 1;
1038 	else if (IS_CHAN_QUARTER_RATE(chan))
1039 		clockMhzScaled = clockMhzScaled >> 2;
1040 
1041 	/*
1042 	 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1043 	 * scaled coef to provide precision for this floating calculation
1044 	 */
1045 	ath9k_hw_get_channel_centers(ah, chan, &centers);
1046 	coef_scaled = clockMhzScaled / centers.synth_center;
1047 
1048 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1049 				      &ds_coef_exp);
1050 
1051 	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1052 		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1053 	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1054 		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1055 
1056 	/*
1057 	 * For Short GI,
1058 	 * scaled coeff is 9/10 that of normal coeff
1059 	 */
1060 	coef_scaled = (9 * coef_scaled) / 10;
1061 
1062 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1063 				      &ds_coef_exp);
1064 
1065 	/* for short gi */
1066 	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1067 		      AR_PHY_SGI_DSC_MAN, ds_coef_man);
1068 	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1069 		      AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1070 }
1071 
1072 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1073 {
1074 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1075 	return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1076 			     AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1077 }
1078 
1079 /*
1080  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1081  * Read the phy active delay register. Value is in 100ns increments.
1082  */
1083 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1084 {
1085 	u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1086 
1087 	ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1088 
1089 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1090 }
1091 
1092 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1093 				  enum ath9k_ani_cmd cmd, int param)
1094 {
1095 	struct ath_common *common = ath9k_hw_common(ah);
1096 	struct ath9k_channel *chan = ah->curchan;
1097 	struct ar5416AniState *aniState = &ah->ani;
1098 	int m1ThreshLow, m2ThreshLow;
1099 	int m1Thresh, m2Thresh;
1100 	int m2CountThr, m2CountThrLow;
1101 	int m1ThreshLowExt, m2ThreshLowExt;
1102 	int m1ThreshExt, m2ThreshExt;
1103 	s32 value, value2;
1104 
1105 	switch (cmd & ah->ani_function) {
1106 	case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1107 		/*
1108 		 * on == 1 means ofdm weak signal detection is ON
1109 		 * on == 1 is the default, for less noise immunity
1110 		 *
1111 		 * on == 0 means ofdm weak signal detection is OFF
1112 		 * on == 0 means more noise imm
1113 		 */
1114 		u32 on = param ? 1 : 0;
1115 
1116 		if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1117 			goto skip_ws_det;
1118 
1119 		m1ThreshLow = on ?
1120 			aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1121 		m2ThreshLow = on ?
1122 			aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1123 		m1Thresh = on ?
1124 			aniState->iniDef.m1Thresh : m1Thresh_off;
1125 		m2Thresh = on ?
1126 			aniState->iniDef.m2Thresh : m2Thresh_off;
1127 		m2CountThr = on ?
1128 			aniState->iniDef.m2CountThr : m2CountThr_off;
1129 		m2CountThrLow = on ?
1130 			aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1131 		m1ThreshLowExt = on ?
1132 			aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1133 		m2ThreshLowExt = on ?
1134 			aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1135 		m1ThreshExt = on ?
1136 			aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1137 		m2ThreshExt = on ?
1138 			aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1139 
1140 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1141 			      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1142 			      m1ThreshLow);
1143 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1144 			      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1145 			      m2ThreshLow);
1146 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1147 			      AR_PHY_SFCORR_M1_THRESH,
1148 			      m1Thresh);
1149 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1150 			      AR_PHY_SFCORR_M2_THRESH,
1151 			      m2Thresh);
1152 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1153 			      AR_PHY_SFCORR_M2COUNT_THR,
1154 			      m2CountThr);
1155 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1156 			      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1157 			      m2CountThrLow);
1158 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1159 			      AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1160 			      m1ThreshLowExt);
1161 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1162 			      AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1163 			      m2ThreshLowExt);
1164 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1165 			      AR_PHY_SFCORR_EXT_M1_THRESH,
1166 			      m1ThreshExt);
1167 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1168 			      AR_PHY_SFCORR_EXT_M2_THRESH,
1169 			      m2ThreshExt);
1170 skip_ws_det:
1171 		if (on)
1172 			REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1173 				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1174 		else
1175 			REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1176 				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1177 
1178 		if (on != aniState->ofdmWeakSigDetect) {
1179 			ath_dbg(common, ANI,
1180 				"** ch %d: ofdm weak signal: %s=>%s\n",
1181 				chan->channel,
1182 				aniState->ofdmWeakSigDetect ?
1183 				"on" : "off",
1184 				on ? "on" : "off");
1185 			if (on)
1186 				ah->stats.ast_ani_ofdmon++;
1187 			else
1188 				ah->stats.ast_ani_ofdmoff++;
1189 			aniState->ofdmWeakSigDetect = on;
1190 		}
1191 		break;
1192 	}
1193 	case ATH9K_ANI_FIRSTEP_LEVEL:{
1194 		u32 level = param;
1195 
1196 		if (level >= ARRAY_SIZE(firstep_table)) {
1197 			ath_dbg(common, ANI,
1198 				"ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1199 				level, ARRAY_SIZE(firstep_table));
1200 			return false;
1201 		}
1202 
1203 		/*
1204 		 * make register setting relative to default
1205 		 * from INI file & cap value
1206 		 */
1207 		value = firstep_table[level] -
1208 			firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1209 			aniState->iniDef.firstep;
1210 		if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1211 			value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1212 		if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1213 			value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1214 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1215 			      AR_PHY_FIND_SIG_FIRSTEP,
1216 			      value);
1217 		/*
1218 		 * we need to set first step low register too
1219 		 * make register setting relative to default
1220 		 * from INI file & cap value
1221 		 */
1222 		value2 = firstep_table[level] -
1223 			 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1224 			 aniState->iniDef.firstepLow;
1225 		if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1226 			value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1227 		if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1228 			value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1229 
1230 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1231 			      AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1232 
1233 		if (level != aniState->firstepLevel) {
1234 			ath_dbg(common, ANI,
1235 				"** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1236 				chan->channel,
1237 				aniState->firstepLevel,
1238 				level,
1239 				ATH9K_ANI_FIRSTEP_LVL,
1240 				value,
1241 				aniState->iniDef.firstep);
1242 			ath_dbg(common, ANI,
1243 				"** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1244 				chan->channel,
1245 				aniState->firstepLevel,
1246 				level,
1247 				ATH9K_ANI_FIRSTEP_LVL,
1248 				value2,
1249 				aniState->iniDef.firstepLow);
1250 			if (level > aniState->firstepLevel)
1251 				ah->stats.ast_ani_stepup++;
1252 			else if (level < aniState->firstepLevel)
1253 				ah->stats.ast_ani_stepdown++;
1254 			aniState->firstepLevel = level;
1255 		}
1256 		break;
1257 	}
1258 	case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1259 		u32 level = param;
1260 
1261 		if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1262 			ath_dbg(common, ANI,
1263 				"ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1264 				level, ARRAY_SIZE(cycpwrThr1_table));
1265 			return false;
1266 		}
1267 		/*
1268 		 * make register setting relative to default
1269 		 * from INI file & cap value
1270 		 */
1271 		value = cycpwrThr1_table[level] -
1272 			cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1273 			aniState->iniDef.cycpwrThr1;
1274 		if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1275 			value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1276 		if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1277 			value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1278 		REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1279 			      AR_PHY_TIMING5_CYCPWR_THR1,
1280 			      value);
1281 
1282 		/*
1283 		 * set AR_PHY_EXT_CCA for extension channel
1284 		 * make register setting relative to default
1285 		 * from INI file & cap value
1286 		 */
1287 		value2 = cycpwrThr1_table[level] -
1288 			 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1289 			 aniState->iniDef.cycpwrThr1Ext;
1290 		if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1291 			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1292 		if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1293 			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1294 		REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1295 			      AR_PHY_EXT_CYCPWR_THR1, value2);
1296 
1297 		if (level != aniState->spurImmunityLevel) {
1298 			ath_dbg(common, ANI,
1299 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1300 				chan->channel,
1301 				aniState->spurImmunityLevel,
1302 				level,
1303 				ATH9K_ANI_SPUR_IMMUNE_LVL,
1304 				value,
1305 				aniState->iniDef.cycpwrThr1);
1306 			ath_dbg(common, ANI,
1307 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1308 				chan->channel,
1309 				aniState->spurImmunityLevel,
1310 				level,
1311 				ATH9K_ANI_SPUR_IMMUNE_LVL,
1312 				value2,
1313 				aniState->iniDef.cycpwrThr1Ext);
1314 			if (level > aniState->spurImmunityLevel)
1315 				ah->stats.ast_ani_spurup++;
1316 			else if (level < aniState->spurImmunityLevel)
1317 				ah->stats.ast_ani_spurdown++;
1318 			aniState->spurImmunityLevel = level;
1319 		}
1320 		break;
1321 	}
1322 	case ATH9K_ANI_MRC_CCK:{
1323 		/*
1324 		 * is_on == 1 means MRC CCK ON (default, less noise imm)
1325 		 * is_on == 0 means MRC CCK is OFF (more noise imm)
1326 		 */
1327 		bool is_on = param ? 1 : 0;
1328 
1329 		if (ah->caps.rx_chainmask == 1)
1330 			break;
1331 
1332 		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1333 			      AR_PHY_MRC_CCK_ENABLE, is_on);
1334 		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1335 			      AR_PHY_MRC_CCK_MUX_REG, is_on);
1336 		if (is_on != aniState->mrcCCK) {
1337 			ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1338 				chan->channel,
1339 				aniState->mrcCCK ? "on" : "off",
1340 				is_on ? "on" : "off");
1341 			if (is_on)
1342 				ah->stats.ast_ani_ccklow++;
1343 			else
1344 				ah->stats.ast_ani_cckhigh++;
1345 			aniState->mrcCCK = is_on;
1346 		}
1347 	break;
1348 	}
1349 	default:
1350 		ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1351 		return false;
1352 	}
1353 
1354 	ath_dbg(common, ANI,
1355 		"ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1356 		aniState->spurImmunityLevel,
1357 		aniState->ofdmWeakSigDetect ? "on" : "off",
1358 		aniState->firstepLevel,
1359 		aniState->mrcCCK ? "on" : "off",
1360 		aniState->listenTime,
1361 		aniState->ofdmPhyErrCount,
1362 		aniState->cckPhyErrCount);
1363 	return true;
1364 }
1365 
1366 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1367 			      int16_t nfarray[NUM_NF_READINGS])
1368 {
1369 #define AR_PHY_CH_MINCCA_PWR	0x1FF00000
1370 #define AR_PHY_CH_MINCCA_PWR_S	20
1371 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1372 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1373 
1374 	int16_t nf;
1375 	int i;
1376 
1377 	for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1378 		if (ah->rxchainmask & BIT(i)) {
1379 			nf = MS(REG_READ(ah, ah->nf_regs[i]),
1380 					 AR_PHY_CH_MINCCA_PWR);
1381 			nfarray[i] = sign_extend32(nf, 8);
1382 
1383 			if (IS_CHAN_HT40(ah->curchan)) {
1384 				u8 ext_idx = AR9300_MAX_CHAINS + i;
1385 
1386 				nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1387 						 AR_PHY_CH_EXT_MINCCA_PWR);
1388 				nfarray[ext_idx] = sign_extend32(nf, 8);
1389 			}
1390 		}
1391 	}
1392 }
1393 
1394 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1395 {
1396 	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1397 	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1398 	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1399 	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1400 	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1401 	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1402 
1403 	if (AR_SREV_9330(ah))
1404 		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1405 
1406 	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1407 		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1408 		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1409 		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1410 		ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1411 	}
1412 }
1413 
1414 /*
1415  * Initialize the ANI register values with default (ini) values.
1416  * This routine is called during a (full) hardware reset after
1417  * all the registers are initialised from the INI.
1418  */
1419 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1420 {
1421 	struct ar5416AniState *aniState;
1422 	struct ath_common *common = ath9k_hw_common(ah);
1423 	struct ath9k_channel *chan = ah->curchan;
1424 	struct ath9k_ani_default *iniDef;
1425 	u32 val;
1426 
1427 	aniState = &ah->ani;
1428 	iniDef = &aniState->iniDef;
1429 
1430 	ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1431 		ah->hw_version.macVersion,
1432 		ah->hw_version.macRev,
1433 		ah->opmode,
1434 		chan->channel);
1435 
1436 	val = REG_READ(ah, AR_PHY_SFCORR);
1437 	iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1438 	iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1439 	iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1440 
1441 	val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1442 	iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1443 	iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1444 	iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1445 
1446 	val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1447 	iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1448 	iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1449 	iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1450 	iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1451 	iniDef->firstep = REG_READ_FIELD(ah,
1452 					 AR_PHY_FIND_SIG,
1453 					 AR_PHY_FIND_SIG_FIRSTEP);
1454 	iniDef->firstepLow = REG_READ_FIELD(ah,
1455 					    AR_PHY_FIND_SIG_LOW,
1456 					    AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1457 	iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1458 					    AR_PHY_TIMING5,
1459 					    AR_PHY_TIMING5_CYCPWR_THR1);
1460 	iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1461 					       AR_PHY_EXT_CCA,
1462 					       AR_PHY_EXT_CYCPWR_THR1);
1463 
1464 	/* these levels just got reset to defaults by the INI */
1465 	aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1466 	aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1467 	aniState->ofdmWeakSigDetect = true;
1468 	aniState->mrcCCK = true;
1469 }
1470 
1471 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1472 				       struct ath_hw_radar_conf *conf)
1473 {
1474 	unsigned int regWrites = 0;
1475 	u32 radar_0 = 0, radar_1;
1476 
1477 	if (!conf) {
1478 		REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1479 		return;
1480 	}
1481 
1482 	radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1483 	radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1484 	radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1485 	radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1486 	radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1487 	radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1488 
1489 	radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1490 	radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1491 		     AR_PHY_RADAR_1_RELPWR_THRESH);
1492 	radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1493 	radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1494 	radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1495 	radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1496 	radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1497 
1498 	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1499 	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1500 	if (conf->ext_channel)
1501 		REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1502 	else
1503 		REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1504 
1505 	if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1506 		REG_WRITE_ARRAY(&ah->ini_dfs,
1507 				IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1508 	}
1509 }
1510 
1511 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1512 {
1513 	struct ath_hw_radar_conf *conf = &ah->radar_conf;
1514 
1515 	conf->fir_power = -28;
1516 	conf->radar_rssi = 0;
1517 	conf->pulse_height = 10;
1518 	conf->pulse_rssi = 15;
1519 	conf->pulse_inband = 8;
1520 	conf->pulse_maxlen = 255;
1521 	conf->pulse_inband_step = 12;
1522 	conf->radar_inband = 8;
1523 }
1524 
1525 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1526 					   struct ath_hw_antcomb_conf *antconf)
1527 {
1528 	u32 regval;
1529 
1530 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1531 	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1532 				  AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1533 	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1534 				 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1535 	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1536 				  AR_PHY_ANT_FAST_DIV_BIAS_S;
1537 
1538 	if (AR_SREV_9330_11(ah)) {
1539 		antconf->lna1_lna2_switch_delta = -1;
1540 		antconf->lna1_lna2_delta = -9;
1541 		antconf->div_group = 1;
1542 	} else if (AR_SREV_9485(ah)) {
1543 		antconf->lna1_lna2_switch_delta = -1;
1544 		antconf->lna1_lna2_delta = -9;
1545 		antconf->div_group = 2;
1546 	} else if (AR_SREV_9565(ah)) {
1547 		antconf->lna1_lna2_switch_delta = 3;
1548 		antconf->lna1_lna2_delta = -9;
1549 		antconf->div_group = 3;
1550 	} else {
1551 		antconf->lna1_lna2_switch_delta = -1;
1552 		antconf->lna1_lna2_delta = -3;
1553 		antconf->div_group = 0;
1554 	}
1555 }
1556 
1557 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1558 				   struct ath_hw_antcomb_conf *antconf)
1559 {
1560 	u32 regval;
1561 
1562 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1563 	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1564 		    AR_PHY_ANT_DIV_ALT_LNACONF |
1565 		    AR_PHY_ANT_FAST_DIV_BIAS |
1566 		    AR_PHY_ANT_DIV_MAIN_GAINTB |
1567 		    AR_PHY_ANT_DIV_ALT_GAINTB);
1568 	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1569 		   & AR_PHY_ANT_DIV_MAIN_LNACONF);
1570 	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1571 		   & AR_PHY_ANT_DIV_ALT_LNACONF);
1572 	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1573 		   & AR_PHY_ANT_FAST_DIV_BIAS);
1574 	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1575 		   & AR_PHY_ANT_DIV_MAIN_GAINTB);
1576 	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1577 		   & AR_PHY_ANT_DIV_ALT_GAINTB);
1578 
1579 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1580 }
1581 
1582 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1583 
1584 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1585 {
1586 	struct ath9k_hw_capabilities *pCap = &ah->caps;
1587 	u8 ant_div_ctl1;
1588 	u32 regval;
1589 
1590 	if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1591 		return;
1592 
1593 	if (AR_SREV_9485(ah)) {
1594 		regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1595 						 IS_CHAN_2GHZ(ah->curchan));
1596 		if (enable) {
1597 			regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1598 			regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1599 		}
1600 		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1601 			      AR_SWITCH_TABLE_COM2_ALL, regval);
1602 	}
1603 
1604 	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1605 
1606 	/*
1607 	 * Set MAIN/ALT LNA conf.
1608 	 * Set MAIN/ALT gain_tb.
1609 	 */
1610 	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1611 	regval &= (~AR_ANT_DIV_CTRL_ALL);
1612 	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1613 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1614 
1615 	if (AR_SREV_9485_11_OR_LATER(ah)) {
1616 		/*
1617 		 * Enable LNA diversity.
1618 		 */
1619 		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1620 		regval &= ~AR_PHY_ANT_DIV_LNADIV;
1621 		regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1622 		if (enable)
1623 			regval |= AR_ANT_DIV_ENABLE;
1624 
1625 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1626 
1627 		/*
1628 		 * Enable fast antenna diversity.
1629 		 */
1630 		regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1631 		regval &= ~AR_FAST_DIV_ENABLE;
1632 		regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1633 		if (enable)
1634 			regval |= AR_FAST_DIV_ENABLE;
1635 
1636 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1637 
1638 		if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1639 			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1640 			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1641 				     AR_PHY_ANT_DIV_ALT_LNACONF |
1642 				     AR_PHY_ANT_DIV_ALT_GAINTB |
1643 				     AR_PHY_ANT_DIV_MAIN_GAINTB));
1644 			/*
1645 			 * Set MAIN to LNA1 and ALT to LNA2 at the
1646 			 * beginning.
1647 			 */
1648 			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1649 				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1650 			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1651 				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1652 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1653 		}
1654 	} else if (AR_SREV_9565(ah)) {
1655 		if (enable) {
1656 			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1657 				    AR_ANT_DIV_ENABLE);
1658 			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1659 				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1660 			REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1661 				    AR_FAST_DIV_ENABLE);
1662 			REG_SET_BIT(ah, AR_PHY_RESTART,
1663 				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1664 			REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1665 				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1666 		} else {
1667 			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1668 				    AR_ANT_DIV_ENABLE);
1669 			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1670 				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1671 			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1672 				    AR_FAST_DIV_ENABLE);
1673 			REG_CLR_BIT(ah, AR_PHY_RESTART,
1674 				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1675 			REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1676 				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1677 
1678 			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1679 			regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1680 				    AR_PHY_ANT_DIV_ALT_LNACONF |
1681 				    AR_PHY_ANT_DIV_MAIN_GAINTB |
1682 				    AR_PHY_ANT_DIV_ALT_GAINTB);
1683 			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1684 				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1685 			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1686 				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1687 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1688 		}
1689 	}
1690 }
1691 
1692 #endif
1693 
1694 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1695 				      struct ath9k_channel *chan,
1696 				      u8 *ini_reloaded)
1697 {
1698 	unsigned int regWrites = 0;
1699 	u32 modesIndex, txgain_index;
1700 
1701 	if (IS_CHAN_5GHZ(chan))
1702 		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1703 	else
1704 		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1705 
1706 	txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1707 
1708 	if (modesIndex == ah->modes_index) {
1709 		*ini_reloaded = false;
1710 		goto set_rfmode;
1711 	}
1712 
1713 	ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1714 	ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1715 	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1716 	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1717 
1718 	if (AR_SREV_9462_20_OR_LATER(ah))
1719 		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1720 				   modesIndex);
1721 
1722 	REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1723 
1724 	if (AR_SREV_9462_20_OR_LATER(ah)) {
1725 		/*
1726 		 * CUS217 mix LNA mode.
1727 		 */
1728 		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1729 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1730 					1, regWrites);
1731 			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1732 					modesIndex, regWrites);
1733 		}
1734 	}
1735 
1736 	/*
1737 	 * For 5GHz channels requiring Fast Clock, apply
1738 	 * different modal values.
1739 	 */
1740 	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1741 		REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1742 
1743 	if (AR_SREV_9565(ah))
1744 		REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1745 
1746 	/*
1747 	 * JAPAN regulatory.
1748 	 */
1749 	if (chan->channel == 2484)
1750 		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1751 
1752 	ah->modes_index = modesIndex;
1753 	*ini_reloaded = true;
1754 
1755 set_rfmode:
1756 	ar9003_hw_set_rfmode(ah, chan);
1757 	return 0;
1758 }
1759 
1760 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1761 					   struct ath_spec_scan *param)
1762 {
1763 	u8 count;
1764 
1765 	if (!param->enabled) {
1766 		REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1767 			    AR_PHY_SPECTRAL_SCAN_ENABLE);
1768 		return;
1769 	}
1770 
1771 	REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1772 	REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1773 
1774 	/* on AR93xx and newer, count = 0 will make the the chip send
1775 	 * spectral samples endlessly. Check if this really was intended,
1776 	 * and fix otherwise.
1777 	 */
1778 	count = param->count;
1779 	if (param->endless)
1780 		count = 0;
1781 	else if (param->count == 0)
1782 		count = 1;
1783 
1784 	if (param->short_repeat)
1785 		REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1786 			    AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1787 	else
1788 		REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1789 			    AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1790 
1791 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1792 		      AR_PHY_SPECTRAL_SCAN_COUNT, count);
1793 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1794 		      AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1795 	REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1796 		      AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1797 
1798 	return;
1799 }
1800 
1801 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1802 {
1803 	/* Activate spectral scan */
1804 	REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1805 		    AR_PHY_SPECTRAL_SCAN_ACTIVE);
1806 }
1807 
1808 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1809 {
1810 	struct ath_common *common = ath9k_hw_common(ah);
1811 
1812 	/* Poll for spectral scan complete */
1813 	if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1814 			   AR_PHY_SPECTRAL_SCAN_ACTIVE,
1815 			   0, AH_WAIT_TIMEOUT)) {
1816 		ath_err(common, "spectral scan wait failed\n");
1817 		return;
1818 	}
1819 }
1820 
1821 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1822 {
1823 	REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1824 	REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1825 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
1826 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1827 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1828 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1829 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1830 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1831 	REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1832 }
1833 
1834 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1835 {
1836 	REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1837 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1838 }
1839 
1840 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1841 {
1842 	static u8 p_pwr_array[ar9300RateSize] = { 0 };
1843 	unsigned int i;
1844 
1845 	txpower = txpower <= MAX_RATE_POWER ? txpower : MAX_RATE_POWER;
1846 	for (i = 0; i < ar9300RateSize; i++)
1847 		p_pwr_array[i] = txpower;
1848 
1849 	ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
1850 }
1851 
1852 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1853 {
1854 	ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1855 	ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1856 	ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1857 			      rate_array[ALL_TARGET_LEGACY_5S]);
1858 	ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1859 			      rate_array[ALL_TARGET_LEGACY_11S]);
1860 }
1861 
1862 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1863 					int offset)
1864 {
1865 	int i, j;
1866 
1867 	for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1868 		/* OFDM rate to power table idx */
1869 		j = ofdm2pwr[i - offset];
1870 		ah->tx_power[i] = rate_array[j];
1871 	}
1872 }
1873 
1874 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1875 				      int ss_offset, int ds_offset,
1876 				      int ts_offset, bool is_40)
1877 {
1878 	int i, j, mcs_idx = 0;
1879 	const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1880 
1881 	for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1882 		j = mcs2pwr[mcs_idx];
1883 		ah->tx_power[i] = rate_array[j];
1884 		mcs_idx++;
1885 	}
1886 
1887 	for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1888 		j = mcs2pwr[mcs_idx];
1889 		ah->tx_power[i] = rate_array[j];
1890 		mcs_idx++;
1891 	}
1892 
1893 	for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1894 		j = mcs2pwr[mcs_idx];
1895 		ah->tx_power[i] = rate_array[j];
1896 		mcs_idx++;
1897 	}
1898 }
1899 
1900 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1901 					int ds_offset, int ts_offset)
1902 {
1903 	memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1904 	       AR9300_HT_SS_RATES);
1905 	memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1906 	       AR9300_HT_DS_RATES);
1907 	memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1908 	       AR9300_HT_TS_RATES);
1909 }
1910 
1911 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1912 				 struct ath9k_channel *chan)
1913 {
1914 	if (IS_CHAN_5GHZ(chan)) {
1915 		ar9003_hw_init_txpower_ofdm(ah, rate_array,
1916 					    AR9300_11NA_OFDM_SHIFT);
1917 		if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1918 			ar9003_hw_init_txpower_ht(ah, rate_array,
1919 						  AR9300_11NA_HT_SS_SHIFT,
1920 						  AR9300_11NA_HT_DS_SHIFT,
1921 						  AR9300_11NA_HT_TS_SHIFT,
1922 						  IS_CHAN_HT40(chan));
1923 			ar9003_hw_init_txpower_stbc(ah,
1924 						    AR9300_11NA_HT_SS_SHIFT,
1925 						    AR9300_11NA_HT_DS_SHIFT,
1926 						    AR9300_11NA_HT_TS_SHIFT);
1927 		}
1928 	} else {
1929 		ar9003_hw_init_txpower_cck(ah, rate_array);
1930 		ar9003_hw_init_txpower_ofdm(ah, rate_array,
1931 					    AR9300_11NG_OFDM_SHIFT);
1932 		if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1933 			ar9003_hw_init_txpower_ht(ah, rate_array,
1934 						  AR9300_11NG_HT_SS_SHIFT,
1935 						  AR9300_11NG_HT_DS_SHIFT,
1936 						  AR9300_11NG_HT_TS_SHIFT,
1937 						  IS_CHAN_HT40(chan));
1938 			ar9003_hw_init_txpower_stbc(ah,
1939 						    AR9300_11NG_HT_SS_SHIFT,
1940 						    AR9300_11NG_HT_DS_SHIFT,
1941 						    AR9300_11NG_HT_TS_SHIFT);
1942 		}
1943 	}
1944 }
1945 
1946 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1947 {
1948 	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1949 	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1950 	static const u32 ar9300_cca_regs[6] = {
1951 		AR_PHY_CCA_0,
1952 		AR_PHY_CCA_1,
1953 		AR_PHY_CCA_2,
1954 		AR_PHY_EXT_CCA,
1955 		AR_PHY_EXT_CCA_1,
1956 		AR_PHY_EXT_CCA_2,
1957 	};
1958 
1959 	priv_ops->rf_set_freq = ar9003_hw_set_channel;
1960 	priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1961 
1962 	if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1963 	    AR_SREV_9561(ah))
1964 		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
1965 	else
1966 		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1967 
1968 	priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1969 	priv_ops->init_bb = ar9003_hw_init_bb;
1970 	priv_ops->process_ini = ar9003_hw_process_ini;
1971 	priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1972 	priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1973 	priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1974 	priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1975 	priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1976 	priv_ops->ani_control = ar9003_hw_ani_control;
1977 	priv_ops->do_getnf = ar9003_hw_do_getnf;
1978 	priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1979 	priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1980 	priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1981 
1982 	ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1983 	ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1984 	ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1985 	ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1986 	ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1987 
1988 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1989 	ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1990 #endif
1991 	ops->tx99_start = ar9003_hw_tx99_start;
1992 	ops->tx99_stop = ar9003_hw_tx99_stop;
1993 	ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1994 
1995 	ar9003_hw_set_nf_limits(ah);
1996 	ar9003_hw_set_radar_conf(ah);
1997 	memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1998 }
1999 
2000 /*
2001  * Baseband Watchdog signatures:
2002  *
2003  * 0x04000539: BB hang when operating in HT40 DFS Channel.
2004  *             Full chip reset is not required, but a recovery
2005  *             mechanism is needed.
2006  *
2007  * 0x1300000a: Related to CAC deafness.
2008  *             Chip reset is not required.
2009  *
2010  * 0x0400000a: Related to CAC deafness.
2011  *             Full chip reset is required.
2012  *
2013  * 0x04000b09: RX state machine gets into an illegal state
2014  *             when a packet with unsupported rate is received.
2015  *             Full chip reset is required and PHY_RESTART has
2016  *             to be disabled.
2017  *
2018  * 0x04000409: Packet stuck on receive.
2019  *             Full chip reset is required for all chips except
2020  *	       AR9340, AR9531 and AR9561.
2021  */
2022 
2023 /*
2024  * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
2025  */
2026 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2027 {
2028 	u32 val;
2029 
2030 	switch(ah->bb_watchdog_last_status) {
2031 	case 0x04000539:
2032 		val = REG_READ(ah, AR_PHY_RADAR_0);
2033 		val &= (~AR_PHY_RADAR_0_FIRPWR);
2034 		val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2035 		REG_WRITE(ah, AR_PHY_RADAR_0, val);
2036 		udelay(1);
2037 		val = REG_READ(ah, AR_PHY_RADAR_0);
2038 		val &= ~AR_PHY_RADAR_0_FIRPWR;
2039 		val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2040 		REG_WRITE(ah, AR_PHY_RADAR_0, val);
2041 
2042 		return false;
2043 	case 0x1300000a:
2044 		return false;
2045 	case 0x0400000a:
2046 	case 0x04000b09:
2047 		return true;
2048 	case 0x04000409:
2049 		if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah))
2050 			return false;
2051 		else
2052 			return true;
2053 	default:
2054 		/*
2055 		 * For any other unknown signatures, do a
2056 		 * full chip reset.
2057 		 */
2058 		return true;
2059 	}
2060 }
2061 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2062 
2063 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2064 {
2065 	struct ath_common *common = ath9k_hw_common(ah);
2066 	u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2067 	u32 val, idle_count;
2068 
2069 	if (!idle_tmo_ms) {
2070 		/* disable IRQ, disable chip-reset for BB panic */
2071 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2072 			  REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2073 			  ~(AR_PHY_WATCHDOG_RST_ENABLE |
2074 			    AR_PHY_WATCHDOG_IRQ_ENABLE));
2075 
2076 		/* disable watchdog in non-IDLE mode, disable in IDLE mode */
2077 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2078 			  REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2079 			  ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2080 			    AR_PHY_WATCHDOG_IDLE_ENABLE));
2081 
2082 		ath_dbg(common, RESET, "Disabled BB Watchdog\n");
2083 		return;
2084 	}
2085 
2086 	/* enable IRQ, disable chip-reset for BB watchdog */
2087 	val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2088 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2089 		  (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2090 		  ~AR_PHY_WATCHDOG_RST_ENABLE);
2091 
2092 	/* bound limit to 10 secs */
2093 	if (idle_tmo_ms > 10000)
2094 		idle_tmo_ms = 10000;
2095 
2096 	/*
2097 	 * The time unit for watchdog event is 2^15 44/88MHz cycles.
2098 	 *
2099 	 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2100 	 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2101 	 *
2102 	 * Given we use fast clock now in 5 GHz, these time units should
2103 	 * be common for both 2 GHz and 5 GHz.
2104 	 */
2105 	idle_count = (100 * idle_tmo_ms) / 74;
2106 	if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2107 		idle_count = (100 * idle_tmo_ms) / 37;
2108 
2109 	/*
2110 	 * enable watchdog in non-IDLE mode, disable in IDLE mode,
2111 	 * set idle time-out.
2112 	 */
2113 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2114 		  AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2115 		  AR_PHY_WATCHDOG_IDLE_MASK |
2116 		  (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2117 
2118 	ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
2119 		idle_tmo_ms);
2120 }
2121 
2122 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2123 {
2124 	/*
2125 	 * we want to avoid printing in ISR context so we save the
2126 	 * watchdog status to be printed later in bottom half context.
2127 	 */
2128 	ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2129 
2130 	/*
2131 	 * the watchdog timer should reset on status read but to be sure
2132 	 * sure we write 0 to the watchdog status bit.
2133 	 */
2134 	REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2135 		  ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2136 }
2137 
2138 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2139 {
2140 	struct ath_common *common = ath9k_hw_common(ah);
2141 	u32 status;
2142 
2143 	if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2144 		return;
2145 
2146 	status = ah->bb_watchdog_last_status;
2147 	ath_dbg(common, RESET,
2148 		"\n==== BB update: BB status=0x%08x ====\n", status);
2149 	ath_dbg(common, RESET,
2150 		"** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2151 		MS(status, AR_PHY_WATCHDOG_INFO),
2152 		MS(status, AR_PHY_WATCHDOG_DET_HANG),
2153 		MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2154 		MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2155 		MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2156 		MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2157 		MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2158 		MS(status, AR_PHY_WATCHDOG_AGC_SM),
2159 		MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2160 
2161 	ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
2162 		REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2163 		REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2164 	ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
2165 		REG_READ(ah, AR_PHY_GEN_CTRL));
2166 
2167 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2168 	if (common->cc_survey.cycles)
2169 		ath_dbg(common, RESET,
2170 			"** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2171 			PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
2172 
2173 	ath_dbg(common, RESET, "==== BB update: done ====\n\n");
2174 }
2175 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
2176 
2177 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2178 {
2179 	u8 result;
2180 	u32 val;
2181 
2182 	/* While receiving unsupported rate frame rx state machine
2183 	 * gets into a state 0xb and if phy_restart happens in that
2184 	 * state, BB would go hang. If RXSM is in 0xb state after
2185 	 * first bb panic, ensure to disable the phy_restart.
2186 	 */
2187 	result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2188 
2189 	if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2190 		ah->bb_hang_rx_ofdm = true;
2191 		val = REG_READ(ah, AR_PHY_RESTART);
2192 		val &= ~AR_PHY_RESTART_ENA;
2193 		REG_WRITE(ah, AR_PHY_RESTART, val);
2194 	}
2195 }
2196 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
2197