1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 21 #define AR9300_OFDM_RATES 8 22 #define AR9300_HT_SS_RATES 8 23 #define AR9300_HT_DS_RATES 8 24 #define AR9300_HT_TS_RATES 8 25 26 #define AR9300_11NA_OFDM_SHIFT 0 27 #define AR9300_11NA_HT_SS_SHIFT 8 28 #define AR9300_11NA_HT_DS_SHIFT 16 29 #define AR9300_11NA_HT_TS_SHIFT 24 30 31 #define AR9300_11NG_OFDM_SHIFT 4 32 #define AR9300_11NG_HT_SS_SHIFT 12 33 #define AR9300_11NG_HT_DS_SHIFT 20 34 #define AR9300_11NG_HT_TS_SHIFT 28 35 36 static const int firstep_table[] = 37 /* level: 0 1 2 3 4 5 6 7 8 */ 38 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 39 40 static const int cycpwrThr1_table[] = 41 /* level: 0 1 2 3 4 5 6 7 8 */ 42 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 43 44 /* 45 * register values to turn OFDM weak signal detection OFF 46 */ 47 static const int m1ThreshLow_off = 127; 48 static const int m2ThreshLow_off = 127; 49 static const int m1Thresh_off = 127; 50 static const int m2Thresh_off = 127; 51 static const int m2CountThr_off = 31; 52 static const int m2CountThrLow_off = 63; 53 static const int m1ThreshLowExt_off = 127; 54 static const int m2ThreshLowExt_off = 127; 55 static const int m1ThreshExt_off = 127; 56 static const int m2ThreshExt_off = 127; 57 58 static const u8 ofdm2pwr[] = { 59 ALL_TARGET_LEGACY_6_24, 60 ALL_TARGET_LEGACY_6_24, 61 ALL_TARGET_LEGACY_6_24, 62 ALL_TARGET_LEGACY_6_24, 63 ALL_TARGET_LEGACY_6_24, 64 ALL_TARGET_LEGACY_36, 65 ALL_TARGET_LEGACY_48, 66 ALL_TARGET_LEGACY_54 67 }; 68 69 static const u8 mcs2pwr_ht20[] = { 70 ALL_TARGET_HT20_0_8_16, 71 ALL_TARGET_HT20_1_3_9_11_17_19, 72 ALL_TARGET_HT20_1_3_9_11_17_19, 73 ALL_TARGET_HT20_1_3_9_11_17_19, 74 ALL_TARGET_HT20_4, 75 ALL_TARGET_HT20_5, 76 ALL_TARGET_HT20_6, 77 ALL_TARGET_HT20_7, 78 ALL_TARGET_HT20_0_8_16, 79 ALL_TARGET_HT20_1_3_9_11_17_19, 80 ALL_TARGET_HT20_1_3_9_11_17_19, 81 ALL_TARGET_HT20_1_3_9_11_17_19, 82 ALL_TARGET_HT20_12, 83 ALL_TARGET_HT20_13, 84 ALL_TARGET_HT20_14, 85 ALL_TARGET_HT20_15, 86 ALL_TARGET_HT20_0_8_16, 87 ALL_TARGET_HT20_1_3_9_11_17_19, 88 ALL_TARGET_HT20_1_3_9_11_17_19, 89 ALL_TARGET_HT20_1_3_9_11_17_19, 90 ALL_TARGET_HT20_20, 91 ALL_TARGET_HT20_21, 92 ALL_TARGET_HT20_22, 93 ALL_TARGET_HT20_23 94 }; 95 96 static const u8 mcs2pwr_ht40[] = { 97 ALL_TARGET_HT40_0_8_16, 98 ALL_TARGET_HT40_1_3_9_11_17_19, 99 ALL_TARGET_HT40_1_3_9_11_17_19, 100 ALL_TARGET_HT40_1_3_9_11_17_19, 101 ALL_TARGET_HT40_4, 102 ALL_TARGET_HT40_5, 103 ALL_TARGET_HT40_6, 104 ALL_TARGET_HT40_7, 105 ALL_TARGET_HT40_0_8_16, 106 ALL_TARGET_HT40_1_3_9_11_17_19, 107 ALL_TARGET_HT40_1_3_9_11_17_19, 108 ALL_TARGET_HT40_1_3_9_11_17_19, 109 ALL_TARGET_HT40_12, 110 ALL_TARGET_HT40_13, 111 ALL_TARGET_HT40_14, 112 ALL_TARGET_HT40_15, 113 ALL_TARGET_HT40_0_8_16, 114 ALL_TARGET_HT40_1_3_9_11_17_19, 115 ALL_TARGET_HT40_1_3_9_11_17_19, 116 ALL_TARGET_HT40_1_3_9_11_17_19, 117 ALL_TARGET_HT40_20, 118 ALL_TARGET_HT40_21, 119 ALL_TARGET_HT40_22, 120 ALL_TARGET_HT40_23, 121 }; 122 123 /** 124 * ar9003_hw_set_channel - set channel on single-chip device 125 * @ah: atheros hardware structure 126 * @chan: 127 * 128 * This is the function to change channel on single-chip devices, that is 129 * for AR9300 family of chipsets. 130 * 131 * This function takes the channel value in MHz and sets 132 * hardware channel value. Assumes writes have been enabled to analog bus. 133 * 134 * Actual Expression, 135 * 136 * For 2GHz channel, 137 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 138 * (freq_ref = 40MHz) 139 * 140 * For 5GHz channel, 141 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 142 * (freq_ref = 40MHz/(24>>amodeRefSel)) 143 * 144 * For 5GHz channels which are 5MHz spaced, 145 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 146 * (freq_ref = 40MHz) 147 */ 148 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 149 { 150 u16 bMode, fracMode = 0, aModeRefSel = 0; 151 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; 152 struct chan_centers centers; 153 int loadSynthChannel; 154 155 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 156 freq = centers.synth_center; 157 158 if (freq < 4800) { /* 2 GHz, fractional mode */ 159 if (AR_SREV_9330(ah)) { 160 if (ah->is_clk_25mhz) 161 div = 75; 162 else 163 div = 120; 164 165 channelSel = (freq * 4) / div; 166 chan_frac = (((freq * 4) % div) * 0x20000) / div; 167 channelSel = (channelSel << 17) | chan_frac; 168 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 169 /* 170 * freq_ref = 40 / (refdiva >> amoderefsel); 171 * where refdiva=1 and amoderefsel=0 172 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 173 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 174 */ 175 channelSel = (freq * 4) / 120; 176 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 177 channelSel = (channelSel << 17) | chan_frac; 178 } else if (AR_SREV_9340(ah)) { 179 if (ah->is_clk_25mhz) { 180 channelSel = (freq * 2) / 75; 181 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 182 channelSel = (channelSel << 17) | chan_frac; 183 } else { 184 channelSel = CHANSEL_2G(freq) >> 1; 185 } 186 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 187 if (ah->is_clk_25mhz) 188 div = 75; 189 else 190 div = 120; 191 192 channelSel = (freq * 4) / div; 193 chan_frac = (((freq * 4) % div) * 0x20000) / div; 194 channelSel = (channelSel << 17) | chan_frac; 195 } else { 196 channelSel = CHANSEL_2G(freq); 197 } 198 /* Set to 2G mode */ 199 bMode = 1; 200 } else { 201 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) && 202 ah->is_clk_25mhz) { 203 channelSel = freq / 75; 204 chan_frac = ((freq % 75) * 0x20000) / 75; 205 channelSel = (channelSel << 17) | chan_frac; 206 } else { 207 channelSel = CHANSEL_5G(freq); 208 /* Doubler is ON, so, divide channelSel by 2. */ 209 channelSel >>= 1; 210 } 211 /* Set to 5G mode */ 212 bMode = 0; 213 } 214 215 /* Enable fractional mode for all channels */ 216 fracMode = 1; 217 aModeRefSel = 0; 218 loadSynthChannel = 0; 219 220 reg32 = (bMode << 29); 221 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 222 223 /* Enable Long shift Select for Synthesizer */ 224 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 225 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 226 227 /* Program Synth. setting */ 228 reg32 = (channelSel << 2) | (fracMode << 30) | 229 (aModeRefSel << 28) | (loadSynthChannel << 31); 230 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 231 232 /* Toggle Load Synth channel bit */ 233 loadSynthChannel = 1; 234 reg32 = (channelSel << 2) | (fracMode << 30) | 235 (aModeRefSel << 28) | (loadSynthChannel << 31); 236 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 237 238 ah->curchan = chan; 239 240 return 0; 241 } 242 243 /** 244 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 245 * @ah: atheros hardware structure 246 * @chan: 247 * 248 * For single-chip solutions. Converts to baseband spur frequency given the 249 * input channel frequency and compute register settings below. 250 * 251 * Spur mitigation for MRC CCK 252 */ 253 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 254 struct ath9k_channel *chan) 255 { 256 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 257 int cur_bb_spur, negative = 0, cck_spur_freq; 258 int i; 259 int range, max_spur_cnts, synth_freq; 260 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); 261 262 /* 263 * Need to verify range +/- 10 MHz in control channel, otherwise spur 264 * is out-of-band and can be ignored. 265 */ 266 267 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 268 AR_SREV_9550(ah)) { 269 if (spur_fbin_ptr[0] == 0) /* No spur */ 270 return; 271 max_spur_cnts = 5; 272 if (IS_CHAN_HT40(chan)) { 273 range = 19; 274 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 275 AR_PHY_GC_DYN2040_PRI_CH) == 0) 276 synth_freq = chan->channel + 10; 277 else 278 synth_freq = chan->channel - 10; 279 } else { 280 range = 10; 281 synth_freq = chan->channel; 282 } 283 } else { 284 range = AR_SREV_9462(ah) ? 5 : 10; 285 max_spur_cnts = 4; 286 synth_freq = chan->channel; 287 } 288 289 for (i = 0; i < max_spur_cnts; i++) { 290 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 291 continue; 292 293 negative = 0; 294 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 295 AR_SREV_9550(ah)) 296 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], 297 IS_CHAN_2GHZ(chan)); 298 else 299 cur_bb_spur = spur_freq[i]; 300 301 cur_bb_spur -= synth_freq; 302 if (cur_bb_spur < 0) { 303 negative = 1; 304 cur_bb_spur = -cur_bb_spur; 305 } 306 if (cur_bb_spur < range) { 307 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 308 309 if (negative == 1) 310 cck_spur_freq = -cck_spur_freq; 311 312 cck_spur_freq = cck_spur_freq & 0xfffff; 313 314 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 315 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 316 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 317 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 318 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 319 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 320 0x2); 321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 322 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 323 0x1); 324 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 325 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 326 cck_spur_freq); 327 328 return; 329 } 330 } 331 332 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 333 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 334 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 335 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 336 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 337 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 338 } 339 340 /* Clean all spur register fields */ 341 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 342 { 343 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 344 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 345 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 346 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 347 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 348 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 349 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 350 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 351 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 352 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 353 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 354 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 355 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 356 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 357 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 358 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 359 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 360 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 361 362 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 363 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 364 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 365 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 366 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 367 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 368 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 369 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 370 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 371 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 372 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 373 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 374 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 375 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 376 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 377 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 378 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 379 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 380 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 381 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 382 } 383 384 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 385 int freq_offset, 386 int spur_freq_sd, 387 int spur_delta_phase, 388 int spur_subchannel_sd, 389 int range, 390 int synth_freq) 391 { 392 int mask_index = 0; 393 394 /* OFDM Spur mitigation */ 395 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 396 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 397 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 398 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 399 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 400 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 401 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 402 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 403 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 404 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 405 406 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) 407 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 408 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 409 410 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 411 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 412 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 413 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 415 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 416 417 if (!AR_SREV_9340(ah) && 418 REG_READ_FIELD(ah, AR_PHY_MODE, 419 AR_PHY_MODE_DYNAMIC) == 0x1) 420 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 421 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 422 423 mask_index = (freq_offset << 4) / 5; 424 if (mask_index < 0) 425 mask_index = mask_index - 1; 426 427 mask_index = mask_index & 0x7f; 428 429 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 430 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 431 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 432 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 433 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 434 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 435 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 436 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 437 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 438 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 439 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 440 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 441 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 442 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 443 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 444 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 445 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 446 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 447 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 448 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 449 } 450 451 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, 452 int freq_offset) 453 { 454 int mask_index = 0; 455 456 mask_index = (freq_offset << 4) / 5; 457 if (mask_index < 0) 458 mask_index = mask_index - 1; 459 460 mask_index = mask_index & 0x7f; 461 462 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 463 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B, 464 mask_index); 465 466 /* A == B */ 467 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 468 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 469 mask_index); 470 471 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 472 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B, 473 mask_index); 474 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 475 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe); 476 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 477 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe); 478 479 /* A == B */ 480 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 481 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 482 } 483 484 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 485 struct ath9k_channel *chan, 486 int freq_offset, 487 int range, 488 int synth_freq) 489 { 490 int spur_freq_sd = 0; 491 int spur_subchannel_sd = 0; 492 int spur_delta_phase = 0; 493 494 if (IS_CHAN_HT40(chan)) { 495 if (freq_offset < 0) { 496 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 497 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 498 spur_subchannel_sd = 1; 499 else 500 spur_subchannel_sd = 0; 501 502 spur_freq_sd = ((freq_offset + 10) << 9) / 11; 503 504 } else { 505 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 506 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 507 spur_subchannel_sd = 0; 508 else 509 spur_subchannel_sd = 1; 510 511 spur_freq_sd = ((freq_offset - 10) << 9) / 11; 512 513 } 514 515 spur_delta_phase = (freq_offset << 17) / 5; 516 517 } else { 518 spur_subchannel_sd = 0; 519 spur_freq_sd = (freq_offset << 9) /11; 520 spur_delta_phase = (freq_offset << 18) / 5; 521 } 522 523 spur_freq_sd = spur_freq_sd & 0x3ff; 524 spur_delta_phase = spur_delta_phase & 0xfffff; 525 526 ar9003_hw_spur_ofdm(ah, 527 freq_offset, 528 spur_freq_sd, 529 spur_delta_phase, 530 spur_subchannel_sd, 531 range, synth_freq); 532 } 533 534 /* Spur mitigation for OFDM */ 535 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 536 struct ath9k_channel *chan) 537 { 538 int synth_freq; 539 int range = 10; 540 int freq_offset = 0; 541 int mode; 542 u8* spurChansPtr; 543 unsigned int i; 544 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 545 546 if (IS_CHAN_5GHZ(chan)) { 547 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 548 mode = 0; 549 } 550 else { 551 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 552 mode = 1; 553 } 554 555 if (spurChansPtr[0] == 0) 556 return; /* No spur in the mode */ 557 558 if (IS_CHAN_HT40(chan)) { 559 range = 19; 560 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 561 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 562 synth_freq = chan->channel - 10; 563 else 564 synth_freq = chan->channel + 10; 565 } else { 566 range = 10; 567 synth_freq = chan->channel; 568 } 569 570 ar9003_hw_spur_ofdm_clear(ah); 571 572 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 573 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode); 574 freq_offset -= synth_freq; 575 if (abs(freq_offset) < range) { 576 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, 577 range, synth_freq); 578 579 if (AR_SREV_9565(ah) && (i < 4)) { 580 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1], 581 mode); 582 freq_offset -= synth_freq; 583 if (abs(freq_offset) < range) 584 ar9003_hw_spur_ofdm_9565(ah, freq_offset); 585 } 586 587 break; 588 } 589 } 590 } 591 592 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 593 struct ath9k_channel *chan) 594 { 595 if (!AR_SREV_9565(ah)) 596 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 597 ar9003_hw_spur_mitigate_ofdm(ah, chan); 598 } 599 600 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, 601 struct ath9k_channel *chan) 602 { 603 u32 pll; 604 605 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); 606 607 if (chan && IS_CHAN_HALF_RATE(chan)) 608 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); 609 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 610 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); 611 612 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); 613 614 return pll; 615 } 616 617 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 618 struct ath9k_channel *chan) 619 { 620 u32 pll; 621 622 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 623 624 if (chan && IS_CHAN_HALF_RATE(chan)) 625 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 626 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 627 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 628 629 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 630 631 return pll; 632 } 633 634 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 635 struct ath9k_channel *chan) 636 { 637 u32 phymode; 638 u32 enableDacFifo = 0; 639 640 enableDacFifo = 641 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 642 643 /* Enable 11n HT, 20 MHz */ 644 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 645 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 646 647 /* Configure baseband for dynamic 20/40 operation */ 648 if (IS_CHAN_HT40(chan)) { 649 phymode |= AR_PHY_GC_DYN2040_EN; 650 /* Configure control (primary) channel at +-10MHz */ 651 if (IS_CHAN_HT40PLUS(chan)) 652 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 653 654 } 655 656 /* make sure we preserve INI settings */ 657 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 658 /* turn off Green Field detection for STA for now */ 659 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 660 661 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 662 663 /* Configure MAC for 20/40 operation */ 664 ath9k_hw_set11nmac2040(ah, chan); 665 666 /* global transmit timeout (25 TUs default)*/ 667 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 668 /* carrier sense timeout */ 669 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 670 } 671 672 static void ar9003_hw_init_bb(struct ath_hw *ah, 673 struct ath9k_channel *chan) 674 { 675 u32 synthDelay; 676 677 /* 678 * Wait for the frequency synth to settle (synth goes on 679 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 680 * Value is in 100ns increments. 681 */ 682 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 683 684 /* Activate the PHY (includes baseband activate + synthesizer on) */ 685 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 686 ath9k_hw_synth_delay(ah, chan, synthDelay); 687 } 688 689 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 690 { 691 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) 692 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 693 AR_PHY_SWAP_ALT_CHAIN); 694 695 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 696 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 697 698 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 699 tx = 3; 700 701 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 702 } 703 704 /* 705 * Override INI values with chip specific configuration. 706 */ 707 static void ar9003_hw_override_ini(struct ath_hw *ah) 708 { 709 u32 val; 710 711 /* 712 * Set the RX_ABORT and RX_DIS and clear it only after 713 * RXE is set for MAC. This prevents frames with 714 * corrupted descriptor status. 715 */ 716 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 717 718 /* 719 * For AR9280 and above, there is a new feature that allows 720 * Multicast search based on both MAC Address and Key ID. By default, 721 * this feature is enabled. But since the driver is not using this 722 * feature, we switch it off; otherwise multicast search based on 723 * MAC addr only will fail. 724 */ 725 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 726 val |= AR_AGG_WEP_ENABLE_FIX | 727 AR_AGG_WEP_ENABLE | 728 AR_PCU_MISC_MODE2_CFP_IGNORE; 729 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 730 731 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 732 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, 733 AR_GLB_SWREG_DISCONT_EN_BT_WLAN); 734 735 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 736 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 737 ah->enabled_cals |= TX_IQ_CAL; 738 else 739 ah->enabled_cals &= ~TX_IQ_CAL; 740 741 } 742 743 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 744 ah->enabled_cals |= TX_CL_CAL; 745 else 746 ah->enabled_cals &= ~TX_CL_CAL; 747 748 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { 749 if (ah->is_clk_25mhz) { 750 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 751 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 752 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 753 } else { 754 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 755 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 756 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 757 } 758 udelay(100); 759 } 760 } 761 762 static void ar9003_hw_prog_ini(struct ath_hw *ah, 763 struct ar5416IniArray *iniArr, 764 int column) 765 { 766 unsigned int i, regWrites = 0; 767 768 /* New INI format: Array may be undefined (pre, core, post arrays) */ 769 if (!iniArr->ia_array) 770 return; 771 772 /* 773 * New INI format: Pre, core, and post arrays for a given subsystem 774 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 775 * the array is non-modal and force the column to 1. 776 */ 777 if (column >= iniArr->ia_columns) 778 column = 1; 779 780 for (i = 0; i < iniArr->ia_rows; i++) { 781 u32 reg = INI_RA(iniArr, i, 0); 782 u32 val = INI_RA(iniArr, i, column); 783 784 REG_WRITE(ah, reg, val); 785 786 DO_DELAY(regWrites); 787 } 788 } 789 790 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, 791 struct ath9k_channel *chan) 792 { 793 int ret; 794 795 if (IS_CHAN_2GHZ(chan)) { 796 if (IS_CHAN_HT40(chan)) 797 return 7; 798 else 799 return 8; 800 } 801 802 if (chan->channel <= 5350) 803 ret = 1; 804 else if ((chan->channel > 5350) && (chan->channel <= 5600)) 805 ret = 3; 806 else 807 ret = 5; 808 809 if (IS_CHAN_HT40(chan)) 810 ret++; 811 812 return ret; 813 } 814 815 static void ar9003_doubler_fix(struct ath_hw *ah) 816 { 817 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { 818 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 819 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 820 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 821 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 822 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 823 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 824 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 825 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 826 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 827 828 udelay(200); 829 830 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, 831 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 832 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, 833 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 834 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, 835 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 836 837 udelay(1); 838 839 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, 840 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 841 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, 842 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 843 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, 844 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 845 846 udelay(200); 847 848 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, 849 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf); 850 851 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, 852 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 853 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 854 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, 855 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 856 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 857 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, 858 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 859 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 860 } 861 } 862 863 static int ar9003_hw_process_ini(struct ath_hw *ah, 864 struct ath9k_channel *chan) 865 { 866 unsigned int regWrites = 0, i; 867 u32 modesIndex; 868 869 if (IS_CHAN_5GHZ(chan)) 870 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 871 else 872 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 873 874 /* 875 * SOC, MAC, BB, RADIO initvals. 876 */ 877 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 878 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 879 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 880 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 881 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 882 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) 883 ar9003_hw_prog_ini(ah, 884 &ah->ini_radio_post_sys2ant, 885 modesIndex); 886 } 887 888 ar9003_doubler_fix(ah); 889 890 /* 891 * RXGAIN initvals. 892 */ 893 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 894 895 if (AR_SREV_9462_20_OR_LATER(ah)) { 896 /* 897 * CUS217 mix LNA mode. 898 */ 899 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { 900 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, 901 1, regWrites); 902 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 903 modesIndex, regWrites); 904 } 905 906 /* 907 * 5G-XLNA 908 */ 909 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || 910 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { 911 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 912 modesIndex, regWrites); 913 } 914 } 915 916 if (AR_SREV_9550(ah)) 917 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, 918 regWrites); 919 920 /* 921 * TXGAIN initvals. 922 */ 923 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 924 int modes_txgain_index = 1; 925 926 if (AR_SREV_9550(ah)) 927 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); 928 929 if (modes_txgain_index < 0) 930 return -EINVAL; 931 932 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, 933 regWrites); 934 } else { 935 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 936 } 937 938 /* 939 * For 5GHz channels requiring Fast Clock, apply 940 * different modal values. 941 */ 942 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 943 REG_WRITE_ARRAY(&ah->iniModesFastClock, 944 modesIndex, regWrites); 945 946 /* 947 * Clock frequency initvals. 948 */ 949 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 950 951 /* 952 * JAPAN regulatory. 953 */ 954 if (chan->channel == 2484) 955 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); 956 957 ah->modes_index = modesIndex; 958 ar9003_hw_override_ini(ah); 959 ar9003_hw_set_channel_regs(ah, chan); 960 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 961 ath9k_hw_apply_txpower(ah, chan, false); 962 963 return 0; 964 } 965 966 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 967 struct ath9k_channel *chan) 968 { 969 u32 rfMode = 0; 970 971 if (chan == NULL) 972 return; 973 974 if (IS_CHAN_2GHZ(chan)) 975 rfMode |= AR_PHY_MODE_DYNAMIC; 976 else 977 rfMode |= AR_PHY_MODE_OFDM; 978 979 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 980 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 981 982 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF)) 983 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 984 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3); 985 986 REG_WRITE(ah, AR_PHY_MODE, rfMode); 987 } 988 989 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 990 { 991 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 992 } 993 994 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 995 struct ath9k_channel *chan) 996 { 997 u32 coef_scaled, ds_coef_exp, ds_coef_man; 998 u32 clockMhzScaled = 0x64000000; 999 struct chan_centers centers; 1000 1001 /* 1002 * half and quarter rate can divide the scaled clock by 2 or 4 1003 * scale for selected channel bandwidth 1004 */ 1005 if (IS_CHAN_HALF_RATE(chan)) 1006 clockMhzScaled = clockMhzScaled >> 1; 1007 else if (IS_CHAN_QUARTER_RATE(chan)) 1008 clockMhzScaled = clockMhzScaled >> 2; 1009 1010 /* 1011 * ALGO -> coef = 1e8/fcarrier*fclock/40; 1012 * scaled coef to provide precision for this floating calculation 1013 */ 1014 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 1015 coef_scaled = clockMhzScaled / centers.synth_center; 1016 1017 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1018 &ds_coef_exp); 1019 1020 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1021 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1022 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1023 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1024 1025 /* 1026 * For Short GI, 1027 * scaled coeff is 9/10 that of normal coeff 1028 */ 1029 coef_scaled = (9 * coef_scaled) / 10; 1030 1031 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 1032 &ds_coef_exp); 1033 1034 /* for short gi */ 1035 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 1036 AR_PHY_SGI_DSC_MAN, ds_coef_man); 1037 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 1038 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 1039 } 1040 1041 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 1042 { 1043 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1044 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1045 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 1046 } 1047 1048 /* 1049 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 1050 * Read the phy active delay register. Value is in 100ns increments. 1051 */ 1052 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 1053 { 1054 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1055 1056 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 1057 1058 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 1059 } 1060 1061 static bool ar9003_hw_ani_control(struct ath_hw *ah, 1062 enum ath9k_ani_cmd cmd, int param) 1063 { 1064 struct ath_common *common = ath9k_hw_common(ah); 1065 struct ath9k_channel *chan = ah->curchan; 1066 struct ar5416AniState *aniState = &ah->ani; 1067 int m1ThreshLow, m2ThreshLow; 1068 int m1Thresh, m2Thresh; 1069 int m2CountThr, m2CountThrLow; 1070 int m1ThreshLowExt, m2ThreshLowExt; 1071 int m1ThreshExt, m2ThreshExt; 1072 s32 value, value2; 1073 1074 switch (cmd & ah->ani_function) { 1075 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1076 /* 1077 * on == 1 means ofdm weak signal detection is ON 1078 * on == 1 is the default, for less noise immunity 1079 * 1080 * on == 0 means ofdm weak signal detection is OFF 1081 * on == 0 means more noise imm 1082 */ 1083 u32 on = param ? 1 : 0; 1084 1085 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 1086 goto skip_ws_det; 1087 1088 m1ThreshLow = on ? 1089 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 1090 m2ThreshLow = on ? 1091 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 1092 m1Thresh = on ? 1093 aniState->iniDef.m1Thresh : m1Thresh_off; 1094 m2Thresh = on ? 1095 aniState->iniDef.m2Thresh : m2Thresh_off; 1096 m2CountThr = on ? 1097 aniState->iniDef.m2CountThr : m2CountThr_off; 1098 m2CountThrLow = on ? 1099 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 1100 m1ThreshLowExt = on ? 1101 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 1102 m2ThreshLowExt = on ? 1103 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1104 m1ThreshExt = on ? 1105 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1106 m2ThreshExt = on ? 1107 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1108 1109 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1110 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1111 m1ThreshLow); 1112 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1113 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1114 m2ThreshLow); 1115 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1116 AR_PHY_SFCORR_M1_THRESH, 1117 m1Thresh); 1118 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1119 AR_PHY_SFCORR_M2_THRESH, 1120 m2Thresh); 1121 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1122 AR_PHY_SFCORR_M2COUNT_THR, 1123 m2CountThr); 1124 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1125 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1126 m2CountThrLow); 1127 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1128 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 1129 m1ThreshLowExt); 1130 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1131 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 1132 m2ThreshLowExt); 1133 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1134 AR_PHY_SFCORR_EXT_M1_THRESH, 1135 m1ThreshExt); 1136 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1137 AR_PHY_SFCORR_EXT_M2_THRESH, 1138 m2ThreshExt); 1139 skip_ws_det: 1140 if (on) 1141 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1142 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1143 else 1144 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1145 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1146 1147 if (on != aniState->ofdmWeakSigDetect) { 1148 ath_dbg(common, ANI, 1149 "** ch %d: ofdm weak signal: %s=>%s\n", 1150 chan->channel, 1151 aniState->ofdmWeakSigDetect ? 1152 "on" : "off", 1153 on ? "on" : "off"); 1154 if (on) 1155 ah->stats.ast_ani_ofdmon++; 1156 else 1157 ah->stats.ast_ani_ofdmoff++; 1158 aniState->ofdmWeakSigDetect = on; 1159 } 1160 break; 1161 } 1162 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1163 u32 level = param; 1164 1165 if (level >= ARRAY_SIZE(firstep_table)) { 1166 ath_dbg(common, ANI, 1167 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1168 level, ARRAY_SIZE(firstep_table)); 1169 return false; 1170 } 1171 1172 /* 1173 * make register setting relative to default 1174 * from INI file & cap value 1175 */ 1176 value = firstep_table[level] - 1177 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1178 aniState->iniDef.firstep; 1179 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1180 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1181 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1182 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1183 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1184 AR_PHY_FIND_SIG_FIRSTEP, 1185 value); 1186 /* 1187 * we need to set first step low register too 1188 * make register setting relative to default 1189 * from INI file & cap value 1190 */ 1191 value2 = firstep_table[level] - 1192 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1193 aniState->iniDef.firstepLow; 1194 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1195 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1196 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1197 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1198 1199 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1200 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 1201 1202 if (level != aniState->firstepLevel) { 1203 ath_dbg(common, ANI, 1204 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1205 chan->channel, 1206 aniState->firstepLevel, 1207 level, 1208 ATH9K_ANI_FIRSTEP_LVL, 1209 value, 1210 aniState->iniDef.firstep); 1211 ath_dbg(common, ANI, 1212 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1213 chan->channel, 1214 aniState->firstepLevel, 1215 level, 1216 ATH9K_ANI_FIRSTEP_LVL, 1217 value2, 1218 aniState->iniDef.firstepLow); 1219 if (level > aniState->firstepLevel) 1220 ah->stats.ast_ani_stepup++; 1221 else if (level < aniState->firstepLevel) 1222 ah->stats.ast_ani_stepdown++; 1223 aniState->firstepLevel = level; 1224 } 1225 break; 1226 } 1227 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1228 u32 level = param; 1229 1230 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1231 ath_dbg(common, ANI, 1232 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1233 level, ARRAY_SIZE(cycpwrThr1_table)); 1234 return false; 1235 } 1236 /* 1237 * make register setting relative to default 1238 * from INI file & cap value 1239 */ 1240 value = cycpwrThr1_table[level] - 1241 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1242 aniState->iniDef.cycpwrThr1; 1243 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1244 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1245 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1246 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1247 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1248 AR_PHY_TIMING5_CYCPWR_THR1, 1249 value); 1250 1251 /* 1252 * set AR_PHY_EXT_CCA for extension channel 1253 * make register setting relative to default 1254 * from INI file & cap value 1255 */ 1256 value2 = cycpwrThr1_table[level] - 1257 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1258 aniState->iniDef.cycpwrThr1Ext; 1259 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1260 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1261 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1262 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1263 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1264 AR_PHY_EXT_CYCPWR_THR1, value2); 1265 1266 if (level != aniState->spurImmunityLevel) { 1267 ath_dbg(common, ANI, 1268 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1269 chan->channel, 1270 aniState->spurImmunityLevel, 1271 level, 1272 ATH9K_ANI_SPUR_IMMUNE_LVL, 1273 value, 1274 aniState->iniDef.cycpwrThr1); 1275 ath_dbg(common, ANI, 1276 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1277 chan->channel, 1278 aniState->spurImmunityLevel, 1279 level, 1280 ATH9K_ANI_SPUR_IMMUNE_LVL, 1281 value2, 1282 aniState->iniDef.cycpwrThr1Ext); 1283 if (level > aniState->spurImmunityLevel) 1284 ah->stats.ast_ani_spurup++; 1285 else if (level < aniState->spurImmunityLevel) 1286 ah->stats.ast_ani_spurdown++; 1287 aniState->spurImmunityLevel = level; 1288 } 1289 break; 1290 } 1291 case ATH9K_ANI_MRC_CCK:{ 1292 /* 1293 * is_on == 1 means MRC CCK ON (default, less noise imm) 1294 * is_on == 0 means MRC CCK is OFF (more noise imm) 1295 */ 1296 bool is_on = param ? 1 : 0; 1297 1298 if (ah->caps.rx_chainmask == 1) 1299 break; 1300 1301 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1302 AR_PHY_MRC_CCK_ENABLE, is_on); 1303 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1304 AR_PHY_MRC_CCK_MUX_REG, is_on); 1305 if (is_on != aniState->mrcCCK) { 1306 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 1307 chan->channel, 1308 aniState->mrcCCK ? "on" : "off", 1309 is_on ? "on" : "off"); 1310 if (is_on) 1311 ah->stats.ast_ani_ccklow++; 1312 else 1313 ah->stats.ast_ani_cckhigh++; 1314 aniState->mrcCCK = is_on; 1315 } 1316 break; 1317 } 1318 default: 1319 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1320 return false; 1321 } 1322 1323 ath_dbg(common, ANI, 1324 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1325 aniState->spurImmunityLevel, 1326 aniState->ofdmWeakSigDetect ? "on" : "off", 1327 aniState->firstepLevel, 1328 aniState->mrcCCK ? "on" : "off", 1329 aniState->listenTime, 1330 aniState->ofdmPhyErrCount, 1331 aniState->cckPhyErrCount); 1332 return true; 1333 } 1334 1335 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1336 int16_t nfarray[NUM_NF_READINGS]) 1337 { 1338 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1339 #define AR_PHY_CH_MINCCA_PWR_S 20 1340 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1341 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1342 1343 int16_t nf; 1344 int i; 1345 1346 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1347 if (ah->rxchainmask & BIT(i)) { 1348 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1349 AR_PHY_CH_MINCCA_PWR); 1350 nfarray[i] = sign_extend32(nf, 8); 1351 1352 if (IS_CHAN_HT40(ah->curchan)) { 1353 u8 ext_idx = AR9300_MAX_CHAINS + i; 1354 1355 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1356 AR_PHY_CH_EXT_MINCCA_PWR); 1357 nfarray[ext_idx] = sign_extend32(nf, 8); 1358 } 1359 } 1360 } 1361 } 1362 1363 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1364 { 1365 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1366 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1367 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1368 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1369 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1370 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1371 1372 if (AR_SREV_9330(ah)) 1373 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1374 1375 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1376 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; 1377 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; 1378 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; 1379 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; 1380 } 1381 } 1382 1383 /* 1384 * Initialize the ANI register values with default (ini) values. 1385 * This routine is called during a (full) hardware reset after 1386 * all the registers are initialised from the INI. 1387 */ 1388 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1389 { 1390 struct ar5416AniState *aniState; 1391 struct ath_common *common = ath9k_hw_common(ah); 1392 struct ath9k_channel *chan = ah->curchan; 1393 struct ath9k_ani_default *iniDef; 1394 u32 val; 1395 1396 aniState = &ah->ani; 1397 iniDef = &aniState->iniDef; 1398 1399 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1400 ah->hw_version.macVersion, 1401 ah->hw_version.macRev, 1402 ah->opmode, 1403 chan->channel); 1404 1405 val = REG_READ(ah, AR_PHY_SFCORR); 1406 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1407 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1408 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1409 1410 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1411 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1412 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1413 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1414 1415 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1416 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1417 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1418 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1419 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1420 iniDef->firstep = REG_READ_FIELD(ah, 1421 AR_PHY_FIND_SIG, 1422 AR_PHY_FIND_SIG_FIRSTEP); 1423 iniDef->firstepLow = REG_READ_FIELD(ah, 1424 AR_PHY_FIND_SIG_LOW, 1425 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1426 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1427 AR_PHY_TIMING5, 1428 AR_PHY_TIMING5_CYCPWR_THR1); 1429 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1430 AR_PHY_EXT_CCA, 1431 AR_PHY_EXT_CYCPWR_THR1); 1432 1433 /* these levels just got reset to defaults by the INI */ 1434 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1435 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1436 aniState->ofdmWeakSigDetect = true; 1437 aniState->mrcCCK = true; 1438 } 1439 1440 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1441 struct ath_hw_radar_conf *conf) 1442 { 1443 unsigned int regWrites = 0; 1444 u32 radar_0 = 0, radar_1; 1445 1446 if (!conf) { 1447 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1448 return; 1449 } 1450 1451 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1452 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1453 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1454 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1455 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1456 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1457 1458 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1459 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1460 AR_PHY_RADAR_1_RELPWR_THRESH); 1461 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1462 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1463 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1464 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1465 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1466 1467 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1468 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1469 if (conf->ext_channel) 1470 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1471 else 1472 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1473 1474 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { 1475 REG_WRITE_ARRAY(&ah->ini_dfs, 1476 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); 1477 } 1478 } 1479 1480 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1481 { 1482 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1483 1484 conf->fir_power = -28; 1485 conf->radar_rssi = 0; 1486 conf->pulse_height = 10; 1487 conf->pulse_rssi = 15; 1488 conf->pulse_inband = 8; 1489 conf->pulse_maxlen = 255; 1490 conf->pulse_inband_step = 12; 1491 conf->radar_inband = 8; 1492 } 1493 1494 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1495 struct ath_hw_antcomb_conf *antconf) 1496 { 1497 u32 regval; 1498 1499 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1500 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> 1501 AR_PHY_ANT_DIV_MAIN_LNACONF_S; 1502 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> 1503 AR_PHY_ANT_DIV_ALT_LNACONF_S; 1504 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> 1505 AR_PHY_ANT_FAST_DIV_BIAS_S; 1506 1507 if (AR_SREV_9330_11(ah)) { 1508 antconf->lna1_lna2_switch_delta = -1; 1509 antconf->lna1_lna2_delta = -9; 1510 antconf->div_group = 1; 1511 } else if (AR_SREV_9485(ah)) { 1512 antconf->lna1_lna2_switch_delta = -1; 1513 antconf->lna1_lna2_delta = -9; 1514 antconf->div_group = 2; 1515 } else if (AR_SREV_9565(ah)) { 1516 antconf->lna1_lna2_switch_delta = 3; 1517 antconf->lna1_lna2_delta = -9; 1518 antconf->div_group = 3; 1519 } else { 1520 antconf->lna1_lna2_switch_delta = -1; 1521 antconf->lna1_lna2_delta = -3; 1522 antconf->div_group = 0; 1523 } 1524 } 1525 1526 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1527 struct ath_hw_antcomb_conf *antconf) 1528 { 1529 u32 regval; 1530 1531 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1532 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1533 AR_PHY_ANT_DIV_ALT_LNACONF | 1534 AR_PHY_ANT_FAST_DIV_BIAS | 1535 AR_PHY_ANT_DIV_MAIN_GAINTB | 1536 AR_PHY_ANT_DIV_ALT_GAINTB); 1537 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) 1538 & AR_PHY_ANT_DIV_MAIN_LNACONF); 1539 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) 1540 & AR_PHY_ANT_DIV_ALT_LNACONF); 1541 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) 1542 & AR_PHY_ANT_FAST_DIV_BIAS); 1543 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) 1544 & AR_PHY_ANT_DIV_MAIN_GAINTB); 1545 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) 1546 & AR_PHY_ANT_DIV_ALT_GAINTB); 1547 1548 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1549 } 1550 1551 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1552 1553 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) 1554 { 1555 struct ath9k_hw_capabilities *pCap = &ah->caps; 1556 u8 ant_div_ctl1; 1557 u32 regval; 1558 1559 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 1560 return; 1561 1562 if (AR_SREV_9485(ah)) { 1563 regval = ar9003_hw_ant_ctrl_common_2_get(ah, 1564 IS_CHAN_2GHZ(ah->curchan)); 1565 if (enable) { 1566 regval &= ~AR_SWITCH_TABLE_COM2_ALL; 1567 regval |= ah->config.ant_ctrl_comm2g_switch_enable; 1568 } 1569 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, 1570 AR_SWITCH_TABLE_COM2_ALL, regval); 1571 } 1572 1573 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1574 1575 /* 1576 * Set MAIN/ALT LNA conf. 1577 * Set MAIN/ALT gain_tb. 1578 */ 1579 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1580 regval &= (~AR_ANT_DIV_CTRL_ALL); 1581 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 1582 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1583 1584 if (AR_SREV_9485_11_OR_LATER(ah)) { 1585 /* 1586 * Enable LNA diversity. 1587 */ 1588 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1589 regval &= ~AR_PHY_ANT_DIV_LNADIV; 1590 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; 1591 if (enable) 1592 regval |= AR_ANT_DIV_ENABLE; 1593 1594 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1595 1596 /* 1597 * Enable fast antenna diversity. 1598 */ 1599 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 1600 regval &= ~AR_FAST_DIV_ENABLE; 1601 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; 1602 if (enable) 1603 regval |= AR_FAST_DIV_ENABLE; 1604 1605 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 1606 1607 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { 1608 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1609 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1610 AR_PHY_ANT_DIV_ALT_LNACONF | 1611 AR_PHY_ANT_DIV_ALT_GAINTB | 1612 AR_PHY_ANT_DIV_MAIN_GAINTB)); 1613 /* 1614 * Set MAIN to LNA1 and ALT to LNA2 at the 1615 * beginning. 1616 */ 1617 regval |= (ATH_ANT_DIV_COMB_LNA1 << 1618 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1619 regval |= (ATH_ANT_DIV_COMB_LNA2 << 1620 AR_PHY_ANT_DIV_ALT_LNACONF_S); 1621 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1622 } 1623 } else if (AR_SREV_9565(ah)) { 1624 if (enable) { 1625 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1626 AR_ANT_DIV_ENABLE); 1627 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1628 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1629 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 1630 AR_FAST_DIV_ENABLE); 1631 REG_SET_BIT(ah, AR_PHY_RESTART, 1632 AR_PHY_RESTART_ENABLE_DIV_M2FLAG); 1633 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, 1634 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1635 } else { 1636 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1637 AR_ANT_DIV_ENABLE); 1638 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1639 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1640 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, 1641 AR_FAST_DIV_ENABLE); 1642 REG_CLR_BIT(ah, AR_PHY_RESTART, 1643 AR_PHY_RESTART_ENABLE_DIV_M2FLAG); 1644 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, 1645 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1646 1647 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1648 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1649 AR_PHY_ANT_DIV_ALT_LNACONF | 1650 AR_PHY_ANT_DIV_MAIN_GAINTB | 1651 AR_PHY_ANT_DIV_ALT_GAINTB); 1652 regval |= (ATH_ANT_DIV_COMB_LNA1 << 1653 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1654 regval |= (ATH_ANT_DIV_COMB_LNA2 << 1655 AR_PHY_ANT_DIV_ALT_LNACONF_S); 1656 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1657 } 1658 } 1659 } 1660 1661 #endif 1662 1663 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1664 struct ath9k_channel *chan, 1665 u8 *ini_reloaded) 1666 { 1667 unsigned int regWrites = 0; 1668 u32 modesIndex, txgain_index; 1669 1670 if (IS_CHAN_5GHZ(chan)) 1671 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 1672 else 1673 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 1674 1675 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; 1676 1677 if (modesIndex == ah->modes_index) { 1678 *ini_reloaded = false; 1679 goto set_rfmode; 1680 } 1681 1682 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1683 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1684 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1685 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1686 1687 if (AR_SREV_9462_20_OR_LATER(ah)) 1688 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, 1689 modesIndex); 1690 1691 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); 1692 1693 if (AR_SREV_9462_20_OR_LATER(ah)) { 1694 /* 1695 * CUS217 mix LNA mode. 1696 */ 1697 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { 1698 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, 1699 1, regWrites); 1700 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 1701 modesIndex, regWrites); 1702 } 1703 } 1704 1705 /* 1706 * For 5GHz channels requiring Fast Clock, apply 1707 * different modal values. 1708 */ 1709 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1710 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); 1711 1712 if (AR_SREV_9565(ah)) 1713 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); 1714 1715 /* 1716 * JAPAN regulatory. 1717 */ 1718 if (chan->channel == 2484) 1719 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); 1720 1721 ah->modes_index = modesIndex; 1722 *ini_reloaded = true; 1723 1724 set_rfmode: 1725 ar9003_hw_set_rfmode(ah, chan); 1726 return 0; 1727 } 1728 1729 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, 1730 struct ath_spec_scan *param) 1731 { 1732 u8 count; 1733 1734 if (!param->enabled) { 1735 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1736 AR_PHY_SPECTRAL_SCAN_ENABLE); 1737 return; 1738 } 1739 1740 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); 1741 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); 1742 1743 /* on AR93xx and newer, count = 0 will make the the chip send 1744 * spectral samples endlessly. Check if this really was intended, 1745 * and fix otherwise. 1746 */ 1747 count = param->count; 1748 if (param->endless) 1749 count = 0; 1750 else if (param->count == 0) 1751 count = 1; 1752 1753 if (param->short_repeat) 1754 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1755 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1756 else 1757 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1758 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1759 1760 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1761 AR_PHY_SPECTRAL_SCAN_COUNT, count); 1762 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1763 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); 1764 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1765 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); 1766 1767 return; 1768 } 1769 1770 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) 1771 { 1772 /* Activate spectral scan */ 1773 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1774 AR_PHY_SPECTRAL_SCAN_ACTIVE); 1775 } 1776 1777 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) 1778 { 1779 struct ath_common *common = ath9k_hw_common(ah); 1780 1781 /* Poll for spectral scan complete */ 1782 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, 1783 AR_PHY_SPECTRAL_SCAN_ACTIVE, 1784 0, AH_WAIT_TIMEOUT)) { 1785 ath_err(common, "spectral scan wait failed\n"); 1786 return; 1787 } 1788 } 1789 1790 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) 1791 { 1792 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); 1793 REG_SET_BIT(ah, 0x9864, 0x7f000); 1794 REG_SET_BIT(ah, 0x9924, 0x7f00fe); 1795 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 1796 REG_WRITE(ah, AR_CR, AR_CR_RXD); 1797 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 1798 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 1799 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 1800 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 1801 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 1802 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); 1803 } 1804 1805 static void ar9003_hw_tx99_stop(struct ath_hw *ah) 1806 { 1807 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); 1808 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 1809 } 1810 1811 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) 1812 { 1813 static s16 p_pwr_array[ar9300RateSize] = { 0 }; 1814 unsigned int i; 1815 1816 if (txpower <= MAX_RATE_POWER) { 1817 for (i = 0; i < ar9300RateSize; i++) 1818 p_pwr_array[i] = txpower; 1819 } else { 1820 for (i = 0; i < ar9300RateSize; i++) 1821 p_pwr_array[i] = MAX_RATE_POWER; 1822 } 1823 1824 REG_WRITE(ah, 0xa458, 0); 1825 1826 REG_WRITE(ah, 0xa3c0, 1827 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) | 1828 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) | 1829 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) | 1830 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)); 1831 REG_WRITE(ah, 0xa3c4, 1832 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) | 1833 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) | 1834 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) | 1835 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)); 1836 REG_WRITE(ah, 0xa3c8, 1837 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) | 1838 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) | 1839 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)); 1840 REG_WRITE(ah, 0xa3cc, 1841 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) | 1842 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) | 1843 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) | 1844 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)); 1845 REG_WRITE(ah, 0xa3d0, 1846 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) | 1847 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) | 1848 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)| 1849 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)); 1850 REG_WRITE(ah, 0xa3d4, 1851 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) | 1852 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) | 1853 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) | 1854 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0)); 1855 REG_WRITE(ah, 0xa3e4, 1856 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) | 1857 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) | 1858 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) | 1859 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0)); 1860 REG_WRITE(ah, 0xa3e8, 1861 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) | 1862 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) | 1863 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) | 1864 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0)); 1865 REG_WRITE(ah, 0xa3d8, 1866 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) | 1867 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) | 1868 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | 1869 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)); 1870 REG_WRITE(ah, 0xa3dc, 1871 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) | 1872 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) | 1873 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) | 1874 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0)); 1875 REG_WRITE(ah, 0xa3ec, 1876 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) | 1877 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) | 1878 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) | 1879 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0)); 1880 } 1881 1882 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) 1883 { 1884 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; 1885 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; 1886 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], 1887 rate_array[ALL_TARGET_LEGACY_5S]); 1888 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], 1889 rate_array[ALL_TARGET_LEGACY_11S]); 1890 } 1891 1892 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, 1893 int offset) 1894 { 1895 int i, j; 1896 1897 for (i = offset; i < offset + AR9300_OFDM_RATES; i++) { 1898 /* OFDM rate to power table idx */ 1899 j = ofdm2pwr[i - offset]; 1900 ah->tx_power[i] = rate_array[j]; 1901 } 1902 } 1903 1904 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, 1905 int ss_offset, int ds_offset, 1906 int ts_offset, bool is_40) 1907 { 1908 int i, j, mcs_idx = 0; 1909 const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20; 1910 1911 for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) { 1912 j = mcs2pwr[mcs_idx]; 1913 ah->tx_power[i] = rate_array[j]; 1914 mcs_idx++; 1915 } 1916 1917 for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) { 1918 j = mcs2pwr[mcs_idx]; 1919 ah->tx_power[i] = rate_array[j]; 1920 mcs_idx++; 1921 } 1922 1923 for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) { 1924 j = mcs2pwr[mcs_idx]; 1925 ah->tx_power[i] = rate_array[j]; 1926 mcs_idx++; 1927 } 1928 } 1929 1930 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, 1931 int ds_offset, int ts_offset) 1932 { 1933 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], 1934 AR9300_HT_SS_RATES); 1935 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], 1936 AR9300_HT_DS_RATES); 1937 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], 1938 AR9300_HT_TS_RATES); 1939 } 1940 1941 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, 1942 struct ath9k_channel *chan) 1943 { 1944 if (IS_CHAN_5GHZ(chan)) { 1945 ar9003_hw_init_txpower_ofdm(ah, rate_array, 1946 AR9300_11NA_OFDM_SHIFT); 1947 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1948 ar9003_hw_init_txpower_ht(ah, rate_array, 1949 AR9300_11NA_HT_SS_SHIFT, 1950 AR9300_11NA_HT_DS_SHIFT, 1951 AR9300_11NA_HT_TS_SHIFT, 1952 IS_CHAN_HT40(chan)); 1953 ar9003_hw_init_txpower_stbc(ah, 1954 AR9300_11NA_HT_SS_SHIFT, 1955 AR9300_11NA_HT_DS_SHIFT, 1956 AR9300_11NA_HT_TS_SHIFT); 1957 } 1958 } else { 1959 ar9003_hw_init_txpower_cck(ah, rate_array); 1960 ar9003_hw_init_txpower_ofdm(ah, rate_array, 1961 AR9300_11NG_OFDM_SHIFT); 1962 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1963 ar9003_hw_init_txpower_ht(ah, rate_array, 1964 AR9300_11NG_HT_SS_SHIFT, 1965 AR9300_11NG_HT_DS_SHIFT, 1966 AR9300_11NG_HT_TS_SHIFT, 1967 IS_CHAN_HT40(chan)); 1968 ar9003_hw_init_txpower_stbc(ah, 1969 AR9300_11NG_HT_SS_SHIFT, 1970 AR9300_11NG_HT_DS_SHIFT, 1971 AR9300_11NG_HT_TS_SHIFT); 1972 } 1973 } 1974 } 1975 1976 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1977 { 1978 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1979 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1980 static const u32 ar9300_cca_regs[6] = { 1981 AR_PHY_CCA_0, 1982 AR_PHY_CCA_1, 1983 AR_PHY_CCA_2, 1984 AR_PHY_EXT_CCA, 1985 AR_PHY_EXT_CCA_1, 1986 AR_PHY_EXT_CCA_2, 1987 }; 1988 1989 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1990 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1991 1992 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1993 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; 1994 else 1995 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1996 1997 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1998 priv_ops->init_bb = ar9003_hw_init_bb; 1999 priv_ops->process_ini = ar9003_hw_process_ini; 2000 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 2001 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 2002 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 2003 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 2004 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 2005 priv_ops->ani_control = ar9003_hw_ani_control; 2006 priv_ops->do_getnf = ar9003_hw_do_getnf; 2007 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 2008 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 2009 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 2010 2011 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 2012 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 2013 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; 2014 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; 2015 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; 2016 2017 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 2018 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; 2019 #endif 2020 ops->tx99_start = ar9003_hw_tx99_start; 2021 ops->tx99_stop = ar9003_hw_tx99_stop; 2022 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; 2023 2024 ar9003_hw_set_nf_limits(ah); 2025 ar9003_hw_set_radar_conf(ah); 2026 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 2027 } 2028 2029 /* 2030 * Baseband Watchdog signatures: 2031 * 2032 * 0x04000539: BB hang when operating in HT40 DFS Channel. 2033 * Full chip reset is not required, but a recovery 2034 * mechanism is needed. 2035 * 2036 * 0x1300000a: Related to CAC deafness. 2037 * Chip reset is not required. 2038 * 2039 * 0x0400000a: Related to CAC deafness. 2040 * Full chip reset is required. 2041 * 2042 * 0x04000b09: RX state machine gets into an illegal state 2043 * when a packet with unsupported rate is received. 2044 * Full chip reset is required and PHY_RESTART has 2045 * to be disabled. 2046 * 2047 * 0x04000409: Packet stuck on receive. 2048 * Full chip reset is required for all chips except AR9340. 2049 */ 2050 2051 /* 2052 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required. 2053 */ 2054 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) 2055 { 2056 u32 val; 2057 2058 switch(ah->bb_watchdog_last_status) { 2059 case 0x04000539: 2060 val = REG_READ(ah, AR_PHY_RADAR_0); 2061 val &= (~AR_PHY_RADAR_0_FIRPWR); 2062 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); 2063 REG_WRITE(ah, AR_PHY_RADAR_0, val); 2064 udelay(1); 2065 val = REG_READ(ah, AR_PHY_RADAR_0); 2066 val &= ~AR_PHY_RADAR_0_FIRPWR; 2067 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); 2068 REG_WRITE(ah, AR_PHY_RADAR_0, val); 2069 2070 return false; 2071 case 0x1300000a: 2072 return false; 2073 case 0x0400000a: 2074 case 0x04000b09: 2075 return true; 2076 case 0x04000409: 2077 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) 2078 return false; 2079 else 2080 return true; 2081 default: 2082 /* 2083 * For any other unknown signatures, do a 2084 * full chip reset. 2085 */ 2086 return true; 2087 } 2088 } 2089 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check); 2090 2091 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 2092 { 2093 struct ath_common *common = ath9k_hw_common(ah); 2094 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 2095 u32 val, idle_count; 2096 2097 if (!idle_tmo_ms) { 2098 /* disable IRQ, disable chip-reset for BB panic */ 2099 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 2100 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 2101 ~(AR_PHY_WATCHDOG_RST_ENABLE | 2102 AR_PHY_WATCHDOG_IRQ_ENABLE)); 2103 2104 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 2105 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 2106 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 2107 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 2108 AR_PHY_WATCHDOG_IDLE_ENABLE)); 2109 2110 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); 2111 return; 2112 } 2113 2114 /* enable IRQ, disable chip-reset for BB watchdog */ 2115 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 2116 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 2117 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 2118 ~AR_PHY_WATCHDOG_RST_ENABLE); 2119 2120 /* bound limit to 10 secs */ 2121 if (idle_tmo_ms > 10000) 2122 idle_tmo_ms = 10000; 2123 2124 /* 2125 * The time unit for watchdog event is 2^15 44/88MHz cycles. 2126 * 2127 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 2128 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 2129 * 2130 * Given we use fast clock now in 5 GHz, these time units should 2131 * be common for both 2 GHz and 5 GHz. 2132 */ 2133 idle_count = (100 * idle_tmo_ms) / 74; 2134 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 2135 idle_count = (100 * idle_tmo_ms) / 37; 2136 2137 /* 2138 * enable watchdog in non-IDLE mode, disable in IDLE mode, 2139 * set idle time-out. 2140 */ 2141 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 2142 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 2143 AR_PHY_WATCHDOG_IDLE_MASK | 2144 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 2145 2146 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", 2147 idle_tmo_ms); 2148 } 2149 2150 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 2151 { 2152 /* 2153 * we want to avoid printing in ISR context so we save the 2154 * watchdog status to be printed later in bottom half context. 2155 */ 2156 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 2157 2158 /* 2159 * the watchdog timer should reset on status read but to be sure 2160 * sure we write 0 to the watchdog status bit. 2161 */ 2162 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 2163 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 2164 } 2165 2166 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 2167 { 2168 struct ath_common *common = ath9k_hw_common(ah); 2169 u32 status; 2170 2171 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 2172 return; 2173 2174 status = ah->bb_watchdog_last_status; 2175 ath_dbg(common, RESET, 2176 "\n==== BB update: BB status=0x%08x ====\n", status); 2177 ath_dbg(common, RESET, 2178 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 2179 MS(status, AR_PHY_WATCHDOG_INFO), 2180 MS(status, AR_PHY_WATCHDOG_DET_HANG), 2181 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 2182 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 2183 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 2184 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 2185 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 2186 MS(status, AR_PHY_WATCHDOG_AGC_SM), 2187 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 2188 2189 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 2190 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 2191 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 2192 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", 2193 REG_READ(ah, AR_PHY_GEN_CTRL)); 2194 2195 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 2196 if (common->cc_survey.cycles) 2197 ath_dbg(common, RESET, 2198 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 2199 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 2200 2201 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); 2202 } 2203 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 2204 2205 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 2206 { 2207 u8 result; 2208 u32 val; 2209 2210 /* While receiving unsupported rate frame rx state machine 2211 * gets into a state 0xb and if phy_restart happens in that 2212 * state, BB would go hang. If RXSM is in 0xb state after 2213 * first bb panic, ensure to disable the phy_restart. 2214 */ 2215 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); 2216 2217 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { 2218 ah->bb_hang_rx_ofdm = true; 2219 val = REG_READ(ah, AR_PHY_RESTART); 2220 val &= ~AR_PHY_RESTART_ENA; 2221 REG_WRITE(ah, AR_PHY_RESTART, val); 2222 } 2223 } 2224 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 2225