1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 21 static const int firstep_table[] = 22 /* level: 0 1 2 3 4 5 6 7 8 */ 23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 24 25 static const int cycpwrThr1_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 28 29 /* 30 * register values to turn OFDM weak signal detection OFF 31 */ 32 static const int m1ThreshLow_off = 127; 33 static const int m2ThreshLow_off = 127; 34 static const int m1Thresh_off = 127; 35 static const int m2Thresh_off = 127; 36 static const int m2CountThr_off = 31; 37 static const int m2CountThrLow_off = 63; 38 static const int m1ThreshLowExt_off = 127; 39 static const int m2ThreshLowExt_off = 127; 40 static const int m1ThreshExt_off = 127; 41 static const int m2ThreshExt_off = 127; 42 43 /** 44 * ar9003_hw_set_channel - set channel on single-chip device 45 * @ah: atheros hardware structure 46 * @chan: 47 * 48 * This is the function to change channel on single-chip devices, that is 49 * for AR9300 family of chipsets. 50 * 51 * This function takes the channel value in MHz and sets 52 * hardware channel value. Assumes writes have been enabled to analog bus. 53 * 54 * Actual Expression, 55 * 56 * For 2GHz channel, 57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 58 * (freq_ref = 40MHz) 59 * 60 * For 5GHz channel, 61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 62 * (freq_ref = 40MHz/(24>>amodeRefSel)) 63 * 64 * For 5GHz channels which are 5MHz spaced, 65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 66 * (freq_ref = 40MHz) 67 */ 68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 69 { 70 u16 bMode, fracMode = 0, aModeRefSel = 0; 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; 72 struct chan_centers centers; 73 int loadSynthChannel; 74 75 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 76 freq = centers.synth_center; 77 78 if (freq < 4800) { /* 2 GHz, fractional mode */ 79 if (AR_SREV_9330(ah)) { 80 if (ah->is_clk_25mhz) 81 div = 75; 82 else 83 div = 120; 84 85 channelSel = (freq * 4) / div; 86 chan_frac = (((freq * 4) % div) * 0x20000) / div; 87 channelSel = (channelSel << 17) | chan_frac; 88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 89 /* 90 * freq_ref = 40 / (refdiva >> amoderefsel); 91 * where refdiva=1 and amoderefsel=0 92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 94 */ 95 channelSel = (freq * 4) / 120; 96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 97 channelSel = (channelSel << 17) | chan_frac; 98 } else if (AR_SREV_9340(ah)) { 99 if (ah->is_clk_25mhz) { 100 channelSel = (freq * 2) / 75; 101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 102 channelSel = (channelSel << 17) | chan_frac; 103 } else { 104 channelSel = CHANSEL_2G(freq) >> 1; 105 } 106 } else if (AR_SREV_9550(ah)) { 107 if (ah->is_clk_25mhz) 108 div = 75; 109 else 110 div = 120; 111 112 channelSel = (freq * 4) / div; 113 chan_frac = (((freq * 4) % div) * 0x20000) / div; 114 channelSel = (channelSel << 17) | chan_frac; 115 } else { 116 channelSel = CHANSEL_2G(freq); 117 } 118 /* Set to 2G mode */ 119 bMode = 1; 120 } else { 121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) && 122 ah->is_clk_25mhz) { 123 channelSel = freq / 75; 124 chan_frac = ((freq % 75) * 0x20000) / 75; 125 channelSel = (channelSel << 17) | chan_frac; 126 } else { 127 channelSel = CHANSEL_5G(freq); 128 /* Doubler is ON, so, divide channelSel by 2. */ 129 channelSel >>= 1; 130 } 131 /* Set to 5G mode */ 132 bMode = 0; 133 } 134 135 /* Enable fractional mode for all channels */ 136 fracMode = 1; 137 aModeRefSel = 0; 138 loadSynthChannel = 0; 139 140 reg32 = (bMode << 29); 141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 142 143 /* Enable Long shift Select for Synthesizer */ 144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 146 147 /* Program Synth. setting */ 148 reg32 = (channelSel << 2) | (fracMode << 30) | 149 (aModeRefSel << 28) | (loadSynthChannel << 31); 150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 151 152 /* Toggle Load Synth channel bit */ 153 loadSynthChannel = 1; 154 reg32 = (channelSel << 2) | (fracMode << 30) | 155 (aModeRefSel << 28) | (loadSynthChannel << 31); 156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 157 158 ah->curchan = chan; 159 160 return 0; 161 } 162 163 /** 164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 165 * @ah: atheros hardware structure 166 * @chan: 167 * 168 * For single-chip solutions. Converts to baseband spur frequency given the 169 * input channel frequency and compute register settings below. 170 * 171 * Spur mitigation for MRC CCK 172 */ 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 174 struct ath9k_channel *chan) 175 { 176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 177 int cur_bb_spur, negative = 0, cck_spur_freq; 178 int i; 179 int range, max_spur_cnts, synth_freq; 180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); 181 182 /* 183 * Need to verify range +/- 10 MHz in control channel, otherwise spur 184 * is out-of-band and can be ignored. 185 */ 186 187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 188 AR_SREV_9550(ah)) { 189 if (spur_fbin_ptr[0] == 0) /* No spur */ 190 return; 191 max_spur_cnts = 5; 192 if (IS_CHAN_HT40(chan)) { 193 range = 19; 194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 195 AR_PHY_GC_DYN2040_PRI_CH) == 0) 196 synth_freq = chan->channel + 10; 197 else 198 synth_freq = chan->channel - 10; 199 } else { 200 range = 10; 201 synth_freq = chan->channel; 202 } 203 } else { 204 range = AR_SREV_9462(ah) ? 5 : 10; 205 max_spur_cnts = 4; 206 synth_freq = chan->channel; 207 } 208 209 for (i = 0; i < max_spur_cnts; i++) { 210 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 211 continue; 212 213 negative = 0; 214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 215 AR_SREV_9550(ah)) 216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], 217 IS_CHAN_2GHZ(chan)); 218 else 219 cur_bb_spur = spur_freq[i]; 220 221 cur_bb_spur -= synth_freq; 222 if (cur_bb_spur < 0) { 223 negative = 1; 224 cur_bb_spur = -cur_bb_spur; 225 } 226 if (cur_bb_spur < range) { 227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 228 229 if (negative == 1) 230 cck_spur_freq = -cck_spur_freq; 231 232 cck_spur_freq = cck_spur_freq & 0xfffff; 233 234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 240 0x2); 241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 243 0x1); 244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 246 cck_spur_freq); 247 248 return; 249 } 250 } 251 252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 258 } 259 260 /* Clean all spur register fields */ 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 262 { 263 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 265 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 267 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 271 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 273 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 275 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 281 282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 284 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 286 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 302 } 303 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 305 int freq_offset, 306 int spur_freq_sd, 307 int spur_delta_phase, 308 int spur_subchannel_sd, 309 int range, 310 int synth_freq) 311 { 312 int mask_index = 0; 313 314 /* OFDM Spur mitigation */ 315 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 317 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 319 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 323 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 325 326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) 327 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 329 330 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 336 337 if (!AR_SREV_9340(ah) && 338 REG_READ_FIELD(ah, AR_PHY_MODE, 339 AR_PHY_MODE_DYNAMIC) == 0x1) 340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 342 343 mask_index = (freq_offset << 4) / 5; 344 if (mask_index < 0) 345 mask_index = mask_index - 1; 346 347 mask_index = mask_index & 0x7f; 348 349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 353 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 369 } 370 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, 372 int freq_offset) 373 { 374 int mask_index = 0; 375 376 mask_index = (freq_offset << 4) / 5; 377 if (mask_index < 0) 378 mask_index = mask_index - 1; 379 380 mask_index = mask_index & 0x7f; 381 382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B, 384 mask_index); 385 386 /* A == B */ 387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 389 mask_index); 390 391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B, 393 mask_index); 394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe); 396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe); 398 399 /* A == B */ 400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 402 } 403 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 405 struct ath9k_channel *chan, 406 int freq_offset, 407 int range, 408 int synth_freq) 409 { 410 int spur_freq_sd = 0; 411 int spur_subchannel_sd = 0; 412 int spur_delta_phase = 0; 413 414 if (IS_CHAN_HT40(chan)) { 415 if (freq_offset < 0) { 416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 418 spur_subchannel_sd = 1; 419 else 420 spur_subchannel_sd = 0; 421 422 spur_freq_sd = ((freq_offset + 10) << 9) / 11; 423 424 } else { 425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 427 spur_subchannel_sd = 0; 428 else 429 spur_subchannel_sd = 1; 430 431 spur_freq_sd = ((freq_offset - 10) << 9) / 11; 432 433 } 434 435 spur_delta_phase = (freq_offset << 17) / 5; 436 437 } else { 438 spur_subchannel_sd = 0; 439 spur_freq_sd = (freq_offset << 9) /11; 440 spur_delta_phase = (freq_offset << 18) / 5; 441 } 442 443 spur_freq_sd = spur_freq_sd & 0x3ff; 444 spur_delta_phase = spur_delta_phase & 0xfffff; 445 446 ar9003_hw_spur_ofdm(ah, 447 freq_offset, 448 spur_freq_sd, 449 spur_delta_phase, 450 spur_subchannel_sd, 451 range, synth_freq); 452 } 453 454 /* Spur mitigation for OFDM */ 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 456 struct ath9k_channel *chan) 457 { 458 int synth_freq; 459 int range = 10; 460 int freq_offset = 0; 461 int mode; 462 u8* spurChansPtr; 463 unsigned int i; 464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 465 466 if (IS_CHAN_5GHZ(chan)) { 467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 468 mode = 0; 469 } 470 else { 471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 472 mode = 1; 473 } 474 475 if (spurChansPtr[0] == 0) 476 return; /* No spur in the mode */ 477 478 if (IS_CHAN_HT40(chan)) { 479 range = 19; 480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 482 synth_freq = chan->channel - 10; 483 else 484 synth_freq = chan->channel + 10; 485 } else { 486 range = 10; 487 synth_freq = chan->channel; 488 } 489 490 ar9003_hw_spur_ofdm_clear(ah); 491 492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode); 494 freq_offset -= synth_freq; 495 if (abs(freq_offset) < range) { 496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, 497 range, synth_freq); 498 499 if (AR_SREV_9565(ah) && (i < 4)) { 500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1], 501 mode); 502 freq_offset -= synth_freq; 503 if (abs(freq_offset) < range) 504 ar9003_hw_spur_ofdm_9565(ah, freq_offset); 505 } 506 507 break; 508 } 509 } 510 } 511 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 513 struct ath9k_channel *chan) 514 { 515 if (!AR_SREV_9565(ah)) 516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 517 ar9003_hw_spur_mitigate_ofdm(ah, chan); 518 } 519 520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 521 struct ath9k_channel *chan) 522 { 523 u32 pll; 524 525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 526 527 if (chan && IS_CHAN_HALF_RATE(chan)) 528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 529 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 531 532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 533 534 return pll; 535 } 536 537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 538 struct ath9k_channel *chan) 539 { 540 u32 phymode; 541 u32 enableDacFifo = 0; 542 543 enableDacFifo = 544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 545 546 /* Enable 11n HT, 20 MHz */ 547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 549 550 /* Configure baseband for dynamic 20/40 operation */ 551 if (IS_CHAN_HT40(chan)) { 552 phymode |= AR_PHY_GC_DYN2040_EN; 553 /* Configure control (primary) channel at +-10MHz */ 554 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 555 (chan->chanmode == CHANNEL_G_HT40PLUS)) 556 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 557 558 } 559 560 /* make sure we preserve INI settings */ 561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 562 /* turn off Green Field detection for STA for now */ 563 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 564 565 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 566 567 /* Configure MAC for 20/40 operation */ 568 ath9k_hw_set11nmac2040(ah); 569 570 /* global transmit timeout (25 TUs default)*/ 571 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 572 /* carrier sense timeout */ 573 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 574 } 575 576 static void ar9003_hw_init_bb(struct ath_hw *ah, 577 struct ath9k_channel *chan) 578 { 579 u32 synthDelay; 580 581 /* 582 * Wait for the frequency synth to settle (synth goes on 583 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 584 * Value is in 100ns increments. 585 */ 586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 587 588 /* Activate the PHY (includes baseband activate + synthesizer on) */ 589 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 590 ath9k_hw_synth_delay(ah, chan, synthDelay); 591 } 592 593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 594 { 595 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) 596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 597 AR_PHY_SWAP_ALT_CHAIN); 598 599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 601 602 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 603 tx = 3; 604 605 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 606 } 607 608 /* 609 * Override INI values with chip specific configuration. 610 */ 611 static void ar9003_hw_override_ini(struct ath_hw *ah) 612 { 613 u32 val; 614 615 /* 616 * Set the RX_ABORT and RX_DIS and clear it only after 617 * RXE is set for MAC. This prevents frames with 618 * corrupted descriptor status. 619 */ 620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 621 622 /* 623 * For AR9280 and above, there is a new feature that allows 624 * Multicast search based on both MAC Address and Key ID. By default, 625 * this feature is enabled. But since the driver is not using this 626 * feature, we switch it off; otherwise multicast search based on 627 * MAC addr only will fail. 628 */ 629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 630 REG_WRITE(ah, AR_PCU_MISC_MODE2, 631 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); 632 633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 634 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 635 } 636 637 static void ar9003_hw_prog_ini(struct ath_hw *ah, 638 struct ar5416IniArray *iniArr, 639 int column) 640 { 641 unsigned int i, regWrites = 0; 642 643 /* New INI format: Array may be undefined (pre, core, post arrays) */ 644 if (!iniArr->ia_array) 645 return; 646 647 /* 648 * New INI format: Pre, core, and post arrays for a given subsystem 649 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 650 * the array is non-modal and force the column to 1. 651 */ 652 if (column >= iniArr->ia_columns) 653 column = 1; 654 655 for (i = 0; i < iniArr->ia_rows; i++) { 656 u32 reg = INI_RA(iniArr, i, 0); 657 u32 val = INI_RA(iniArr, i, column); 658 659 REG_WRITE(ah, reg, val); 660 661 DO_DELAY(regWrites); 662 } 663 } 664 665 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, 666 struct ath9k_channel *chan) 667 { 668 int ret; 669 670 switch (chan->chanmode) { 671 case CHANNEL_A: 672 case CHANNEL_A_HT20: 673 if (chan->channel <= 5350) 674 ret = 1; 675 else if ((chan->channel > 5350) && (chan->channel <= 5600)) 676 ret = 3; 677 else 678 ret = 5; 679 break; 680 681 case CHANNEL_A_HT40PLUS: 682 case CHANNEL_A_HT40MINUS: 683 if (chan->channel <= 5350) 684 ret = 2; 685 else if ((chan->channel > 5350) && (chan->channel <= 5600)) 686 ret = 4; 687 else 688 ret = 6; 689 break; 690 691 case CHANNEL_G: 692 case CHANNEL_G_HT20: 693 case CHANNEL_B: 694 ret = 8; 695 break; 696 697 case CHANNEL_G_HT40PLUS: 698 case CHANNEL_G_HT40MINUS: 699 ret = 7; 700 break; 701 702 default: 703 ret = -EINVAL; 704 } 705 706 return ret; 707 } 708 709 static int ar9003_hw_process_ini(struct ath_hw *ah, 710 struct ath9k_channel *chan) 711 { 712 unsigned int regWrites = 0, i; 713 u32 modesIndex; 714 715 switch (chan->chanmode) { 716 case CHANNEL_A: 717 case CHANNEL_A_HT20: 718 modesIndex = 1; 719 break; 720 case CHANNEL_A_HT40PLUS: 721 case CHANNEL_A_HT40MINUS: 722 modesIndex = 2; 723 break; 724 case CHANNEL_G: 725 case CHANNEL_G_HT20: 726 case CHANNEL_B: 727 modesIndex = 4; 728 break; 729 case CHANNEL_G_HT40PLUS: 730 case CHANNEL_G_HT40MINUS: 731 modesIndex = 3; 732 break; 733 734 default: 735 return -EINVAL; 736 } 737 738 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 739 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 740 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 741 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 742 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 743 if (i == ATH_INI_POST && AR_SREV_9462_20(ah)) 744 ar9003_hw_prog_ini(ah, 745 &ah->ini_radio_post_sys2ant, 746 modesIndex); 747 } 748 749 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 750 if (AR_SREV_9550(ah)) 751 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, 752 regWrites); 753 754 if (AR_SREV_9550(ah)) { 755 int modes_txgain_index; 756 757 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); 758 if (modes_txgain_index < 0) 759 return -EINVAL; 760 761 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, 762 regWrites); 763 } else { 764 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 765 } 766 767 /* 768 * For 5GHz channels requiring Fast Clock, apply 769 * different modal values. 770 */ 771 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 772 REG_WRITE_ARRAY(&ah->iniModesFastClock, 773 modesIndex, regWrites); 774 775 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 776 777 if (chan->channel == 2484) 778 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); 779 780 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 781 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, 782 AR_GLB_SWREG_DISCONT_EN_BT_WLAN); 783 784 ah->modes_index = modesIndex; 785 ar9003_hw_override_ini(ah); 786 ar9003_hw_set_channel_regs(ah, chan); 787 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 788 ath9k_hw_apply_txpower(ah, chan, false); 789 790 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 791 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 792 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 793 ah->enabled_cals |= TX_IQ_CAL; 794 else 795 ah->enabled_cals &= ~TX_IQ_CAL; 796 797 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 798 ah->enabled_cals |= TX_CL_CAL; 799 else 800 ah->enabled_cals &= ~TX_CL_CAL; 801 } 802 803 return 0; 804 } 805 806 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 807 struct ath9k_channel *chan) 808 { 809 u32 rfMode = 0; 810 811 if (chan == NULL) 812 return; 813 814 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 815 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 816 817 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 818 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 819 if (IS_CHAN_QUARTER_RATE(chan)) 820 rfMode |= AR_PHY_MODE_QUARTER; 821 if (IS_CHAN_HALF_RATE(chan)) 822 rfMode |= AR_PHY_MODE_HALF; 823 824 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF)) 825 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 826 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3); 827 828 REG_WRITE(ah, AR_PHY_MODE, rfMode); 829 } 830 831 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 832 { 833 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 834 } 835 836 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 837 struct ath9k_channel *chan) 838 { 839 u32 coef_scaled, ds_coef_exp, ds_coef_man; 840 u32 clockMhzScaled = 0x64000000; 841 struct chan_centers centers; 842 843 /* 844 * half and quarter rate can divide the scaled clock by 2 or 4 845 * scale for selected channel bandwidth 846 */ 847 if (IS_CHAN_HALF_RATE(chan)) 848 clockMhzScaled = clockMhzScaled >> 1; 849 else if (IS_CHAN_QUARTER_RATE(chan)) 850 clockMhzScaled = clockMhzScaled >> 2; 851 852 /* 853 * ALGO -> coef = 1e8/fcarrier*fclock/40; 854 * scaled coef to provide precision for this floating calculation 855 */ 856 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 857 coef_scaled = clockMhzScaled / centers.synth_center; 858 859 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 860 &ds_coef_exp); 861 862 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 863 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 864 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 865 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 866 867 /* 868 * For Short GI, 869 * scaled coeff is 9/10 that of normal coeff 870 */ 871 coef_scaled = (9 * coef_scaled) / 10; 872 873 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 874 &ds_coef_exp); 875 876 /* for short gi */ 877 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 878 AR_PHY_SGI_DSC_MAN, ds_coef_man); 879 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 880 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 881 } 882 883 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 884 { 885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 886 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 887 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 888 } 889 890 /* 891 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 892 * Read the phy active delay register. Value is in 100ns increments. 893 */ 894 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 895 { 896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 897 898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 899 900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 901 } 902 903 static bool ar9003_hw_ani_control(struct ath_hw *ah, 904 enum ath9k_ani_cmd cmd, int param) 905 { 906 struct ath_common *common = ath9k_hw_common(ah); 907 struct ath9k_channel *chan = ah->curchan; 908 struct ar5416AniState *aniState = &chan->ani; 909 s32 value, value2; 910 911 switch (cmd & ah->ani_function) { 912 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 913 /* 914 * on == 1 means ofdm weak signal detection is ON 915 * on == 1 is the default, for less noise immunity 916 * 917 * on == 0 means ofdm weak signal detection is OFF 918 * on == 0 means more noise imm 919 */ 920 u32 on = param ? 1 : 0; 921 922 if (on) 923 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 924 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 925 else 926 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 927 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 928 929 if (on != aniState->ofdmWeakSigDetect) { 930 ath_dbg(common, ANI, 931 "** ch %d: ofdm weak signal: %s=>%s\n", 932 chan->channel, 933 aniState->ofdmWeakSigDetect ? 934 "on" : "off", 935 on ? "on" : "off"); 936 if (on) 937 ah->stats.ast_ani_ofdmon++; 938 else 939 ah->stats.ast_ani_ofdmoff++; 940 aniState->ofdmWeakSigDetect = on; 941 } 942 break; 943 } 944 case ATH9K_ANI_FIRSTEP_LEVEL:{ 945 u32 level = param; 946 947 if (level >= ARRAY_SIZE(firstep_table)) { 948 ath_dbg(common, ANI, 949 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 950 level, ARRAY_SIZE(firstep_table)); 951 return false; 952 } 953 954 /* 955 * make register setting relative to default 956 * from INI file & cap value 957 */ 958 value = firstep_table[level] - 959 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 960 aniState->iniDef.firstep; 961 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 962 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 963 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 964 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 965 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 966 AR_PHY_FIND_SIG_FIRSTEP, 967 value); 968 /* 969 * we need to set first step low register too 970 * make register setting relative to default 971 * from INI file & cap value 972 */ 973 value2 = firstep_table[level] - 974 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 975 aniState->iniDef.firstepLow; 976 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 977 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 978 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 979 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 980 981 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 982 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 983 984 if (level != aniState->firstepLevel) { 985 ath_dbg(common, ANI, 986 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 987 chan->channel, 988 aniState->firstepLevel, 989 level, 990 ATH9K_ANI_FIRSTEP_LVL, 991 value, 992 aniState->iniDef.firstep); 993 ath_dbg(common, ANI, 994 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 995 chan->channel, 996 aniState->firstepLevel, 997 level, 998 ATH9K_ANI_FIRSTEP_LVL, 999 value2, 1000 aniState->iniDef.firstepLow); 1001 if (level > aniState->firstepLevel) 1002 ah->stats.ast_ani_stepup++; 1003 else if (level < aniState->firstepLevel) 1004 ah->stats.ast_ani_stepdown++; 1005 aniState->firstepLevel = level; 1006 } 1007 break; 1008 } 1009 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1010 u32 level = param; 1011 1012 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1013 ath_dbg(common, ANI, 1014 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1015 level, ARRAY_SIZE(cycpwrThr1_table)); 1016 return false; 1017 } 1018 /* 1019 * make register setting relative to default 1020 * from INI file & cap value 1021 */ 1022 value = cycpwrThr1_table[level] - 1023 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1024 aniState->iniDef.cycpwrThr1; 1025 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1026 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1027 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1028 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1029 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1030 AR_PHY_TIMING5_CYCPWR_THR1, 1031 value); 1032 1033 /* 1034 * set AR_PHY_EXT_CCA for extension channel 1035 * make register setting relative to default 1036 * from INI file & cap value 1037 */ 1038 value2 = cycpwrThr1_table[level] - 1039 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1040 aniState->iniDef.cycpwrThr1Ext; 1041 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1042 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1043 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1044 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1045 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1046 AR_PHY_EXT_CYCPWR_THR1, value2); 1047 1048 if (level != aniState->spurImmunityLevel) { 1049 ath_dbg(common, ANI, 1050 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1051 chan->channel, 1052 aniState->spurImmunityLevel, 1053 level, 1054 ATH9K_ANI_SPUR_IMMUNE_LVL, 1055 value, 1056 aniState->iniDef.cycpwrThr1); 1057 ath_dbg(common, ANI, 1058 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1059 chan->channel, 1060 aniState->spurImmunityLevel, 1061 level, 1062 ATH9K_ANI_SPUR_IMMUNE_LVL, 1063 value2, 1064 aniState->iniDef.cycpwrThr1Ext); 1065 if (level > aniState->spurImmunityLevel) 1066 ah->stats.ast_ani_spurup++; 1067 else if (level < aniState->spurImmunityLevel) 1068 ah->stats.ast_ani_spurdown++; 1069 aniState->spurImmunityLevel = level; 1070 } 1071 break; 1072 } 1073 case ATH9K_ANI_MRC_CCK:{ 1074 /* 1075 * is_on == 1 means MRC CCK ON (default, less noise imm) 1076 * is_on == 0 means MRC CCK is OFF (more noise imm) 1077 */ 1078 bool is_on = param ? 1 : 0; 1079 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1080 AR_PHY_MRC_CCK_ENABLE, is_on); 1081 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1082 AR_PHY_MRC_CCK_MUX_REG, is_on); 1083 if (is_on != aniState->mrcCCK) { 1084 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 1085 chan->channel, 1086 aniState->mrcCCK ? "on" : "off", 1087 is_on ? "on" : "off"); 1088 if (is_on) 1089 ah->stats.ast_ani_ccklow++; 1090 else 1091 ah->stats.ast_ani_cckhigh++; 1092 aniState->mrcCCK = is_on; 1093 } 1094 break; 1095 } 1096 case ATH9K_ANI_PRESENT: 1097 break; 1098 default: 1099 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1100 return false; 1101 } 1102 1103 ath_dbg(common, ANI, 1104 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1105 aniState->spurImmunityLevel, 1106 aniState->ofdmWeakSigDetect ? "on" : "off", 1107 aniState->firstepLevel, 1108 aniState->mrcCCK ? "on" : "off", 1109 aniState->listenTime, 1110 aniState->ofdmPhyErrCount, 1111 aniState->cckPhyErrCount); 1112 return true; 1113 } 1114 1115 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1116 int16_t nfarray[NUM_NF_READINGS]) 1117 { 1118 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1119 #define AR_PHY_CH_MINCCA_PWR_S 20 1120 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1121 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1122 1123 int16_t nf; 1124 int i; 1125 1126 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1127 if (ah->rxchainmask & BIT(i)) { 1128 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1129 AR_PHY_CH_MINCCA_PWR); 1130 nfarray[i] = sign_extend32(nf, 8); 1131 1132 if (IS_CHAN_HT40(ah->curchan)) { 1133 u8 ext_idx = AR9300_MAX_CHAINS + i; 1134 1135 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1136 AR_PHY_CH_EXT_MINCCA_PWR); 1137 nfarray[ext_idx] = sign_extend32(nf, 8); 1138 } 1139 } 1140 } 1141 } 1142 1143 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1144 { 1145 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1146 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1147 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1148 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1149 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1150 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1151 1152 if (AR_SREV_9330(ah)) 1153 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1154 1155 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1156 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; 1157 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; 1158 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; 1159 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; 1160 } 1161 } 1162 1163 /* 1164 * Initialize the ANI register values with default (ini) values. 1165 * This routine is called during a (full) hardware reset after 1166 * all the registers are initialised from the INI. 1167 */ 1168 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1169 { 1170 struct ar5416AniState *aniState; 1171 struct ath_common *common = ath9k_hw_common(ah); 1172 struct ath9k_channel *chan = ah->curchan; 1173 struct ath9k_ani_default *iniDef; 1174 u32 val; 1175 1176 aniState = &ah->curchan->ani; 1177 iniDef = &aniState->iniDef; 1178 1179 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1180 ah->hw_version.macVersion, 1181 ah->hw_version.macRev, 1182 ah->opmode, 1183 chan->channel, 1184 chan->channelFlags); 1185 1186 val = REG_READ(ah, AR_PHY_SFCORR); 1187 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1188 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1189 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1190 1191 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1192 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1193 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1194 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1195 1196 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1197 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1198 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1199 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1200 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1201 iniDef->firstep = REG_READ_FIELD(ah, 1202 AR_PHY_FIND_SIG, 1203 AR_PHY_FIND_SIG_FIRSTEP); 1204 iniDef->firstepLow = REG_READ_FIELD(ah, 1205 AR_PHY_FIND_SIG_LOW, 1206 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1207 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1208 AR_PHY_TIMING5, 1209 AR_PHY_TIMING5_CYCPWR_THR1); 1210 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1211 AR_PHY_EXT_CCA, 1212 AR_PHY_EXT_CYCPWR_THR1); 1213 1214 /* these levels just got reset to defaults by the INI */ 1215 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1216 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1217 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG; 1218 aniState->mrcCCK = true; 1219 } 1220 1221 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1222 struct ath_hw_radar_conf *conf) 1223 { 1224 u32 radar_0 = 0, radar_1 = 0; 1225 1226 if (!conf) { 1227 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1228 return; 1229 } 1230 1231 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1232 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1233 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1234 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1235 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1236 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1237 1238 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1239 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1240 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1241 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1242 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1243 1244 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1245 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1246 if (conf->ext_channel) 1247 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1248 else 1249 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1250 } 1251 1252 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1253 { 1254 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1255 1256 conf->fir_power = -28; 1257 conf->radar_rssi = 0; 1258 conf->pulse_height = 10; 1259 conf->pulse_rssi = 24; 1260 conf->pulse_inband = 8; 1261 conf->pulse_maxlen = 255; 1262 conf->pulse_inband_step = 12; 1263 conf->radar_inband = 8; 1264 } 1265 1266 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1267 struct ath_hw_antcomb_conf *antconf) 1268 { 1269 u32 regval; 1270 1271 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1272 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> 1273 AR_PHY_ANT_DIV_MAIN_LNACONF_S; 1274 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> 1275 AR_PHY_ANT_DIV_ALT_LNACONF_S; 1276 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> 1277 AR_PHY_ANT_FAST_DIV_BIAS_S; 1278 1279 if (AR_SREV_9330_11(ah)) { 1280 antconf->lna1_lna2_delta = -9; 1281 antconf->div_group = 1; 1282 } else if (AR_SREV_9485(ah)) { 1283 antconf->lna1_lna2_delta = -9; 1284 antconf->div_group = 2; 1285 } else if (AR_SREV_9565(ah)) { 1286 antconf->lna1_lna2_delta = -3; 1287 antconf->div_group = 3; 1288 } else { 1289 antconf->lna1_lna2_delta = -3; 1290 antconf->div_group = 0; 1291 } 1292 } 1293 1294 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1295 struct ath_hw_antcomb_conf *antconf) 1296 { 1297 u32 regval; 1298 1299 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1300 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1301 AR_PHY_ANT_DIV_ALT_LNACONF | 1302 AR_PHY_ANT_FAST_DIV_BIAS | 1303 AR_PHY_ANT_DIV_MAIN_GAINTB | 1304 AR_PHY_ANT_DIV_ALT_GAINTB); 1305 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) 1306 & AR_PHY_ANT_DIV_MAIN_LNACONF); 1307 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) 1308 & AR_PHY_ANT_DIV_ALT_LNACONF); 1309 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) 1310 & AR_PHY_ANT_FAST_DIV_BIAS); 1311 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) 1312 & AR_PHY_ANT_DIV_MAIN_GAINTB); 1313 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) 1314 & AR_PHY_ANT_DIV_ALT_GAINTB); 1315 1316 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1317 } 1318 1319 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah, 1320 bool enable) 1321 { 1322 u8 ant_div_ctl1; 1323 u32 regval; 1324 1325 if (!AR_SREV_9565(ah)) 1326 return; 1327 1328 ah->shared_chain_lnadiv = enable; 1329 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1330 1331 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1332 regval &= (~AR_ANT_DIV_CTRL_ALL); 1333 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 1334 regval &= ~AR_PHY_ANT_DIV_LNADIV; 1335 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; 1336 1337 if (enable) 1338 regval |= AR_ANT_DIV_ENABLE; 1339 1340 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1341 1342 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 1343 regval &= ~AR_FAST_DIV_ENABLE; 1344 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; 1345 1346 if (enable) 1347 regval |= AR_FAST_DIV_ENABLE; 1348 1349 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 1350 1351 if (enable) { 1352 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1353 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1354 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan)) 1355 REG_SET_BIT(ah, AR_PHY_RESTART, 1356 AR_PHY_RESTART_ENABLE_DIV_M2FLAG); 1357 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, 1358 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1359 } else { 1360 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE); 1361 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1362 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1363 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE); 1364 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, 1365 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1366 1367 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1368 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1369 AR_PHY_ANT_DIV_ALT_LNACONF | 1370 AR_PHY_ANT_DIV_MAIN_GAINTB | 1371 AR_PHY_ANT_DIV_ALT_GAINTB); 1372 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1373 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S); 1374 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1375 } 1376 } 1377 1378 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1379 struct ath9k_channel *chan, 1380 u8 *ini_reloaded) 1381 { 1382 unsigned int regWrites = 0; 1383 u32 modesIndex; 1384 1385 switch (chan->chanmode) { 1386 case CHANNEL_A: 1387 case CHANNEL_A_HT20: 1388 modesIndex = 1; 1389 break; 1390 case CHANNEL_A_HT40PLUS: 1391 case CHANNEL_A_HT40MINUS: 1392 modesIndex = 2; 1393 break; 1394 case CHANNEL_G: 1395 case CHANNEL_G_HT20: 1396 case CHANNEL_B: 1397 modesIndex = 4; 1398 break; 1399 case CHANNEL_G_HT40PLUS: 1400 case CHANNEL_G_HT40MINUS: 1401 modesIndex = 3; 1402 break; 1403 1404 default: 1405 return -EINVAL; 1406 } 1407 1408 if (modesIndex == ah->modes_index) { 1409 *ini_reloaded = false; 1410 goto set_rfmode; 1411 } 1412 1413 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1414 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1415 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1416 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1417 1418 if (AR_SREV_9462_20(ah)) 1419 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, 1420 modesIndex); 1421 1422 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1423 1424 /* 1425 * For 5GHz channels requiring Fast Clock, apply 1426 * different modal values. 1427 */ 1428 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1429 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); 1430 1431 if (AR_SREV_9565(ah)) 1432 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); 1433 1434 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 1435 1436 ah->modes_index = modesIndex; 1437 *ini_reloaded = true; 1438 1439 set_rfmode: 1440 ar9003_hw_set_rfmode(ah, chan); 1441 return 0; 1442 } 1443 1444 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, 1445 struct ath_spec_scan *param) 1446 { 1447 u8 count; 1448 1449 if (!param->enabled) { 1450 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1451 AR_PHY_SPECTRAL_SCAN_ENABLE); 1452 return; 1453 } 1454 1455 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); 1456 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); 1457 1458 /* on AR93xx and newer, count = 0 will make the the chip send 1459 * spectral samples endlessly. Check if this really was intended, 1460 * and fix otherwise. 1461 */ 1462 count = param->count; 1463 if (param->endless) 1464 count = 0; 1465 else if (param->count == 0) 1466 count = 1; 1467 1468 if (param->short_repeat) 1469 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1470 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1471 else 1472 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1473 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1474 1475 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1476 AR_PHY_SPECTRAL_SCAN_COUNT, count); 1477 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1478 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); 1479 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1480 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); 1481 1482 return; 1483 } 1484 1485 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) 1486 { 1487 /* Activate spectral scan */ 1488 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1489 AR_PHY_SPECTRAL_SCAN_ACTIVE); 1490 } 1491 1492 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) 1493 { 1494 struct ath_common *common = ath9k_hw_common(ah); 1495 1496 /* Poll for spectral scan complete */ 1497 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, 1498 AR_PHY_SPECTRAL_SCAN_ACTIVE, 1499 0, AH_WAIT_TIMEOUT)) { 1500 ath_err(common, "spectral scan wait failed\n"); 1501 return; 1502 } 1503 } 1504 1505 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1506 { 1507 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1508 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1509 static const u32 ar9300_cca_regs[6] = { 1510 AR_PHY_CCA_0, 1511 AR_PHY_CCA_1, 1512 AR_PHY_CCA_2, 1513 AR_PHY_EXT_CCA, 1514 AR_PHY_EXT_CCA_1, 1515 AR_PHY_EXT_CCA_2, 1516 }; 1517 1518 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1519 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1520 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1521 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1522 priv_ops->init_bb = ar9003_hw_init_bb; 1523 priv_ops->process_ini = ar9003_hw_process_ini; 1524 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 1525 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 1526 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1527 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1528 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1529 priv_ops->ani_control = ar9003_hw_ani_control; 1530 priv_ops->do_getnf = ar9003_hw_do_getnf; 1531 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1532 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1533 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 1534 1535 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1536 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1537 ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv; 1538 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; 1539 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; 1540 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; 1541 1542 ar9003_hw_set_nf_limits(ah); 1543 ar9003_hw_set_radar_conf(ah); 1544 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1545 } 1546 1547 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 1548 { 1549 struct ath_common *common = ath9k_hw_common(ah); 1550 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 1551 u32 val, idle_count; 1552 1553 if (!idle_tmo_ms) { 1554 /* disable IRQ, disable chip-reset for BB panic */ 1555 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1556 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 1557 ~(AR_PHY_WATCHDOG_RST_ENABLE | 1558 AR_PHY_WATCHDOG_IRQ_ENABLE)); 1559 1560 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 1561 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1562 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 1563 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1564 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1565 1566 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); 1567 return; 1568 } 1569 1570 /* enable IRQ, disable chip-reset for BB watchdog */ 1571 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 1572 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1573 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 1574 ~AR_PHY_WATCHDOG_RST_ENABLE); 1575 1576 /* bound limit to 10 secs */ 1577 if (idle_tmo_ms > 10000) 1578 idle_tmo_ms = 10000; 1579 1580 /* 1581 * The time unit for watchdog event is 2^15 44/88MHz cycles. 1582 * 1583 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 1584 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 1585 * 1586 * Given we use fast clock now in 5 GHz, these time units should 1587 * be common for both 2 GHz and 5 GHz. 1588 */ 1589 idle_count = (100 * idle_tmo_ms) / 74; 1590 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 1591 idle_count = (100 * idle_tmo_ms) / 37; 1592 1593 /* 1594 * enable watchdog in non-IDLE mode, disable in IDLE mode, 1595 * set idle time-out. 1596 */ 1597 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1598 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1599 AR_PHY_WATCHDOG_IDLE_MASK | 1600 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1601 1602 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", 1603 idle_tmo_ms); 1604 } 1605 1606 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1607 { 1608 /* 1609 * we want to avoid printing in ISR context so we save the 1610 * watchdog status to be printed later in bottom half context. 1611 */ 1612 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 1613 1614 /* 1615 * the watchdog timer should reset on status read but to be sure 1616 * sure we write 0 to the watchdog status bit. 1617 */ 1618 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 1619 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 1620 } 1621 1622 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 1623 { 1624 struct ath_common *common = ath9k_hw_common(ah); 1625 u32 status; 1626 1627 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 1628 return; 1629 1630 status = ah->bb_watchdog_last_status; 1631 ath_dbg(common, RESET, 1632 "\n==== BB update: BB status=0x%08x ====\n", status); 1633 ath_dbg(common, RESET, 1634 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1635 MS(status, AR_PHY_WATCHDOG_INFO), 1636 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1637 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1638 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1639 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1640 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1641 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1642 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1643 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 1644 1645 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1646 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 1647 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 1648 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", 1649 REG_READ(ah, AR_PHY_GEN_CTRL)); 1650 1651 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 1652 if (common->cc_survey.cycles) 1653 ath_dbg(common, RESET, 1654 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 1655 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 1656 1657 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); 1658 } 1659 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 1660 1661 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 1662 { 1663 u32 val; 1664 1665 /* While receiving unsupported rate frame rx state machine 1666 * gets into a state 0xb and if phy_restart happens in that 1667 * state, BB would go hang. If RXSM is in 0xb state after 1668 * first bb panic, ensure to disable the phy_restart. 1669 */ 1670 if (!((MS(ah->bb_watchdog_last_status, 1671 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) || 1672 ah->bb_hang_rx_ofdm)) 1673 return; 1674 1675 ah->bb_hang_rx_ofdm = true; 1676 val = REG_READ(ah, AR_PHY_RESTART); 1677 val &= ~AR_PHY_RESTART_ENA; 1678 1679 REG_WRITE(ah, AR_PHY_RESTART, val); 1680 } 1681 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 1682