1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 21 static const int firstep_table[] = 22 /* level: 0 1 2 3 4 5 6 7 8 */ 23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 24 25 static const int cycpwrThr1_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 28 29 /* 30 * register values to turn OFDM weak signal detection OFF 31 */ 32 static const int m1ThreshLow_off = 127; 33 static const int m2ThreshLow_off = 127; 34 static const int m1Thresh_off = 127; 35 static const int m2Thresh_off = 127; 36 static const int m2CountThr_off = 31; 37 static const int m2CountThrLow_off = 63; 38 static const int m1ThreshLowExt_off = 127; 39 static const int m2ThreshLowExt_off = 127; 40 static const int m1ThreshExt_off = 127; 41 static const int m2ThreshExt_off = 127; 42 43 /** 44 * ar9003_hw_set_channel - set channel on single-chip device 45 * @ah: atheros hardware structure 46 * @chan: 47 * 48 * This is the function to change channel on single-chip devices, that is 49 * for AR9300 family of chipsets. 50 * 51 * This function takes the channel value in MHz and sets 52 * hardware channel value. Assumes writes have been enabled to analog bus. 53 * 54 * Actual Expression, 55 * 56 * For 2GHz channel, 57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 58 * (freq_ref = 40MHz) 59 * 60 * For 5GHz channel, 61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 62 * (freq_ref = 40MHz/(24>>amodeRefSel)) 63 * 64 * For 5GHz channels which are 5MHz spaced, 65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 66 * (freq_ref = 40MHz) 67 */ 68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 69 { 70 u16 bMode, fracMode = 0, aModeRefSel = 0; 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; 72 struct chan_centers centers; 73 int loadSynthChannel; 74 75 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 76 freq = centers.synth_center; 77 78 if (freq < 4800) { /* 2 GHz, fractional mode */ 79 if (AR_SREV_9330(ah)) { 80 if (ah->is_clk_25mhz) 81 div = 75; 82 else 83 div = 120; 84 85 channelSel = (freq * 4) / div; 86 chan_frac = (((freq * 4) % div) * 0x20000) / div; 87 channelSel = (channelSel << 17) | chan_frac; 88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 89 /* 90 * freq_ref = 40 / (refdiva >> amoderefsel); 91 * where refdiva=1 and amoderefsel=0 92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 94 */ 95 channelSel = (freq * 4) / 120; 96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 97 channelSel = (channelSel << 17) | chan_frac; 98 } else if (AR_SREV_9340(ah)) { 99 if (ah->is_clk_25mhz) { 100 channelSel = (freq * 2) / 75; 101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 102 channelSel = (channelSel << 17) | chan_frac; 103 } else { 104 channelSel = CHANSEL_2G(freq) >> 1; 105 } 106 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 107 if (ah->is_clk_25mhz) 108 div = 75; 109 else 110 div = 120; 111 112 channelSel = (freq * 4) / div; 113 chan_frac = (((freq * 4) % div) * 0x20000) / div; 114 channelSel = (channelSel << 17) | chan_frac; 115 } else { 116 channelSel = CHANSEL_2G(freq); 117 } 118 /* Set to 2G mode */ 119 bMode = 1; 120 } else { 121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) && 122 ah->is_clk_25mhz) { 123 channelSel = freq / 75; 124 chan_frac = ((freq % 75) * 0x20000) / 75; 125 channelSel = (channelSel << 17) | chan_frac; 126 } else { 127 channelSel = CHANSEL_5G(freq); 128 /* Doubler is ON, so, divide channelSel by 2. */ 129 channelSel >>= 1; 130 } 131 /* Set to 5G mode */ 132 bMode = 0; 133 } 134 135 /* Enable fractional mode for all channels */ 136 fracMode = 1; 137 aModeRefSel = 0; 138 loadSynthChannel = 0; 139 140 reg32 = (bMode << 29); 141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 142 143 /* Enable Long shift Select for Synthesizer */ 144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 146 147 /* Program Synth. setting */ 148 reg32 = (channelSel << 2) | (fracMode << 30) | 149 (aModeRefSel << 28) | (loadSynthChannel << 31); 150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 151 152 /* Toggle Load Synth channel bit */ 153 loadSynthChannel = 1; 154 reg32 = (channelSel << 2) | (fracMode << 30) | 155 (aModeRefSel << 28) | (loadSynthChannel << 31); 156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 157 158 ah->curchan = chan; 159 160 return 0; 161 } 162 163 /** 164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 165 * @ah: atheros hardware structure 166 * @chan: 167 * 168 * For single-chip solutions. Converts to baseband spur frequency given the 169 * input channel frequency and compute register settings below. 170 * 171 * Spur mitigation for MRC CCK 172 */ 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 174 struct ath9k_channel *chan) 175 { 176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 177 int cur_bb_spur, negative = 0, cck_spur_freq; 178 int i; 179 int range, max_spur_cnts, synth_freq; 180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); 181 182 /* 183 * Need to verify range +/- 10 MHz in control channel, otherwise spur 184 * is out-of-band and can be ignored. 185 */ 186 187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 188 AR_SREV_9550(ah)) { 189 if (spur_fbin_ptr[0] == 0) /* No spur */ 190 return; 191 max_spur_cnts = 5; 192 if (IS_CHAN_HT40(chan)) { 193 range = 19; 194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 195 AR_PHY_GC_DYN2040_PRI_CH) == 0) 196 synth_freq = chan->channel + 10; 197 else 198 synth_freq = chan->channel - 10; 199 } else { 200 range = 10; 201 synth_freq = chan->channel; 202 } 203 } else { 204 range = AR_SREV_9462(ah) ? 5 : 10; 205 max_spur_cnts = 4; 206 synth_freq = chan->channel; 207 } 208 209 for (i = 0; i < max_spur_cnts; i++) { 210 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 211 continue; 212 213 negative = 0; 214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 215 AR_SREV_9550(ah)) 216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], 217 IS_CHAN_2GHZ(chan)); 218 else 219 cur_bb_spur = spur_freq[i]; 220 221 cur_bb_spur -= synth_freq; 222 if (cur_bb_spur < 0) { 223 negative = 1; 224 cur_bb_spur = -cur_bb_spur; 225 } 226 if (cur_bb_spur < range) { 227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 228 229 if (negative == 1) 230 cck_spur_freq = -cck_spur_freq; 231 232 cck_spur_freq = cck_spur_freq & 0xfffff; 233 234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 240 0x2); 241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 243 0x1); 244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 246 cck_spur_freq); 247 248 return; 249 } 250 } 251 252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 258 } 259 260 /* Clean all spur register fields */ 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 262 { 263 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 265 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 267 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 271 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 273 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 275 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 281 282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 284 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 286 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 302 } 303 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 305 int freq_offset, 306 int spur_freq_sd, 307 int spur_delta_phase, 308 int spur_subchannel_sd, 309 int range, 310 int synth_freq) 311 { 312 int mask_index = 0; 313 314 /* OFDM Spur mitigation */ 315 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 317 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 319 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 323 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 325 326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) 327 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 329 330 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 336 337 if (!AR_SREV_9340(ah) && 338 REG_READ_FIELD(ah, AR_PHY_MODE, 339 AR_PHY_MODE_DYNAMIC) == 0x1) 340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 342 343 mask_index = (freq_offset << 4) / 5; 344 if (mask_index < 0) 345 mask_index = mask_index - 1; 346 347 mask_index = mask_index & 0x7f; 348 349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 353 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 369 } 370 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, 372 int freq_offset) 373 { 374 int mask_index = 0; 375 376 mask_index = (freq_offset << 4) / 5; 377 if (mask_index < 0) 378 mask_index = mask_index - 1; 379 380 mask_index = mask_index & 0x7f; 381 382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B, 384 mask_index); 385 386 /* A == B */ 387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 389 mask_index); 390 391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B, 393 mask_index); 394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe); 396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe); 398 399 /* A == B */ 400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, 401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 402 } 403 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 405 struct ath9k_channel *chan, 406 int freq_offset, 407 int range, 408 int synth_freq) 409 { 410 int spur_freq_sd = 0; 411 int spur_subchannel_sd = 0; 412 int spur_delta_phase = 0; 413 414 if (IS_CHAN_HT40(chan)) { 415 if (freq_offset < 0) { 416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 418 spur_subchannel_sd = 1; 419 else 420 spur_subchannel_sd = 0; 421 422 spur_freq_sd = ((freq_offset + 10) << 9) / 11; 423 424 } else { 425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 427 spur_subchannel_sd = 0; 428 else 429 spur_subchannel_sd = 1; 430 431 spur_freq_sd = ((freq_offset - 10) << 9) / 11; 432 433 } 434 435 spur_delta_phase = (freq_offset << 17) / 5; 436 437 } else { 438 spur_subchannel_sd = 0; 439 spur_freq_sd = (freq_offset << 9) /11; 440 spur_delta_phase = (freq_offset << 18) / 5; 441 } 442 443 spur_freq_sd = spur_freq_sd & 0x3ff; 444 spur_delta_phase = spur_delta_phase & 0xfffff; 445 446 ar9003_hw_spur_ofdm(ah, 447 freq_offset, 448 spur_freq_sd, 449 spur_delta_phase, 450 spur_subchannel_sd, 451 range, synth_freq); 452 } 453 454 /* Spur mitigation for OFDM */ 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 456 struct ath9k_channel *chan) 457 { 458 int synth_freq; 459 int range = 10; 460 int freq_offset = 0; 461 int mode; 462 u8* spurChansPtr; 463 unsigned int i; 464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 465 466 if (IS_CHAN_5GHZ(chan)) { 467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 468 mode = 0; 469 } 470 else { 471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 472 mode = 1; 473 } 474 475 if (spurChansPtr[0] == 0) 476 return; /* No spur in the mode */ 477 478 if (IS_CHAN_HT40(chan)) { 479 range = 19; 480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 482 synth_freq = chan->channel - 10; 483 else 484 synth_freq = chan->channel + 10; 485 } else { 486 range = 10; 487 synth_freq = chan->channel; 488 } 489 490 ar9003_hw_spur_ofdm_clear(ah); 491 492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode); 494 freq_offset -= synth_freq; 495 if (abs(freq_offset) < range) { 496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, 497 range, synth_freq); 498 499 if (AR_SREV_9565(ah) && (i < 4)) { 500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1], 501 mode); 502 freq_offset -= synth_freq; 503 if (abs(freq_offset) < range) 504 ar9003_hw_spur_ofdm_9565(ah, freq_offset); 505 } 506 507 break; 508 } 509 } 510 } 511 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 513 struct ath9k_channel *chan) 514 { 515 if (!AR_SREV_9565(ah)) 516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 517 ar9003_hw_spur_mitigate_ofdm(ah, chan); 518 } 519 520 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, 521 struct ath9k_channel *chan) 522 { 523 u32 pll; 524 525 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); 526 527 if (chan && IS_CHAN_HALF_RATE(chan)) 528 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); 529 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 530 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); 531 532 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); 533 534 return pll; 535 } 536 537 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 538 struct ath9k_channel *chan) 539 { 540 u32 pll; 541 542 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 543 544 if (chan && IS_CHAN_HALF_RATE(chan)) 545 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 546 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 547 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 548 549 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 550 551 return pll; 552 } 553 554 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 555 struct ath9k_channel *chan) 556 { 557 u32 phymode; 558 u32 enableDacFifo = 0; 559 560 enableDacFifo = 561 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 562 563 /* Enable 11n HT, 20 MHz */ 564 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 565 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 566 567 /* Configure baseband for dynamic 20/40 operation */ 568 if (IS_CHAN_HT40(chan)) { 569 phymode |= AR_PHY_GC_DYN2040_EN; 570 /* Configure control (primary) channel at +-10MHz */ 571 if (IS_CHAN_HT40PLUS(chan)) 572 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 573 574 } 575 576 /* make sure we preserve INI settings */ 577 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 578 /* turn off Green Field detection for STA for now */ 579 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 580 581 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 582 583 /* Configure MAC for 20/40 operation */ 584 ath9k_hw_set11nmac2040(ah, chan); 585 586 /* global transmit timeout (25 TUs default)*/ 587 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 588 /* carrier sense timeout */ 589 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 590 } 591 592 static void ar9003_hw_init_bb(struct ath_hw *ah, 593 struct ath9k_channel *chan) 594 { 595 u32 synthDelay; 596 597 /* 598 * Wait for the frequency synth to settle (synth goes on 599 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 600 * Value is in 100ns increments. 601 */ 602 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 603 604 /* Activate the PHY (includes baseband activate + synthesizer on) */ 605 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 606 ath9k_hw_synth_delay(ah, chan, synthDelay); 607 } 608 609 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 610 { 611 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) 612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 613 AR_PHY_SWAP_ALT_CHAIN); 614 615 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 616 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 617 618 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 619 tx = 3; 620 621 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 622 } 623 624 /* 625 * Override INI values with chip specific configuration. 626 */ 627 static void ar9003_hw_override_ini(struct ath_hw *ah) 628 { 629 u32 val; 630 631 /* 632 * Set the RX_ABORT and RX_DIS and clear it only after 633 * RXE is set for MAC. This prevents frames with 634 * corrupted descriptor status. 635 */ 636 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 637 638 /* 639 * For AR9280 and above, there is a new feature that allows 640 * Multicast search based on both MAC Address and Key ID. By default, 641 * this feature is enabled. But since the driver is not using this 642 * feature, we switch it off; otherwise multicast search based on 643 * MAC addr only will fail. 644 */ 645 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 646 val |= AR_AGG_WEP_ENABLE_FIX | 647 AR_AGG_WEP_ENABLE | 648 AR_PCU_MISC_MODE2_CFP_IGNORE; 649 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 650 651 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 652 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, 653 AR_GLB_SWREG_DISCONT_EN_BT_WLAN); 654 655 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 656 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 657 ah->enabled_cals |= TX_IQ_CAL; 658 else 659 ah->enabled_cals &= ~TX_IQ_CAL; 660 661 } 662 663 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 664 ah->enabled_cals |= TX_CL_CAL; 665 else 666 ah->enabled_cals &= ~TX_CL_CAL; 667 } 668 669 static void ar9003_hw_prog_ini(struct ath_hw *ah, 670 struct ar5416IniArray *iniArr, 671 int column) 672 { 673 unsigned int i, regWrites = 0; 674 675 /* New INI format: Array may be undefined (pre, core, post arrays) */ 676 if (!iniArr->ia_array) 677 return; 678 679 /* 680 * New INI format: Pre, core, and post arrays for a given subsystem 681 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 682 * the array is non-modal and force the column to 1. 683 */ 684 if (column >= iniArr->ia_columns) 685 column = 1; 686 687 for (i = 0; i < iniArr->ia_rows; i++) { 688 u32 reg = INI_RA(iniArr, i, 0); 689 u32 val = INI_RA(iniArr, i, column); 690 691 REG_WRITE(ah, reg, val); 692 693 DO_DELAY(regWrites); 694 } 695 } 696 697 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, 698 struct ath9k_channel *chan) 699 { 700 int ret; 701 702 if (IS_CHAN_2GHZ(chan)) { 703 if (IS_CHAN_HT40(chan)) 704 return 7; 705 else 706 return 8; 707 } 708 709 if (chan->channel <= 5350) 710 ret = 1; 711 else if ((chan->channel > 5350) && (chan->channel <= 5600)) 712 ret = 3; 713 else 714 ret = 5; 715 716 if (IS_CHAN_HT40(chan)) 717 ret++; 718 719 return ret; 720 } 721 722 static void ar9003_doubler_fix(struct ath_hw *ah) 723 { 724 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { 725 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 726 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 727 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 728 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 729 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 730 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 731 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 732 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 733 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); 734 735 udelay(200); 736 737 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, 738 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 739 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, 740 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 741 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, 742 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); 743 744 udelay(1); 745 746 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, 747 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 748 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, 749 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 750 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, 751 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); 752 753 udelay(200); 754 755 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, 756 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf); 757 758 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, 759 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 760 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 761 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, 762 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 763 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 764 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, 765 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | 766 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); 767 } 768 } 769 770 static int ar9003_hw_process_ini(struct ath_hw *ah, 771 struct ath9k_channel *chan) 772 { 773 unsigned int regWrites = 0, i; 774 u32 modesIndex; 775 776 if (IS_CHAN_5GHZ(chan)) 777 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 778 else 779 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 780 781 /* 782 * SOC, MAC, BB, RADIO initvals. 783 */ 784 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 785 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 786 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 787 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 788 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 789 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) 790 ar9003_hw_prog_ini(ah, 791 &ah->ini_radio_post_sys2ant, 792 modesIndex); 793 } 794 795 ar9003_doubler_fix(ah); 796 797 /* 798 * RXGAIN initvals. 799 */ 800 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 801 802 if (AR_SREV_9462_20_OR_LATER(ah)) { 803 /* 804 * CUS217 mix LNA mode. 805 */ 806 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { 807 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, 808 1, regWrites); 809 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 810 modesIndex, regWrites); 811 } 812 813 /* 814 * 5G-XLNA 815 */ 816 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || 817 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { 818 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 819 modesIndex, regWrites); 820 } 821 } 822 823 if (AR_SREV_9550(ah)) 824 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, 825 regWrites); 826 827 /* 828 * TXGAIN initvals. 829 */ 830 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { 831 int modes_txgain_index = 1; 832 833 if (AR_SREV_9550(ah)) 834 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); 835 836 if (modes_txgain_index < 0) 837 return -EINVAL; 838 839 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, 840 regWrites); 841 } else { 842 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 843 } 844 845 /* 846 * For 5GHz channels requiring Fast Clock, apply 847 * different modal values. 848 */ 849 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 850 REG_WRITE_ARRAY(&ah->iniModesFastClock, 851 modesIndex, regWrites); 852 853 /* 854 * Clock frequency initvals. 855 */ 856 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); 857 858 /* 859 * JAPAN regulatory. 860 */ 861 if (chan->channel == 2484) 862 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); 863 864 ah->modes_index = modesIndex; 865 ar9003_hw_override_ini(ah); 866 ar9003_hw_set_channel_regs(ah, chan); 867 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 868 ath9k_hw_apply_txpower(ah, chan, false); 869 870 return 0; 871 } 872 873 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 874 struct ath9k_channel *chan) 875 { 876 u32 rfMode = 0; 877 878 if (chan == NULL) 879 return; 880 881 if (IS_CHAN_2GHZ(chan)) 882 rfMode |= AR_PHY_MODE_DYNAMIC; 883 else 884 rfMode |= AR_PHY_MODE_OFDM; 885 886 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 887 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 888 889 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF)) 890 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 891 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3); 892 893 REG_WRITE(ah, AR_PHY_MODE, rfMode); 894 } 895 896 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 897 { 898 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 899 } 900 901 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 902 struct ath9k_channel *chan) 903 { 904 u32 coef_scaled, ds_coef_exp, ds_coef_man; 905 u32 clockMhzScaled = 0x64000000; 906 struct chan_centers centers; 907 908 /* 909 * half and quarter rate can divide the scaled clock by 2 or 4 910 * scale for selected channel bandwidth 911 */ 912 if (IS_CHAN_HALF_RATE(chan)) 913 clockMhzScaled = clockMhzScaled >> 1; 914 else if (IS_CHAN_QUARTER_RATE(chan)) 915 clockMhzScaled = clockMhzScaled >> 2; 916 917 /* 918 * ALGO -> coef = 1e8/fcarrier*fclock/40; 919 * scaled coef to provide precision for this floating calculation 920 */ 921 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 922 coef_scaled = clockMhzScaled / centers.synth_center; 923 924 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 925 &ds_coef_exp); 926 927 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 928 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 929 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 930 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 931 932 /* 933 * For Short GI, 934 * scaled coeff is 9/10 that of normal coeff 935 */ 936 coef_scaled = (9 * coef_scaled) / 10; 937 938 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 939 &ds_coef_exp); 940 941 /* for short gi */ 942 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 943 AR_PHY_SGI_DSC_MAN, ds_coef_man); 944 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 945 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 946 } 947 948 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 949 { 950 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 951 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 952 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 953 } 954 955 /* 956 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 957 * Read the phy active delay register. Value is in 100ns increments. 958 */ 959 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 960 { 961 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 962 963 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 964 965 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 966 } 967 968 static bool ar9003_hw_ani_control(struct ath_hw *ah, 969 enum ath9k_ani_cmd cmd, int param) 970 { 971 struct ath_common *common = ath9k_hw_common(ah); 972 struct ath9k_channel *chan = ah->curchan; 973 struct ar5416AniState *aniState = &ah->ani; 974 int m1ThreshLow, m2ThreshLow; 975 int m1Thresh, m2Thresh; 976 int m2CountThr, m2CountThrLow; 977 int m1ThreshLowExt, m2ThreshLowExt; 978 int m1ThreshExt, m2ThreshExt; 979 s32 value, value2; 980 981 switch (cmd & ah->ani_function) { 982 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 983 /* 984 * on == 1 means ofdm weak signal detection is ON 985 * on == 1 is the default, for less noise immunity 986 * 987 * on == 0 means ofdm weak signal detection is OFF 988 * on == 0 means more noise imm 989 */ 990 u32 on = param ? 1 : 0; 991 992 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 993 goto skip_ws_det; 994 995 m1ThreshLow = on ? 996 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 997 m2ThreshLow = on ? 998 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 999 m1Thresh = on ? 1000 aniState->iniDef.m1Thresh : m1Thresh_off; 1001 m2Thresh = on ? 1002 aniState->iniDef.m2Thresh : m2Thresh_off; 1003 m2CountThr = on ? 1004 aniState->iniDef.m2CountThr : m2CountThr_off; 1005 m2CountThrLow = on ? 1006 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 1007 m1ThreshLowExt = on ? 1008 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 1009 m2ThreshLowExt = on ? 1010 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1011 m1ThreshExt = on ? 1012 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1013 m2ThreshExt = on ? 1014 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1015 1016 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1017 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1018 m1ThreshLow); 1019 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1020 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1021 m2ThreshLow); 1022 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1023 AR_PHY_SFCORR_M1_THRESH, 1024 m1Thresh); 1025 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1026 AR_PHY_SFCORR_M2_THRESH, 1027 m2Thresh); 1028 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1029 AR_PHY_SFCORR_M2COUNT_THR, 1030 m2CountThr); 1031 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1032 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1033 m2CountThrLow); 1034 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1035 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 1036 m1ThreshLowExt); 1037 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1038 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 1039 m2ThreshLowExt); 1040 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1041 AR_PHY_SFCORR_EXT_M1_THRESH, 1042 m1ThreshExt); 1043 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1044 AR_PHY_SFCORR_EXT_M2_THRESH, 1045 m2ThreshExt); 1046 skip_ws_det: 1047 if (on) 1048 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1049 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1050 else 1051 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1052 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1053 1054 if (on != aniState->ofdmWeakSigDetect) { 1055 ath_dbg(common, ANI, 1056 "** ch %d: ofdm weak signal: %s=>%s\n", 1057 chan->channel, 1058 aniState->ofdmWeakSigDetect ? 1059 "on" : "off", 1060 on ? "on" : "off"); 1061 if (on) 1062 ah->stats.ast_ani_ofdmon++; 1063 else 1064 ah->stats.ast_ani_ofdmoff++; 1065 aniState->ofdmWeakSigDetect = on; 1066 } 1067 break; 1068 } 1069 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1070 u32 level = param; 1071 1072 if (level >= ARRAY_SIZE(firstep_table)) { 1073 ath_dbg(common, ANI, 1074 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1075 level, ARRAY_SIZE(firstep_table)); 1076 return false; 1077 } 1078 1079 /* 1080 * make register setting relative to default 1081 * from INI file & cap value 1082 */ 1083 value = firstep_table[level] - 1084 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1085 aniState->iniDef.firstep; 1086 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1087 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1088 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1089 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1090 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1091 AR_PHY_FIND_SIG_FIRSTEP, 1092 value); 1093 /* 1094 * we need to set first step low register too 1095 * make register setting relative to default 1096 * from INI file & cap value 1097 */ 1098 value2 = firstep_table[level] - 1099 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1100 aniState->iniDef.firstepLow; 1101 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1102 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1103 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1104 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1105 1106 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1107 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 1108 1109 if (level != aniState->firstepLevel) { 1110 ath_dbg(common, ANI, 1111 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1112 chan->channel, 1113 aniState->firstepLevel, 1114 level, 1115 ATH9K_ANI_FIRSTEP_LVL, 1116 value, 1117 aniState->iniDef.firstep); 1118 ath_dbg(common, ANI, 1119 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1120 chan->channel, 1121 aniState->firstepLevel, 1122 level, 1123 ATH9K_ANI_FIRSTEP_LVL, 1124 value2, 1125 aniState->iniDef.firstepLow); 1126 if (level > aniState->firstepLevel) 1127 ah->stats.ast_ani_stepup++; 1128 else if (level < aniState->firstepLevel) 1129 ah->stats.ast_ani_stepdown++; 1130 aniState->firstepLevel = level; 1131 } 1132 break; 1133 } 1134 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1135 u32 level = param; 1136 1137 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1138 ath_dbg(common, ANI, 1139 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1140 level, ARRAY_SIZE(cycpwrThr1_table)); 1141 return false; 1142 } 1143 /* 1144 * make register setting relative to default 1145 * from INI file & cap value 1146 */ 1147 value = cycpwrThr1_table[level] - 1148 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1149 aniState->iniDef.cycpwrThr1; 1150 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1151 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1152 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1153 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1154 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1155 AR_PHY_TIMING5_CYCPWR_THR1, 1156 value); 1157 1158 /* 1159 * set AR_PHY_EXT_CCA for extension channel 1160 * make register setting relative to default 1161 * from INI file & cap value 1162 */ 1163 value2 = cycpwrThr1_table[level] - 1164 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1165 aniState->iniDef.cycpwrThr1Ext; 1166 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1167 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1168 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1169 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1170 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1171 AR_PHY_EXT_CYCPWR_THR1, value2); 1172 1173 if (level != aniState->spurImmunityLevel) { 1174 ath_dbg(common, ANI, 1175 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1176 chan->channel, 1177 aniState->spurImmunityLevel, 1178 level, 1179 ATH9K_ANI_SPUR_IMMUNE_LVL, 1180 value, 1181 aniState->iniDef.cycpwrThr1); 1182 ath_dbg(common, ANI, 1183 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1184 chan->channel, 1185 aniState->spurImmunityLevel, 1186 level, 1187 ATH9K_ANI_SPUR_IMMUNE_LVL, 1188 value2, 1189 aniState->iniDef.cycpwrThr1Ext); 1190 if (level > aniState->spurImmunityLevel) 1191 ah->stats.ast_ani_spurup++; 1192 else if (level < aniState->spurImmunityLevel) 1193 ah->stats.ast_ani_spurdown++; 1194 aniState->spurImmunityLevel = level; 1195 } 1196 break; 1197 } 1198 case ATH9K_ANI_MRC_CCK:{ 1199 /* 1200 * is_on == 1 means MRC CCK ON (default, less noise imm) 1201 * is_on == 0 means MRC CCK is OFF (more noise imm) 1202 */ 1203 bool is_on = param ? 1 : 0; 1204 1205 if (ah->caps.rx_chainmask == 1) 1206 break; 1207 1208 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1209 AR_PHY_MRC_CCK_ENABLE, is_on); 1210 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1211 AR_PHY_MRC_CCK_MUX_REG, is_on); 1212 if (is_on != aniState->mrcCCK) { 1213 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 1214 chan->channel, 1215 aniState->mrcCCK ? "on" : "off", 1216 is_on ? "on" : "off"); 1217 if (is_on) 1218 ah->stats.ast_ani_ccklow++; 1219 else 1220 ah->stats.ast_ani_cckhigh++; 1221 aniState->mrcCCK = is_on; 1222 } 1223 break; 1224 } 1225 default: 1226 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1227 return false; 1228 } 1229 1230 ath_dbg(common, ANI, 1231 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1232 aniState->spurImmunityLevel, 1233 aniState->ofdmWeakSigDetect ? "on" : "off", 1234 aniState->firstepLevel, 1235 aniState->mrcCCK ? "on" : "off", 1236 aniState->listenTime, 1237 aniState->ofdmPhyErrCount, 1238 aniState->cckPhyErrCount); 1239 return true; 1240 } 1241 1242 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1243 int16_t nfarray[NUM_NF_READINGS]) 1244 { 1245 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1246 #define AR_PHY_CH_MINCCA_PWR_S 20 1247 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1248 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1249 1250 int16_t nf; 1251 int i; 1252 1253 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1254 if (ah->rxchainmask & BIT(i)) { 1255 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1256 AR_PHY_CH_MINCCA_PWR); 1257 nfarray[i] = sign_extend32(nf, 8); 1258 1259 if (IS_CHAN_HT40(ah->curchan)) { 1260 u8 ext_idx = AR9300_MAX_CHAINS + i; 1261 1262 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1263 AR_PHY_CH_EXT_MINCCA_PWR); 1264 nfarray[ext_idx] = sign_extend32(nf, 8); 1265 } 1266 } 1267 } 1268 } 1269 1270 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1271 { 1272 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1273 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1274 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1275 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1276 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1277 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1278 1279 if (AR_SREV_9330(ah)) 1280 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1281 1282 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 1283 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; 1284 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; 1285 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; 1286 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; 1287 } 1288 } 1289 1290 /* 1291 * Initialize the ANI register values with default (ini) values. 1292 * This routine is called during a (full) hardware reset after 1293 * all the registers are initialised from the INI. 1294 */ 1295 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1296 { 1297 struct ar5416AniState *aniState; 1298 struct ath_common *common = ath9k_hw_common(ah); 1299 struct ath9k_channel *chan = ah->curchan; 1300 struct ath9k_ani_default *iniDef; 1301 u32 val; 1302 1303 aniState = &ah->ani; 1304 iniDef = &aniState->iniDef; 1305 1306 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1307 ah->hw_version.macVersion, 1308 ah->hw_version.macRev, 1309 ah->opmode, 1310 chan->channel); 1311 1312 val = REG_READ(ah, AR_PHY_SFCORR); 1313 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1314 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1315 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1316 1317 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1318 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1319 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1320 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1321 1322 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1323 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1324 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1325 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1326 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1327 iniDef->firstep = REG_READ_FIELD(ah, 1328 AR_PHY_FIND_SIG, 1329 AR_PHY_FIND_SIG_FIRSTEP); 1330 iniDef->firstepLow = REG_READ_FIELD(ah, 1331 AR_PHY_FIND_SIG_LOW, 1332 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1333 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1334 AR_PHY_TIMING5, 1335 AR_PHY_TIMING5_CYCPWR_THR1); 1336 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1337 AR_PHY_EXT_CCA, 1338 AR_PHY_EXT_CYCPWR_THR1); 1339 1340 /* these levels just got reset to defaults by the INI */ 1341 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1342 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1343 aniState->ofdmWeakSigDetect = true; 1344 aniState->mrcCCK = true; 1345 } 1346 1347 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1348 struct ath_hw_radar_conf *conf) 1349 { 1350 unsigned int regWrites = 0; 1351 u32 radar_0 = 0, radar_1 = 0; 1352 1353 if (!conf) { 1354 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1355 return; 1356 } 1357 1358 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1359 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1360 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1361 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1362 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1363 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1364 1365 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1366 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1367 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1368 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1369 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1370 1371 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1372 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1373 if (conf->ext_channel) 1374 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1375 else 1376 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1377 1378 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { 1379 REG_WRITE_ARRAY(&ah->ini_dfs, 1380 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); 1381 } 1382 } 1383 1384 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1385 { 1386 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1387 1388 conf->fir_power = -28; 1389 conf->radar_rssi = 0; 1390 conf->pulse_height = 10; 1391 conf->pulse_rssi = 24; 1392 conf->pulse_inband = 8; 1393 conf->pulse_maxlen = 255; 1394 conf->pulse_inband_step = 12; 1395 conf->radar_inband = 8; 1396 } 1397 1398 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1399 struct ath_hw_antcomb_conf *antconf) 1400 { 1401 u32 regval; 1402 1403 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1404 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> 1405 AR_PHY_ANT_DIV_MAIN_LNACONF_S; 1406 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> 1407 AR_PHY_ANT_DIV_ALT_LNACONF_S; 1408 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> 1409 AR_PHY_ANT_FAST_DIV_BIAS_S; 1410 1411 if (AR_SREV_9330_11(ah)) { 1412 antconf->lna1_lna2_switch_delta = -1; 1413 antconf->lna1_lna2_delta = -9; 1414 antconf->div_group = 1; 1415 } else if (AR_SREV_9485(ah)) { 1416 antconf->lna1_lna2_switch_delta = -1; 1417 antconf->lna1_lna2_delta = -9; 1418 antconf->div_group = 2; 1419 } else if (AR_SREV_9565(ah)) { 1420 antconf->lna1_lna2_switch_delta = 3; 1421 antconf->lna1_lna2_delta = -9; 1422 antconf->div_group = 3; 1423 } else { 1424 antconf->lna1_lna2_switch_delta = -1; 1425 antconf->lna1_lna2_delta = -3; 1426 antconf->div_group = 0; 1427 } 1428 } 1429 1430 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1431 struct ath_hw_antcomb_conf *antconf) 1432 { 1433 u32 regval; 1434 1435 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1436 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1437 AR_PHY_ANT_DIV_ALT_LNACONF | 1438 AR_PHY_ANT_FAST_DIV_BIAS | 1439 AR_PHY_ANT_DIV_MAIN_GAINTB | 1440 AR_PHY_ANT_DIV_ALT_GAINTB); 1441 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) 1442 & AR_PHY_ANT_DIV_MAIN_LNACONF); 1443 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) 1444 & AR_PHY_ANT_DIV_ALT_LNACONF); 1445 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) 1446 & AR_PHY_ANT_FAST_DIV_BIAS); 1447 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) 1448 & AR_PHY_ANT_DIV_MAIN_GAINTB); 1449 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) 1450 & AR_PHY_ANT_DIV_ALT_GAINTB); 1451 1452 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1453 } 1454 1455 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1456 1457 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) 1458 { 1459 struct ath9k_hw_capabilities *pCap = &ah->caps; 1460 u8 ant_div_ctl1; 1461 u32 regval; 1462 1463 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 1464 return; 1465 1466 if (AR_SREV_9485(ah)) { 1467 regval = ar9003_hw_ant_ctrl_common_2_get(ah, 1468 IS_CHAN_2GHZ(ah->curchan)); 1469 if (enable) { 1470 regval &= ~AR_SWITCH_TABLE_COM2_ALL; 1471 regval |= ah->config.ant_ctrl_comm2g_switch_enable; 1472 } 1473 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, 1474 AR_SWITCH_TABLE_COM2_ALL, regval); 1475 } 1476 1477 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 1478 1479 /* 1480 * Set MAIN/ALT LNA conf. 1481 * Set MAIN/ALT gain_tb. 1482 */ 1483 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1484 regval &= (~AR_ANT_DIV_CTRL_ALL); 1485 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 1486 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1487 1488 if (AR_SREV_9485_11_OR_LATER(ah)) { 1489 /* 1490 * Enable LNA diversity. 1491 */ 1492 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1493 regval &= ~AR_PHY_ANT_DIV_LNADIV; 1494 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; 1495 if (enable) 1496 regval |= AR_ANT_DIV_ENABLE; 1497 1498 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1499 1500 /* 1501 * Enable fast antenna diversity. 1502 */ 1503 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 1504 regval &= ~AR_FAST_DIV_ENABLE; 1505 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; 1506 if (enable) 1507 regval |= AR_FAST_DIV_ENABLE; 1508 1509 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 1510 1511 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { 1512 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1513 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1514 AR_PHY_ANT_DIV_ALT_LNACONF | 1515 AR_PHY_ANT_DIV_ALT_GAINTB | 1516 AR_PHY_ANT_DIV_MAIN_GAINTB)); 1517 /* 1518 * Set MAIN to LNA1 and ALT to LNA2 at the 1519 * beginning. 1520 */ 1521 regval |= (ATH_ANT_DIV_COMB_LNA1 << 1522 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1523 regval |= (ATH_ANT_DIV_COMB_LNA2 << 1524 AR_PHY_ANT_DIV_ALT_LNACONF_S); 1525 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1526 } 1527 } else if (AR_SREV_9565(ah)) { 1528 if (enable) { 1529 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1530 AR_ANT_DIV_ENABLE); 1531 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1532 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1533 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 1534 AR_FAST_DIV_ENABLE); 1535 REG_SET_BIT(ah, AR_PHY_RESTART, 1536 AR_PHY_RESTART_ENABLE_DIV_M2FLAG); 1537 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, 1538 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1539 } else { 1540 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1541 AR_ANT_DIV_ENABLE); 1542 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, 1543 (1 << AR_PHY_ANT_SW_RX_PROT_S)); 1544 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, 1545 AR_FAST_DIV_ENABLE); 1546 REG_CLR_BIT(ah, AR_PHY_RESTART, 1547 AR_PHY_RESTART_ENABLE_DIV_M2FLAG); 1548 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, 1549 AR_BTCOEX_WL_LNADIV_FORCE_ON); 1550 1551 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1552 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | 1553 AR_PHY_ANT_DIV_ALT_LNACONF | 1554 AR_PHY_ANT_DIV_MAIN_GAINTB | 1555 AR_PHY_ANT_DIV_ALT_GAINTB); 1556 regval |= (ATH_ANT_DIV_COMB_LNA1 << 1557 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 1558 regval |= (ATH_ANT_DIV_COMB_LNA2 << 1559 AR_PHY_ANT_DIV_ALT_LNACONF_S); 1560 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1561 } 1562 } 1563 } 1564 1565 #endif 1566 1567 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1568 struct ath9k_channel *chan, 1569 u8 *ini_reloaded) 1570 { 1571 unsigned int regWrites = 0; 1572 u32 modesIndex, txgain_index; 1573 1574 if (IS_CHAN_5GHZ(chan)) 1575 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 1576 else 1577 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 1578 1579 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; 1580 1581 if (modesIndex == ah->modes_index) { 1582 *ini_reloaded = false; 1583 goto set_rfmode; 1584 } 1585 1586 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1587 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1588 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1589 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1590 1591 if (AR_SREV_9462_20_OR_LATER(ah)) 1592 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, 1593 modesIndex); 1594 1595 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); 1596 1597 if (AR_SREV_9462_20_OR_LATER(ah)) { 1598 /* 1599 * CUS217 mix LNA mode. 1600 */ 1601 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { 1602 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, 1603 1, regWrites); 1604 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 1605 modesIndex, regWrites); 1606 } 1607 } 1608 1609 /* 1610 * For 5GHz channels requiring Fast Clock, apply 1611 * different modal values. 1612 */ 1613 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1614 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); 1615 1616 if (AR_SREV_9565(ah)) 1617 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); 1618 1619 /* 1620 * JAPAN regulatory. 1621 */ 1622 if (chan->channel == 2484) 1623 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); 1624 1625 ah->modes_index = modesIndex; 1626 *ini_reloaded = true; 1627 1628 set_rfmode: 1629 ar9003_hw_set_rfmode(ah, chan); 1630 return 0; 1631 } 1632 1633 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, 1634 struct ath_spec_scan *param) 1635 { 1636 u8 count; 1637 1638 if (!param->enabled) { 1639 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1640 AR_PHY_SPECTRAL_SCAN_ENABLE); 1641 return; 1642 } 1643 1644 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); 1645 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); 1646 1647 /* on AR93xx and newer, count = 0 will make the the chip send 1648 * spectral samples endlessly. Check if this really was intended, 1649 * and fix otherwise. 1650 */ 1651 count = param->count; 1652 if (param->endless) 1653 count = 0; 1654 else if (param->count == 0) 1655 count = 1; 1656 1657 if (param->short_repeat) 1658 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1659 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1660 else 1661 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1662 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); 1663 1664 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1665 AR_PHY_SPECTRAL_SCAN_COUNT, count); 1666 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1667 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); 1668 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, 1669 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); 1670 1671 return; 1672 } 1673 1674 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) 1675 { 1676 /* Activate spectral scan */ 1677 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, 1678 AR_PHY_SPECTRAL_SCAN_ACTIVE); 1679 } 1680 1681 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) 1682 { 1683 struct ath_common *common = ath9k_hw_common(ah); 1684 1685 /* Poll for spectral scan complete */ 1686 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, 1687 AR_PHY_SPECTRAL_SCAN_ACTIVE, 1688 0, AH_WAIT_TIMEOUT)) { 1689 ath_err(common, "spectral scan wait failed\n"); 1690 return; 1691 } 1692 } 1693 1694 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) 1695 { 1696 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); 1697 REG_SET_BIT(ah, 0x9864, 0x7f000); 1698 REG_SET_BIT(ah, 0x9924, 0x7f00fe); 1699 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 1700 REG_WRITE(ah, AR_CR, AR_CR_RXD); 1701 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 1702 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 1703 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 1704 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 1705 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 1706 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); 1707 } 1708 1709 static void ar9003_hw_tx99_stop(struct ath_hw *ah) 1710 { 1711 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); 1712 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); 1713 } 1714 1715 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) 1716 { 1717 static s16 p_pwr_array[ar9300RateSize] = { 0 }; 1718 unsigned int i; 1719 1720 if (txpower <= MAX_RATE_POWER) { 1721 for (i = 0; i < ar9300RateSize; i++) 1722 p_pwr_array[i] = txpower; 1723 } else { 1724 for (i = 0; i < ar9300RateSize; i++) 1725 p_pwr_array[i] = MAX_RATE_POWER; 1726 } 1727 1728 REG_WRITE(ah, 0xa458, 0); 1729 1730 REG_WRITE(ah, 0xa3c0, 1731 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) | 1732 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) | 1733 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) | 1734 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)); 1735 REG_WRITE(ah, 0xa3c4, 1736 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) | 1737 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) | 1738 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) | 1739 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)); 1740 REG_WRITE(ah, 0xa3c8, 1741 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) | 1742 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) | 1743 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)); 1744 REG_WRITE(ah, 0xa3cc, 1745 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) | 1746 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) | 1747 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) | 1748 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)); 1749 REG_WRITE(ah, 0xa3d0, 1750 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) | 1751 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) | 1752 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)| 1753 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)); 1754 REG_WRITE(ah, 0xa3d4, 1755 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) | 1756 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) | 1757 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) | 1758 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0)); 1759 REG_WRITE(ah, 0xa3e4, 1760 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) | 1761 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) | 1762 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) | 1763 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0)); 1764 REG_WRITE(ah, 0xa3e8, 1765 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) | 1766 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) | 1767 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) | 1768 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0)); 1769 REG_WRITE(ah, 0xa3d8, 1770 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) | 1771 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) | 1772 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | 1773 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)); 1774 REG_WRITE(ah, 0xa3dc, 1775 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) | 1776 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) | 1777 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) | 1778 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0)); 1779 REG_WRITE(ah, 0xa3ec, 1780 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) | 1781 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) | 1782 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) | 1783 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0)); 1784 } 1785 1786 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1787 { 1788 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1789 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1790 static const u32 ar9300_cca_regs[6] = { 1791 AR_PHY_CCA_0, 1792 AR_PHY_CCA_1, 1793 AR_PHY_CCA_2, 1794 AR_PHY_EXT_CCA, 1795 AR_PHY_EXT_CCA_1, 1796 AR_PHY_EXT_CCA_2, 1797 }; 1798 1799 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1800 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1801 1802 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) 1803 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; 1804 else 1805 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1806 1807 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1808 priv_ops->init_bb = ar9003_hw_init_bb; 1809 priv_ops->process_ini = ar9003_hw_process_ini; 1810 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 1811 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 1812 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1813 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1814 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1815 priv_ops->ani_control = ar9003_hw_ani_control; 1816 priv_ops->do_getnf = ar9003_hw_do_getnf; 1817 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1818 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1819 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 1820 1821 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1822 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1823 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; 1824 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; 1825 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; 1826 1827 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1828 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; 1829 #endif 1830 ops->tx99_start = ar9003_hw_tx99_start; 1831 ops->tx99_stop = ar9003_hw_tx99_stop; 1832 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; 1833 1834 ar9003_hw_set_nf_limits(ah); 1835 ar9003_hw_set_radar_conf(ah); 1836 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1837 } 1838 1839 /* 1840 * Baseband Watchdog signatures: 1841 * 1842 * 0x04000539: BB hang when operating in HT40 DFS Channel. 1843 * Full chip reset is not required, but a recovery 1844 * mechanism is needed. 1845 * 1846 * 0x1300000a: Related to CAC deafness. 1847 * Chip reset is not required. 1848 * 1849 * 0x0400000a: Related to CAC deafness. 1850 * Full chip reset is required. 1851 * 1852 * 0x04000b09: RX state machine gets into an illegal state 1853 * when a packet with unsupported rate is received. 1854 * Full chip reset is required and PHY_RESTART has 1855 * to be disabled. 1856 * 1857 * 0x04000409: Packet stuck on receive. 1858 * Full chip reset is required for all chips except AR9340. 1859 */ 1860 1861 /* 1862 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required. 1863 */ 1864 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) 1865 { 1866 u32 val; 1867 1868 switch(ah->bb_watchdog_last_status) { 1869 case 0x04000539: 1870 val = REG_READ(ah, AR_PHY_RADAR_0); 1871 val &= (~AR_PHY_RADAR_0_FIRPWR); 1872 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); 1873 REG_WRITE(ah, AR_PHY_RADAR_0, val); 1874 udelay(1); 1875 val = REG_READ(ah, AR_PHY_RADAR_0); 1876 val &= ~AR_PHY_RADAR_0_FIRPWR; 1877 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); 1878 REG_WRITE(ah, AR_PHY_RADAR_0, val); 1879 1880 return false; 1881 case 0x1300000a: 1882 return false; 1883 case 0x0400000a: 1884 case 0x04000b09: 1885 return true; 1886 case 0x04000409: 1887 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) 1888 return false; 1889 else 1890 return true; 1891 default: 1892 /* 1893 * For any other unknown signatures, do a 1894 * full chip reset. 1895 */ 1896 return true; 1897 } 1898 } 1899 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check); 1900 1901 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 1902 { 1903 struct ath_common *common = ath9k_hw_common(ah); 1904 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 1905 u32 val, idle_count; 1906 1907 if (!idle_tmo_ms) { 1908 /* disable IRQ, disable chip-reset for BB panic */ 1909 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1910 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 1911 ~(AR_PHY_WATCHDOG_RST_ENABLE | 1912 AR_PHY_WATCHDOG_IRQ_ENABLE)); 1913 1914 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 1915 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1916 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 1917 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1918 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1919 1920 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); 1921 return; 1922 } 1923 1924 /* enable IRQ, disable chip-reset for BB watchdog */ 1925 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 1926 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1927 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 1928 ~AR_PHY_WATCHDOG_RST_ENABLE); 1929 1930 /* bound limit to 10 secs */ 1931 if (idle_tmo_ms > 10000) 1932 idle_tmo_ms = 10000; 1933 1934 /* 1935 * The time unit for watchdog event is 2^15 44/88MHz cycles. 1936 * 1937 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 1938 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 1939 * 1940 * Given we use fast clock now in 5 GHz, these time units should 1941 * be common for both 2 GHz and 5 GHz. 1942 */ 1943 idle_count = (100 * idle_tmo_ms) / 74; 1944 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 1945 idle_count = (100 * idle_tmo_ms) / 37; 1946 1947 /* 1948 * enable watchdog in non-IDLE mode, disable in IDLE mode, 1949 * set idle time-out. 1950 */ 1951 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1952 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1953 AR_PHY_WATCHDOG_IDLE_MASK | 1954 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1955 1956 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", 1957 idle_tmo_ms); 1958 } 1959 1960 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1961 { 1962 /* 1963 * we want to avoid printing in ISR context so we save the 1964 * watchdog status to be printed later in bottom half context. 1965 */ 1966 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 1967 1968 /* 1969 * the watchdog timer should reset on status read but to be sure 1970 * sure we write 0 to the watchdog status bit. 1971 */ 1972 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 1973 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 1974 } 1975 1976 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 1977 { 1978 struct ath_common *common = ath9k_hw_common(ah); 1979 u32 status; 1980 1981 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 1982 return; 1983 1984 status = ah->bb_watchdog_last_status; 1985 ath_dbg(common, RESET, 1986 "\n==== BB update: BB status=0x%08x ====\n", status); 1987 ath_dbg(common, RESET, 1988 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1989 MS(status, AR_PHY_WATCHDOG_INFO), 1990 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1991 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1992 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1993 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1994 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1995 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1996 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1997 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 1998 1999 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 2000 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 2001 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 2002 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", 2003 REG_READ(ah, AR_PHY_GEN_CTRL)); 2004 2005 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 2006 if (common->cc_survey.cycles) 2007 ath_dbg(common, RESET, 2008 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 2009 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 2010 2011 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); 2012 } 2013 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 2014 2015 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 2016 { 2017 u8 result; 2018 u32 val; 2019 2020 /* While receiving unsupported rate frame rx state machine 2021 * gets into a state 0xb and if phy_restart happens in that 2022 * state, BB would go hang. If RXSM is in 0xb state after 2023 * first bb panic, ensure to disable the phy_restart. 2024 */ 2025 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); 2026 2027 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { 2028 ah->bb_hang_rx_ofdm = true; 2029 val = REG_READ(ah, AR_PHY_RESTART); 2030 val &= ~AR_PHY_RESTART_ENA; 2031 REG_WRITE(ah, AR_PHY_RESTART, val); 2032 } 2033 } 2034 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 2035