1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_phy.h" 19 20 static const int firstep_table[] = 21 /* level: 0 1 2 3 4 5 6 7 8 */ 22 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 23 24 static const int cycpwrThr1_table[] = 25 /* level: 0 1 2 3 4 5 6 7 8 */ 26 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 27 28 /* 29 * register values to turn OFDM weak signal detection OFF 30 */ 31 static const int m1ThreshLow_off = 127; 32 static const int m2ThreshLow_off = 127; 33 static const int m1Thresh_off = 127; 34 static const int m2Thresh_off = 127; 35 static const int m2CountThr_off = 31; 36 static const int m2CountThrLow_off = 63; 37 static const int m1ThreshLowExt_off = 127; 38 static const int m2ThreshLowExt_off = 127; 39 static const int m1ThreshExt_off = 127; 40 static const int m2ThreshExt_off = 127; 41 42 /** 43 * ar9003_hw_set_channel - set channel on single-chip device 44 * @ah: atheros hardware structure 45 * @chan: 46 * 47 * This is the function to change channel on single-chip devices, that is 48 * all devices after ar9280. 49 * 50 * This function takes the channel value in MHz and sets 51 * hardware channel value. Assumes writes have been enabled to analog bus. 52 * 53 * Actual Expression, 54 * 55 * For 2GHz channel, 56 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 57 * (freq_ref = 40MHz) 58 * 59 * For 5GHz channel, 60 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 61 * (freq_ref = 40MHz/(24>>amodeRefSel)) 62 * 63 * For 5GHz channels which are 5MHz spaced, 64 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 65 * (freq_ref = 40MHz) 66 */ 67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 68 { 69 u16 bMode, fracMode = 0, aModeRefSel = 0; 70 u32 freq, channelSel = 0, reg32 = 0; 71 struct chan_centers centers; 72 int loadSynthChannel; 73 74 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 75 freq = centers.synth_center; 76 77 if (freq < 4800) { /* 2 GHz, fractional mode */ 78 if (AR_SREV_9330(ah)) { 79 u32 chan_frac; 80 u32 div; 81 82 if (ah->is_clk_25mhz) 83 div = 75; 84 else 85 div = 120; 86 87 channelSel = (freq * 4) / div; 88 chan_frac = (((freq * 4) % div) * 0x20000) / div; 89 channelSel = (channelSel << 17) | chan_frac; 90 } else if (AR_SREV_9485(ah)) { 91 u32 chan_frac; 92 93 /* 94 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0 95 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 96 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 97 */ 98 channelSel = (freq * 4) / 120; 99 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 100 channelSel = (channelSel << 17) | chan_frac; 101 } else if (AR_SREV_9340(ah)) { 102 if (ah->is_clk_25mhz) { 103 u32 chan_frac; 104 105 channelSel = (freq * 2) / 75; 106 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 107 channelSel = (channelSel << 17) | chan_frac; 108 } else 109 channelSel = CHANSEL_2G(freq) >> 1; 110 } else 111 channelSel = CHANSEL_2G(freq); 112 /* Set to 2G mode */ 113 bMode = 1; 114 } else { 115 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) { 116 u32 chan_frac; 117 118 channelSel = (freq * 2) / 75; 119 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 120 channelSel = (channelSel << 17) | chan_frac; 121 } else { 122 channelSel = CHANSEL_5G(freq); 123 /* Doubler is ON, so, divide channelSel by 2. */ 124 channelSel >>= 1; 125 } 126 /* Set to 5G mode */ 127 bMode = 0; 128 } 129 130 /* Enable fractional mode for all channels */ 131 fracMode = 1; 132 aModeRefSel = 0; 133 loadSynthChannel = 0; 134 135 reg32 = (bMode << 29); 136 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 137 138 /* Enable Long shift Select for Synthesizer */ 139 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 140 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 141 142 /* Program Synth. setting */ 143 reg32 = (channelSel << 2) | (fracMode << 30) | 144 (aModeRefSel << 28) | (loadSynthChannel << 31); 145 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 146 147 /* Toggle Load Synth channel bit */ 148 loadSynthChannel = 1; 149 reg32 = (channelSel << 2) | (fracMode << 30) | 150 (aModeRefSel << 28) | (loadSynthChannel << 31); 151 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 152 153 ah->curchan = chan; 154 ah->curchan_rad_index = -1; 155 156 return 0; 157 } 158 159 /** 160 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 161 * @ah: atheros hardware structure 162 * @chan: 163 * 164 * For single-chip solutions. Converts to baseband spur frequency given the 165 * input channel frequency and compute register settings below. 166 * 167 * Spur mitigation for MRC CCK 168 */ 169 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 170 struct ath9k_channel *chan) 171 { 172 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 173 int cur_bb_spur, negative = 0, cck_spur_freq; 174 int i; 175 int range, max_spur_cnts, synth_freq; 176 u8 *spur_fbin_ptr = NULL; 177 178 /* 179 * Need to verify range +/- 10 MHz in control channel, otherwise spur 180 * is out-of-band and can be ignored. 181 */ 182 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) { 184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, 185 IS_CHAN_2GHZ(chan)); 186 if (spur_fbin_ptr[0] == 0) /* No spur */ 187 return; 188 max_spur_cnts = 5; 189 if (IS_CHAN_HT40(chan)) { 190 range = 19; 191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 192 AR_PHY_GC_DYN2040_PRI_CH) == 0) 193 synth_freq = chan->channel + 10; 194 else 195 synth_freq = chan->channel - 10; 196 } else { 197 range = 10; 198 synth_freq = chan->channel; 199 } 200 } else { 201 range = 10; 202 max_spur_cnts = 4; 203 synth_freq = chan->channel; 204 } 205 206 for (i = 0; i < max_spur_cnts; i++) { 207 negative = 0; 208 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 209 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i], 210 IS_CHAN_2GHZ(chan)) - synth_freq; 211 else 212 cur_bb_spur = spur_freq[i] - synth_freq; 213 214 if (cur_bb_spur < 0) { 215 negative = 1; 216 cur_bb_spur = -cur_bb_spur; 217 } 218 if (cur_bb_spur < range) { 219 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 220 221 if (negative == 1) 222 cck_spur_freq = -cck_spur_freq; 223 224 cck_spur_freq = cck_spur_freq & 0xfffff; 225 226 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 227 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 228 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 229 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 230 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 231 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 232 0x2); 233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 234 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 235 0x1); 236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 237 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 238 cck_spur_freq); 239 240 return; 241 } 242 } 243 244 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 245 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 246 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 247 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 248 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 249 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 250 } 251 252 /* Clean all spur register fields */ 253 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 254 { 255 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 256 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 257 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 258 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 259 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 260 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 261 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 262 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 263 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 264 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 265 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 266 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 267 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 268 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 269 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 270 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 271 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 272 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 273 274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 275 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 276 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 277 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 278 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 279 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 280 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 281 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 282 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 283 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 284 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 285 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 286 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 287 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 288 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 289 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 292 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 293 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 294 } 295 296 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 297 int freq_offset, 298 int spur_freq_sd, 299 int spur_delta_phase, 300 int spur_subchannel_sd) 301 { 302 int mask_index = 0; 303 304 /* OFDM Spur mitigation */ 305 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 306 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 307 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 308 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 309 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 310 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 311 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 312 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 313 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 314 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 315 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 316 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 317 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 318 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 319 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 320 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 321 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 322 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 323 324 if (REG_READ_FIELD(ah, AR_PHY_MODE, 325 AR_PHY_MODE_DYNAMIC) == 0x1) 326 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 327 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 328 329 mask_index = (freq_offset << 4) / 5; 330 if (mask_index < 0) 331 mask_index = mask_index - 1; 332 333 mask_index = mask_index & 0x7f; 334 335 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 336 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 337 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 338 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 339 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 340 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 341 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 342 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 343 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 344 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 345 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 346 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 347 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 348 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 349 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 350 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 351 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 352 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 353 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 354 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 355 } 356 357 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 358 struct ath9k_channel *chan, 359 int freq_offset) 360 { 361 int spur_freq_sd = 0; 362 int spur_subchannel_sd = 0; 363 int spur_delta_phase = 0; 364 365 if (IS_CHAN_HT40(chan)) { 366 if (freq_offset < 0) { 367 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 368 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 369 spur_subchannel_sd = 1; 370 else 371 spur_subchannel_sd = 0; 372 373 spur_freq_sd = (freq_offset << 9) / 11; 374 375 } else { 376 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 377 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 378 spur_subchannel_sd = 0; 379 else 380 spur_subchannel_sd = 1; 381 382 spur_freq_sd = (freq_offset << 9) / 11; 383 384 } 385 386 spur_delta_phase = (freq_offset << 17) / 5; 387 388 } else { 389 spur_subchannel_sd = 0; 390 spur_freq_sd = (freq_offset << 9) /11; 391 spur_delta_phase = (freq_offset << 18) / 5; 392 } 393 394 spur_freq_sd = spur_freq_sd & 0x3ff; 395 spur_delta_phase = spur_delta_phase & 0xfffff; 396 397 ar9003_hw_spur_ofdm(ah, 398 freq_offset, 399 spur_freq_sd, 400 spur_delta_phase, 401 spur_subchannel_sd); 402 } 403 404 /* Spur mitigation for OFDM */ 405 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 406 struct ath9k_channel *chan) 407 { 408 int synth_freq; 409 int range = 10; 410 int freq_offset = 0; 411 int mode; 412 u8* spurChansPtr; 413 unsigned int i; 414 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 415 416 if (IS_CHAN_5GHZ(chan)) { 417 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 418 mode = 0; 419 } 420 else { 421 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 422 mode = 1; 423 } 424 425 if (spurChansPtr[0] == 0) 426 return; /* No spur in the mode */ 427 428 if (IS_CHAN_HT40(chan)) { 429 range = 19; 430 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 431 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 432 synth_freq = chan->channel - 10; 433 else 434 synth_freq = chan->channel + 10; 435 } else { 436 range = 10; 437 synth_freq = chan->channel; 438 } 439 440 ar9003_hw_spur_ofdm_clear(ah); 441 442 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 443 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq; 444 if (abs(freq_offset) < range) { 445 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); 446 break; 447 } 448 } 449 } 450 451 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 452 struct ath9k_channel *chan) 453 { 454 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 455 ar9003_hw_spur_mitigate_ofdm(ah, chan); 456 } 457 458 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 459 struct ath9k_channel *chan) 460 { 461 u32 pll; 462 463 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 464 465 if (chan && IS_CHAN_HALF_RATE(chan)) 466 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 467 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 468 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 469 470 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 471 472 return pll; 473 } 474 475 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 476 struct ath9k_channel *chan) 477 { 478 u32 phymode; 479 u32 enableDacFifo = 0; 480 481 enableDacFifo = 482 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 483 484 /* Enable 11n HT, 20 MHz */ 485 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 486 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 487 488 /* Configure baseband for dynamic 20/40 operation */ 489 if (IS_CHAN_HT40(chan)) { 490 phymode |= AR_PHY_GC_DYN2040_EN; 491 /* Configure control (primary) channel at +-10MHz */ 492 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 493 (chan->chanmode == CHANNEL_G_HT40PLUS)) 494 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 495 496 } 497 498 /* make sure we preserve INI settings */ 499 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 500 /* turn off Green Field detection for STA for now */ 501 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 502 503 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 504 505 /* Configure MAC for 20/40 operation */ 506 ath9k_hw_set11nmac2040(ah); 507 508 /* global transmit timeout (25 TUs default)*/ 509 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 510 /* carrier sense timeout */ 511 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 512 } 513 514 static void ar9003_hw_init_bb(struct ath_hw *ah, 515 struct ath9k_channel *chan) 516 { 517 u32 synthDelay; 518 519 /* 520 * Wait for the frequency synth to settle (synth goes on 521 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 522 * Value is in 100ns increments. 523 */ 524 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 525 if (IS_CHAN_B(chan)) 526 synthDelay = (4 * synthDelay) / 22; 527 else 528 synthDelay /= 10; 529 530 /* Activate the PHY (includes baseband activate + synthesizer on) */ 531 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 532 533 /* 534 * There is an issue if the AP starts the calibration before 535 * the base band timeout completes. This could result in the 536 * rx_clear false triggering. As a workaround we add delay an 537 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 538 * does not happen. 539 */ 540 udelay(synthDelay + BASE_ACTIVATE_DELAY); 541 } 542 543 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 544 { 545 switch (rx) { 546 case 0x5: 547 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 548 AR_PHY_SWAP_ALT_CHAIN); 549 case 0x3: 550 case 0x1: 551 case 0x2: 552 case 0x7: 553 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 554 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 555 break; 556 default: 557 break; 558 } 559 560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 562 else if (AR_SREV_9462(ah)) 563 /* xxx only when MCI support is enabled */ 564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 565 else 566 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 567 568 if (tx == 0x5) { 569 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 570 AR_PHY_SWAP_ALT_CHAIN); 571 } 572 } 573 574 /* 575 * Override INI values with chip specific configuration. 576 */ 577 static void ar9003_hw_override_ini(struct ath_hw *ah) 578 { 579 u32 val; 580 581 /* 582 * Set the RX_ABORT and RX_DIS and clear it only after 583 * RXE is set for MAC. This prevents frames with 584 * corrupted descriptor status. 585 */ 586 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 587 588 /* 589 * For AR9280 and above, there is a new feature that allows 590 * Multicast search based on both MAC Address and Key ID. By default, 591 * this feature is enabled. But since the driver is not using this 592 * feature, we switch it off; otherwise multicast search based on 593 * MAC addr only will fail. 594 */ 595 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 596 REG_WRITE(ah, AR_PCU_MISC_MODE2, 597 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); 598 599 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 600 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 601 } 602 603 static void ar9003_hw_prog_ini(struct ath_hw *ah, 604 struct ar5416IniArray *iniArr, 605 int column) 606 { 607 unsigned int i, regWrites = 0; 608 609 /* New INI format: Array may be undefined (pre, core, post arrays) */ 610 if (!iniArr->ia_array) 611 return; 612 613 /* 614 * New INI format: Pre, core, and post arrays for a given subsystem 615 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 616 * the array is non-modal and force the column to 1. 617 */ 618 if (column >= iniArr->ia_columns) 619 column = 1; 620 621 for (i = 0; i < iniArr->ia_rows; i++) { 622 u32 reg = INI_RA(iniArr, i, 0); 623 u32 val = INI_RA(iniArr, i, column); 624 625 REG_WRITE(ah, reg, val); 626 627 DO_DELAY(regWrites); 628 } 629 } 630 631 static int ar9003_hw_process_ini(struct ath_hw *ah, 632 struct ath9k_channel *chan) 633 { 634 unsigned int regWrites = 0, i; 635 u32 modesIndex; 636 637 switch (chan->chanmode) { 638 case CHANNEL_A: 639 case CHANNEL_A_HT20: 640 modesIndex = 1; 641 break; 642 case CHANNEL_A_HT40PLUS: 643 case CHANNEL_A_HT40MINUS: 644 modesIndex = 2; 645 break; 646 case CHANNEL_G: 647 case CHANNEL_G_HT20: 648 case CHANNEL_B: 649 modesIndex = 4; 650 break; 651 case CHANNEL_G_HT40PLUS: 652 case CHANNEL_G_HT40MINUS: 653 modesIndex = 3; 654 break; 655 656 default: 657 return -EINVAL; 658 } 659 660 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 661 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 662 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 663 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 664 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 665 if (i == ATH_INI_POST && AR_SREV_9462_20(ah)) 666 ar9003_hw_prog_ini(ah, 667 &ah->ini_radio_post_sys2ant, 668 modesIndex); 669 } 670 671 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 672 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 673 674 /* 675 * For 5GHz channels requiring Fast Clock, apply 676 * different modal values. 677 */ 678 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 679 REG_WRITE_ARRAY(&ah->iniModesAdditional, 680 modesIndex, regWrites); 681 682 if (AR_SREV_9330(ah)) 683 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 684 685 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 686 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 687 688 if (AR_SREV_9462(ah)) 689 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); 690 691 ah->modes_index = modesIndex; 692 ar9003_hw_override_ini(ah); 693 ar9003_hw_set_channel_regs(ah, chan); 694 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 695 ath9k_hw_apply_txpower(ah, chan); 696 697 if (AR_SREV_9462(ah)) { 698 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 699 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 700 ah->enabled_cals |= TX_IQ_CAL; 701 else 702 ah->enabled_cals &= ~TX_IQ_CAL; 703 704 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 705 ah->enabled_cals |= TX_CL_CAL; 706 else 707 ah->enabled_cals &= ~TX_CL_CAL; 708 } 709 710 return 0; 711 } 712 713 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 714 struct ath9k_channel *chan) 715 { 716 u32 rfMode = 0; 717 718 if (chan == NULL) 719 return; 720 721 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 722 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 723 724 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 725 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 726 727 REG_WRITE(ah, AR_PHY_MODE, rfMode); 728 } 729 730 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 731 { 732 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 733 } 734 735 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 736 struct ath9k_channel *chan) 737 { 738 u32 coef_scaled, ds_coef_exp, ds_coef_man; 739 u32 clockMhzScaled = 0x64000000; 740 struct chan_centers centers; 741 742 /* 743 * half and quarter rate can divide the scaled clock by 2 or 4 744 * scale for selected channel bandwidth 745 */ 746 if (IS_CHAN_HALF_RATE(chan)) 747 clockMhzScaled = clockMhzScaled >> 1; 748 else if (IS_CHAN_QUARTER_RATE(chan)) 749 clockMhzScaled = clockMhzScaled >> 2; 750 751 /* 752 * ALGO -> coef = 1e8/fcarrier*fclock/40; 753 * scaled coef to provide precision for this floating calculation 754 */ 755 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 756 coef_scaled = clockMhzScaled / centers.synth_center; 757 758 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 759 &ds_coef_exp); 760 761 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 762 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 763 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 764 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 765 766 /* 767 * For Short GI, 768 * scaled coeff is 9/10 that of normal coeff 769 */ 770 coef_scaled = (9 * coef_scaled) / 10; 771 772 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 773 &ds_coef_exp); 774 775 /* for short gi */ 776 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 777 AR_PHY_SGI_DSC_MAN, ds_coef_man); 778 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 779 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 780 } 781 782 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 783 { 784 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 785 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 786 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 787 } 788 789 /* 790 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 791 * Read the phy active delay register. Value is in 100ns increments. 792 */ 793 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 794 { 795 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 796 if (IS_CHAN_B(ah->curchan)) 797 synthDelay = (4 * synthDelay) / 22; 798 else 799 synthDelay /= 10; 800 801 udelay(synthDelay + BASE_ACTIVATE_DELAY); 802 803 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 804 } 805 806 static bool ar9003_hw_ani_control(struct ath_hw *ah, 807 enum ath9k_ani_cmd cmd, int param) 808 { 809 struct ath_common *common = ath9k_hw_common(ah); 810 struct ath9k_channel *chan = ah->curchan; 811 struct ar5416AniState *aniState = &chan->ani; 812 s32 value, value2; 813 814 switch (cmd & ah->ani_function) { 815 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 816 /* 817 * on == 1 means ofdm weak signal detection is ON 818 * on == 1 is the default, for less noise immunity 819 * 820 * on == 0 means ofdm weak signal detection is OFF 821 * on == 0 means more noise imm 822 */ 823 u32 on = param ? 1 : 0; 824 /* 825 * make register setting for default 826 * (weak sig detect ON) come from INI file 827 */ 828 int m1ThreshLow = on ? 829 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 830 int m2ThreshLow = on ? 831 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 832 int m1Thresh = on ? 833 aniState->iniDef.m1Thresh : m1Thresh_off; 834 int m2Thresh = on ? 835 aniState->iniDef.m2Thresh : m2Thresh_off; 836 int m2CountThr = on ? 837 aniState->iniDef.m2CountThr : m2CountThr_off; 838 int m2CountThrLow = on ? 839 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 840 int m1ThreshLowExt = on ? 841 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 842 int m2ThreshLowExt = on ? 843 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 844 int m1ThreshExt = on ? 845 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 846 int m2ThreshExt = on ? 847 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 848 849 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 850 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 851 m1ThreshLow); 852 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 853 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 854 m2ThreshLow); 855 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 856 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 857 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 858 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 859 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 860 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 861 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 862 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 863 m2CountThrLow); 864 865 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 866 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 867 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 868 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 869 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 870 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 871 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 872 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 873 874 if (on) 875 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 876 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 877 else 878 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 879 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 880 881 if (!on != aniState->ofdmWeakSigDetectOff) { 882 ath_dbg(common, ATH_DBG_ANI, 883 "** ch %d: ofdm weak signal: %s=>%s\n", 884 chan->channel, 885 !aniState->ofdmWeakSigDetectOff ? 886 "on" : "off", 887 on ? "on" : "off"); 888 if (on) 889 ah->stats.ast_ani_ofdmon++; 890 else 891 ah->stats.ast_ani_ofdmoff++; 892 aniState->ofdmWeakSigDetectOff = !on; 893 } 894 break; 895 } 896 case ATH9K_ANI_FIRSTEP_LEVEL:{ 897 u32 level = param; 898 899 if (level >= ARRAY_SIZE(firstep_table)) { 900 ath_dbg(common, ATH_DBG_ANI, 901 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 902 level, ARRAY_SIZE(firstep_table)); 903 return false; 904 } 905 906 /* 907 * make register setting relative to default 908 * from INI file & cap value 909 */ 910 value = firstep_table[level] - 911 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 912 aniState->iniDef.firstep; 913 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 914 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 915 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 916 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 917 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 918 AR_PHY_FIND_SIG_FIRSTEP, 919 value); 920 /* 921 * we need to set first step low register too 922 * make register setting relative to default 923 * from INI file & cap value 924 */ 925 value2 = firstep_table[level] - 926 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 927 aniState->iniDef.firstepLow; 928 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 929 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 930 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 931 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 932 933 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 934 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 935 936 if (level != aniState->firstepLevel) { 937 ath_dbg(common, ATH_DBG_ANI, 938 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 939 chan->channel, 940 aniState->firstepLevel, 941 level, 942 ATH9K_ANI_FIRSTEP_LVL_NEW, 943 value, 944 aniState->iniDef.firstep); 945 ath_dbg(common, ATH_DBG_ANI, 946 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 947 chan->channel, 948 aniState->firstepLevel, 949 level, 950 ATH9K_ANI_FIRSTEP_LVL_NEW, 951 value2, 952 aniState->iniDef.firstepLow); 953 if (level > aniState->firstepLevel) 954 ah->stats.ast_ani_stepup++; 955 else if (level < aniState->firstepLevel) 956 ah->stats.ast_ani_stepdown++; 957 aniState->firstepLevel = level; 958 } 959 break; 960 } 961 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 962 u32 level = param; 963 964 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 965 ath_dbg(common, ATH_DBG_ANI, 966 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 967 level, ARRAY_SIZE(cycpwrThr1_table)); 968 return false; 969 } 970 /* 971 * make register setting relative to default 972 * from INI file & cap value 973 */ 974 value = cycpwrThr1_table[level] - 975 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 976 aniState->iniDef.cycpwrThr1; 977 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 978 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 979 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 980 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 981 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 982 AR_PHY_TIMING5_CYCPWR_THR1, 983 value); 984 985 /* 986 * set AR_PHY_EXT_CCA for extension channel 987 * make register setting relative to default 988 * from INI file & cap value 989 */ 990 value2 = cycpwrThr1_table[level] - 991 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 992 aniState->iniDef.cycpwrThr1Ext; 993 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 994 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 995 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 996 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 997 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 998 AR_PHY_EXT_CYCPWR_THR1, value2); 999 1000 if (level != aniState->spurImmunityLevel) { 1001 ath_dbg(common, ATH_DBG_ANI, 1002 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1003 chan->channel, 1004 aniState->spurImmunityLevel, 1005 level, 1006 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1007 value, 1008 aniState->iniDef.cycpwrThr1); 1009 ath_dbg(common, ATH_DBG_ANI, 1010 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1011 chan->channel, 1012 aniState->spurImmunityLevel, 1013 level, 1014 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1015 value2, 1016 aniState->iniDef.cycpwrThr1Ext); 1017 if (level > aniState->spurImmunityLevel) 1018 ah->stats.ast_ani_spurup++; 1019 else if (level < aniState->spurImmunityLevel) 1020 ah->stats.ast_ani_spurdown++; 1021 aniState->spurImmunityLevel = level; 1022 } 1023 break; 1024 } 1025 case ATH9K_ANI_MRC_CCK:{ 1026 /* 1027 * is_on == 1 means MRC CCK ON (default, less noise imm) 1028 * is_on == 0 means MRC CCK is OFF (more noise imm) 1029 */ 1030 bool is_on = param ? 1 : 0; 1031 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1032 AR_PHY_MRC_CCK_ENABLE, is_on); 1033 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1034 AR_PHY_MRC_CCK_MUX_REG, is_on); 1035 if (!is_on != aniState->mrcCCKOff) { 1036 ath_dbg(common, ATH_DBG_ANI, 1037 "** ch %d: MRC CCK: %s=>%s\n", 1038 chan->channel, 1039 !aniState->mrcCCKOff ? "on" : "off", 1040 is_on ? "on" : "off"); 1041 if (is_on) 1042 ah->stats.ast_ani_ccklow++; 1043 else 1044 ah->stats.ast_ani_cckhigh++; 1045 aniState->mrcCCKOff = !is_on; 1046 } 1047 break; 1048 } 1049 case ATH9K_ANI_PRESENT: 1050 break; 1051 default: 1052 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); 1053 return false; 1054 } 1055 1056 ath_dbg(common, ATH_DBG_ANI, 1057 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1058 aniState->spurImmunityLevel, 1059 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1060 aniState->firstepLevel, 1061 !aniState->mrcCCKOff ? "on" : "off", 1062 aniState->listenTime, 1063 aniState->ofdmPhyErrCount, 1064 aniState->cckPhyErrCount); 1065 return true; 1066 } 1067 1068 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1069 int16_t nfarray[NUM_NF_READINGS]) 1070 { 1071 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1072 #define AR_PHY_CH_MINCCA_PWR_S 20 1073 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1074 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1075 1076 int16_t nf; 1077 int i; 1078 1079 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1080 if (ah->rxchainmask & BIT(i)) { 1081 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1082 AR_PHY_CH_MINCCA_PWR); 1083 nfarray[i] = sign_extend32(nf, 8); 1084 1085 if (IS_CHAN_HT40(ah->curchan)) { 1086 u8 ext_idx = AR9300_MAX_CHAINS + i; 1087 1088 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1089 AR_PHY_CH_EXT_MINCCA_PWR); 1090 nfarray[ext_idx] = sign_extend32(nf, 8); 1091 } 1092 } 1093 } 1094 } 1095 1096 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1097 { 1098 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1099 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1100 if (AR_SREV_9330(ah)) 1101 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1102 else 1103 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1104 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1105 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1106 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1107 } 1108 1109 /* 1110 * Initialize the ANI register values with default (ini) values. 1111 * This routine is called during a (full) hardware reset after 1112 * all the registers are initialised from the INI. 1113 */ 1114 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1115 { 1116 struct ar5416AniState *aniState; 1117 struct ath_common *common = ath9k_hw_common(ah); 1118 struct ath9k_channel *chan = ah->curchan; 1119 struct ath9k_ani_default *iniDef; 1120 u32 val; 1121 1122 aniState = &ah->curchan->ani; 1123 iniDef = &aniState->iniDef; 1124 1125 ath_dbg(common, ATH_DBG_ANI, 1126 "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1127 ah->hw_version.macVersion, 1128 ah->hw_version.macRev, 1129 ah->opmode, 1130 chan->channel, 1131 chan->channelFlags); 1132 1133 val = REG_READ(ah, AR_PHY_SFCORR); 1134 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1135 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1136 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1137 1138 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1139 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1140 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1141 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1142 1143 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1144 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1145 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1146 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1147 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1148 iniDef->firstep = REG_READ_FIELD(ah, 1149 AR_PHY_FIND_SIG, 1150 AR_PHY_FIND_SIG_FIRSTEP); 1151 iniDef->firstepLow = REG_READ_FIELD(ah, 1152 AR_PHY_FIND_SIG_LOW, 1153 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1154 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1155 AR_PHY_TIMING5, 1156 AR_PHY_TIMING5_CYCPWR_THR1); 1157 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1158 AR_PHY_EXT_CCA, 1159 AR_PHY_EXT_CYCPWR_THR1); 1160 1161 /* these levels just got reset to defaults by the INI */ 1162 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1163 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1164 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1165 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1166 } 1167 1168 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1169 struct ath_hw_radar_conf *conf) 1170 { 1171 u32 radar_0 = 0, radar_1 = 0; 1172 1173 if (!conf) { 1174 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1175 return; 1176 } 1177 1178 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1179 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1180 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1181 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1182 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1183 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1184 1185 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1186 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1187 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1188 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1189 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1190 1191 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1192 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1193 if (conf->ext_channel) 1194 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1195 else 1196 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1197 } 1198 1199 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1200 { 1201 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1202 1203 conf->fir_power = -28; 1204 conf->radar_rssi = 0; 1205 conf->pulse_height = 10; 1206 conf->pulse_rssi = 24; 1207 conf->pulse_inband = 8; 1208 conf->pulse_maxlen = 255; 1209 conf->pulse_inband_step = 12; 1210 conf->radar_inband = 8; 1211 } 1212 1213 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1214 struct ath_hw_antcomb_conf *antconf) 1215 { 1216 u32 regval; 1217 1218 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1219 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >> 1220 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S; 1221 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >> 1222 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S; 1223 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >> 1224 AR_PHY_9485_ANT_FAST_DIV_BIAS_S; 1225 1226 if (AR_SREV_9330_11(ah)) { 1227 antconf->lna1_lna2_delta = -9; 1228 antconf->div_group = 1; 1229 } else if (AR_SREV_9485(ah)) { 1230 antconf->lna1_lna2_delta = -9; 1231 antconf->div_group = 2; 1232 } else { 1233 antconf->lna1_lna2_delta = -3; 1234 antconf->div_group = 0; 1235 } 1236 } 1237 1238 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1239 struct ath_hw_antcomb_conf *antconf) 1240 { 1241 u32 regval; 1242 1243 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1244 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 1245 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 1246 AR_PHY_9485_ANT_FAST_DIV_BIAS | 1247 AR_PHY_9485_ANT_DIV_MAIN_GAINTB | 1248 AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1249 regval |= ((antconf->main_lna_conf << 1250 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S) 1251 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF); 1252 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S) 1253 & AR_PHY_9485_ANT_DIV_ALT_LNACONF); 1254 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S) 1255 & AR_PHY_9485_ANT_FAST_DIV_BIAS); 1256 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S) 1257 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB); 1258 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S) 1259 & AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1260 1261 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1262 } 1263 1264 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1265 struct ath9k_channel *chan, 1266 u8 *ini_reloaded) 1267 { 1268 unsigned int regWrites = 0; 1269 u32 modesIndex; 1270 1271 switch (chan->chanmode) { 1272 case CHANNEL_A: 1273 case CHANNEL_A_HT20: 1274 modesIndex = 1; 1275 break; 1276 case CHANNEL_A_HT40PLUS: 1277 case CHANNEL_A_HT40MINUS: 1278 modesIndex = 2; 1279 break; 1280 case CHANNEL_G: 1281 case CHANNEL_G_HT20: 1282 case CHANNEL_B: 1283 modesIndex = 4; 1284 break; 1285 case CHANNEL_G_HT40PLUS: 1286 case CHANNEL_G_HT40MINUS: 1287 modesIndex = 3; 1288 break; 1289 1290 default: 1291 return -EINVAL; 1292 } 1293 1294 if (modesIndex == ah->modes_index) { 1295 *ini_reloaded = false; 1296 goto set_rfmode; 1297 } 1298 1299 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1300 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1301 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1302 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1303 if (AR_SREV_9462_20(ah)) 1304 ar9003_hw_prog_ini(ah, 1305 &ah->ini_radio_post_sys2ant, 1306 modesIndex); 1307 1308 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1309 1310 /* 1311 * For 5GHz channels requiring Fast Clock, apply 1312 * different modal values. 1313 */ 1314 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1315 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites); 1316 1317 if (AR_SREV_9330(ah)) 1318 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 1319 1320 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 1321 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 1322 1323 ah->modes_index = modesIndex; 1324 *ini_reloaded = true; 1325 1326 set_rfmode: 1327 ar9003_hw_set_rfmode(ah, chan); 1328 return 0; 1329 } 1330 1331 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1332 { 1333 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1334 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1335 static const u32 ar9300_cca_regs[6] = { 1336 AR_PHY_CCA_0, 1337 AR_PHY_CCA_1, 1338 AR_PHY_CCA_2, 1339 AR_PHY_EXT_CCA, 1340 AR_PHY_EXT_CCA_1, 1341 AR_PHY_EXT_CCA_2, 1342 }; 1343 1344 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1345 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1346 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1347 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1348 priv_ops->init_bb = ar9003_hw_init_bb; 1349 priv_ops->process_ini = ar9003_hw_process_ini; 1350 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 1351 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 1352 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1353 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1354 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1355 priv_ops->ani_control = ar9003_hw_ani_control; 1356 priv_ops->do_getnf = ar9003_hw_do_getnf; 1357 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1358 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1359 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 1360 1361 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1362 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1363 1364 ar9003_hw_set_nf_limits(ah); 1365 ar9003_hw_set_radar_conf(ah); 1366 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1367 } 1368 1369 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 1370 { 1371 struct ath_common *common = ath9k_hw_common(ah); 1372 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 1373 u32 val, idle_count; 1374 1375 if (!idle_tmo_ms) { 1376 /* disable IRQ, disable chip-reset for BB panic */ 1377 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1378 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 1379 ~(AR_PHY_WATCHDOG_RST_ENABLE | 1380 AR_PHY_WATCHDOG_IRQ_ENABLE)); 1381 1382 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 1383 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1384 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 1385 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1386 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1387 1388 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); 1389 return; 1390 } 1391 1392 /* enable IRQ, disable chip-reset for BB watchdog */ 1393 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 1394 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1395 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 1396 ~AR_PHY_WATCHDOG_RST_ENABLE); 1397 1398 /* bound limit to 10 secs */ 1399 if (idle_tmo_ms > 10000) 1400 idle_tmo_ms = 10000; 1401 1402 /* 1403 * The time unit for watchdog event is 2^15 44/88MHz cycles. 1404 * 1405 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 1406 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 1407 * 1408 * Given we use fast clock now in 5 GHz, these time units should 1409 * be common for both 2 GHz and 5 GHz. 1410 */ 1411 idle_count = (100 * idle_tmo_ms) / 74; 1412 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 1413 idle_count = (100 * idle_tmo_ms) / 37; 1414 1415 /* 1416 * enable watchdog in non-IDLE mode, disable in IDLE mode, 1417 * set idle time-out. 1418 */ 1419 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1420 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1421 AR_PHY_WATCHDOG_IDLE_MASK | 1422 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1423 1424 ath_dbg(common, ATH_DBG_RESET, 1425 "Enabled BB Watchdog timeout (%u ms)\n", 1426 idle_tmo_ms); 1427 } 1428 1429 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1430 { 1431 /* 1432 * we want to avoid printing in ISR context so we save the 1433 * watchdog status to be printed later in bottom half context. 1434 */ 1435 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 1436 1437 /* 1438 * the watchdog timer should reset on status read but to be sure 1439 * sure we write 0 to the watchdog status bit. 1440 */ 1441 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 1442 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 1443 } 1444 1445 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 1446 { 1447 struct ath_common *common = ath9k_hw_common(ah); 1448 u32 status; 1449 1450 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 1451 return; 1452 1453 status = ah->bb_watchdog_last_status; 1454 ath_dbg(common, ATH_DBG_RESET, 1455 "\n==== BB update: BB status=0x%08x ====\n", status); 1456 ath_dbg(common, ATH_DBG_RESET, 1457 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1458 MS(status, AR_PHY_WATCHDOG_INFO), 1459 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1460 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1461 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1462 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1463 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1464 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1465 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1466 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 1467 1468 ath_dbg(common, ATH_DBG_RESET, 1469 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1470 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 1471 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 1472 ath_dbg(common, ATH_DBG_RESET, 1473 "** BB mode: BB_gen_controls=0x%08x **\n", 1474 REG_READ(ah, AR_PHY_GEN_CTRL)); 1475 1476 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 1477 if (common->cc_survey.cycles) 1478 ath_dbg(common, ATH_DBG_RESET, 1479 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 1480 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 1481 1482 ath_dbg(common, ATH_DBG_RESET, 1483 "==== BB update: done ====\n\n"); 1484 } 1485 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 1486 1487 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 1488 { 1489 u32 val; 1490 1491 /* While receiving unsupported rate frame rx state machine 1492 * gets into a state 0xb and if phy_restart happens in that 1493 * state, BB would go hang. If RXSM is in 0xb state after 1494 * first bb panic, ensure to disable the phy_restart. 1495 */ 1496 if (!((MS(ah->bb_watchdog_last_status, 1497 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) || 1498 ah->bb_hang_rx_ofdm)) 1499 return; 1500 1501 ah->bb_hang_rx_ofdm = true; 1502 val = REG_READ(ah, AR_PHY_RESTART); 1503 val &= ~AR_PHY_RESTART_ENA; 1504 1505 REG_WRITE(ah, AR_PHY_RESTART, val); 1506 } 1507 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 1508