1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "hw-ops.h" 20 #include "ar9003_phy.h" 21 #include "ar9003_mci.h" 22 23 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah) 24 { 25 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, 26 AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1); 27 udelay(1); 28 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, 29 AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0); 30 } 31 32 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address, 33 u32 bit_position, int time_out) 34 { 35 struct ath_common *common = ath9k_hw_common(ah); 36 37 while (time_out) { 38 if (REG_READ(ah, address) & bit_position) { 39 REG_WRITE(ah, address, bit_position); 40 41 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) { 42 if (bit_position & 43 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) 44 ar9003_mci_reset_req_wakeup(ah); 45 46 if (bit_position & 47 (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | 48 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) 49 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 50 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE); 51 52 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 53 AR_MCI_INTERRUPT_RX_MSG); 54 } 55 break; 56 } 57 58 udelay(10); 59 time_out -= 10; 60 61 if (time_out < 0) 62 break; 63 } 64 65 if (time_out <= 0) { 66 ath_dbg(common, MCI, 67 "MCI Wait for Reg 0x%08x = 0x%08x timeout\n", 68 address, bit_position); 69 ath_dbg(common, MCI, 70 "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x\n", 71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), 72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); 73 time_out = 0; 74 } 75 76 return time_out; 77 } 78 79 static void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done) 80 { 81 u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00}; 82 83 ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16, 84 wait_done, false); 85 udelay(5); 86 } 87 88 static void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done) 89 { 90 u32 payload = 0x00000000; 91 92 ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1, 93 wait_done, false); 94 } 95 96 static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done) 97 { 98 ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP, 99 NULL, 0, wait_done, false); 100 udelay(5); 101 } 102 103 static void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done) 104 { 105 ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP, 106 NULL, 0, wait_done, false); 107 } 108 109 static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done) 110 { 111 u32 payload = 0x70000000; 112 113 ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1, 114 wait_done, false); 115 } 116 117 static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done) 118 { 119 ar9003_mci_send_message(ah, MCI_SYS_SLEEPING, 120 MCI_FLAG_DISABLE_TIMESTAMP, 121 NULL, 0, wait_done, false); 122 } 123 124 static void ar9003_mci_send_coex_version_query(struct ath_hw *ah, 125 bool wait_done) 126 { 127 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 128 u32 payload[4] = {0, 0, 0, 0}; 129 130 if (!mci->bt_version_known && 131 (mci->bt_state != MCI_BT_SLEEP)) { 132 MCI_GPM_SET_TYPE_OPCODE(payload, 133 MCI_GPM_COEX_AGENT, 134 MCI_GPM_COEX_VERSION_QUERY); 135 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 136 wait_done, true); 137 } 138 } 139 140 static void ar9003_mci_send_coex_version_response(struct ath_hw *ah, 141 bool wait_done) 142 { 143 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 144 u32 payload[4] = {0, 0, 0, 0}; 145 146 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, 147 MCI_GPM_COEX_VERSION_RESPONSE); 148 *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) = 149 mci->wlan_ver_major; 150 *(((u8 *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) = 151 mci->wlan_ver_minor; 152 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true); 153 } 154 155 static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah, 156 bool wait_done) 157 { 158 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 159 u32 *payload = &mci->wlan_channels[0]; 160 161 if ((mci->wlan_channels_update == true) && 162 (mci->bt_state != MCI_BT_SLEEP)) { 163 MCI_GPM_SET_TYPE_OPCODE(payload, 164 MCI_GPM_COEX_AGENT, 165 MCI_GPM_COEX_WLAN_CHANNELS); 166 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 167 wait_done, true); 168 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff); 169 } 170 } 171 172 static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah, 173 bool wait_done, u8 query_type) 174 { 175 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 176 u32 payload[4] = {0, 0, 0, 0}; 177 bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO | 178 MCI_GPM_COEX_QUERY_BT_TOPOLOGY)); 179 180 if (mci->bt_state != MCI_BT_SLEEP) { 181 182 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, 183 MCI_GPM_COEX_STATUS_QUERY); 184 185 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type; 186 187 /* 188 * If bt_status_query message is not sent successfully, 189 * then need_flush_btinfo should be set again. 190 */ 191 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 192 wait_done, true)) { 193 if (query_btinfo) 194 mci->need_flush_btinfo = true; 195 } 196 197 if (query_btinfo) 198 mci->query_bt = false; 199 } 200 } 201 202 static void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt, 203 bool wait_done) 204 { 205 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 206 u32 payload[4] = {0, 0, 0, 0}; 207 208 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, 209 MCI_GPM_COEX_HALT_BT_GPM); 210 211 if (halt) { 212 mci->query_bt = true; 213 /* Send next unhalt no matter halt sent or not */ 214 mci->unhalt_bt_gpm = true; 215 mci->need_flush_btinfo = true; 216 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) = 217 MCI_GPM_COEX_BT_GPM_HALT; 218 } else 219 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) = 220 MCI_GPM_COEX_BT_GPM_UNHALT; 221 222 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true); 223 } 224 225 static void ar9003_mci_prep_interface(struct ath_hw *ah) 226 { 227 struct ath_common *common = ath9k_hw_common(ah); 228 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 229 u32 saved_mci_int_en; 230 u32 mci_timeout = 150; 231 232 mci->bt_state = MCI_BT_SLEEP; 233 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); 234 235 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); 236 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 237 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); 238 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 239 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); 240 241 ar9003_mci_remote_reset(ah, true); 242 ar9003_mci_send_req_wake(ah, true); 243 244 if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 245 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) { 246 247 mci->bt_state = MCI_BT_AWAKE; 248 249 /* 250 * we don't need to send more remote_reset at this moment. 251 * If BT receive first remote_reset, then BT HW will 252 * be cleaned up and will be able to receive req_wake 253 * and BT HW will respond sys_waking. 254 * In this case, WLAN will receive BT's HW sys_waking. 255 * Otherwise, if BT SW missed initial remote_reset, 256 * that remote_reset will still clean up BT MCI RX, 257 * and the req_wake will wake BT up, 258 * and BT SW will respond this req_wake with a remote_reset and 259 * sys_waking. In this case, WLAN will receive BT's SW 260 * sys_waking. In either case, BT's RX is cleaned up. So we 261 * don't need to reply BT's remote_reset now, if any. 262 * Similarly, if in any case, WLAN can receive BT's sys_waking, 263 * that means WLAN's RX is also fine. 264 */ 265 ar9003_mci_send_sys_waking(ah, true); 266 udelay(10); 267 268 /* 269 * Set BT priority interrupt value to be 0xff to 270 * avoid having too many BT PRIORITY interrupts. 271 */ 272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); 273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); 274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); 275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); 276 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF); 277 278 /* 279 * A contention reset will be received after send out 280 * sys_waking. Also BT priority interrupt bits will be set. 281 * Clear those bits before the next step. 282 */ 283 284 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 285 AR_MCI_INTERRUPT_RX_MSG_CONT_RST); 286 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 287 AR_MCI_INTERRUPT_BT_PRI); 288 289 if (mci->is_2g) { 290 ar9003_mci_send_lna_transfer(ah, true); 291 udelay(5); 292 } 293 294 if ((mci->is_2g && !mci->update_2g5g)) { 295 if (ar9003_mci_wait_for_interrupt(ah, 296 AR_MCI_INTERRUPT_RX_MSG_RAW, 297 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO, 298 mci_timeout)) 299 ath_dbg(common, MCI, 300 "MCI WLAN has control over the LNA & BT obeys it\n"); 301 else 302 ath_dbg(common, MCI, 303 "MCI BT didn't respond to LNA_TRANS\n"); 304 } 305 } 306 307 /* Clear the extra redundant SYS_WAKING from BT */ 308 if ((mci->bt_state == MCI_BT_AWAKE) && 309 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 310 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) && 311 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 312 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) { 313 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 314 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING); 315 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 316 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE); 317 } 318 319 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); 320 } 321 322 void ar9003_mci_set_full_sleep(struct ath_hw *ah) 323 { 324 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 325 326 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && 327 (mci->bt_state != MCI_BT_SLEEP) && 328 !mci->halted_bt_gpm) { 329 ar9003_mci_send_coex_halt_bt_gpm(ah, true, true); 330 } 331 332 mci->ready = false; 333 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 334 } 335 336 static void ar9003_mci_disable_interrupt(struct ath_hw *ah) 337 { 338 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); 339 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 340 } 341 342 static void ar9003_mci_enable_interrupt(struct ath_hw *ah) 343 { 344 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT); 345 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 346 AR_MCI_INTERRUPT_RX_MSG_DEFAULT); 347 } 348 349 static bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints) 350 { 351 u32 intr; 352 353 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); 354 return ((intr & ints) == ints); 355 } 356 357 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr, 358 u32 *rx_msg_intr) 359 { 360 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 361 362 *raw_intr = mci->raw_intr; 363 *rx_msg_intr = mci->rx_msg_intr; 364 365 /* Clean int bits after the values are read. */ 366 mci->raw_intr = 0; 367 mci->rx_msg_intr = 0; 368 } 369 EXPORT_SYMBOL(ar9003_mci_get_interrupt); 370 371 void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 372 { 373 struct ath_common *common = ath9k_hw_common(ah); 374 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 375 u32 raw_intr, rx_msg_intr; 376 377 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); 378 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); 379 380 if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) { 381 ath_dbg(common, MCI, 382 "MCI gets 0xdeadbeef during int processing\n"); 383 } else { 384 mci->rx_msg_intr |= rx_msg_intr; 385 mci->raw_intr |= raw_intr; 386 *masked |= ATH9K_INT_MCI; 387 388 if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) 389 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); 390 391 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); 392 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); 393 } 394 } 395 396 static void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g) 397 { 398 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 399 400 if (!mci->update_2g5g && 401 (mci->is_2g != is_2g)) 402 mci->update_2g5g = true; 403 404 mci->is_2g = is_2g; 405 } 406 407 static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index) 408 { 409 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 410 u32 *payload; 411 u32 recv_type, offset; 412 413 if (msg_index == MCI_GPM_INVALID) 414 return false; 415 416 offset = msg_index << 4; 417 418 payload = (u32 *)(mci->gpm_buf + offset); 419 recv_type = MCI_GPM_TYPE(payload); 420 421 if (recv_type == MCI_GPM_RSVD_PATTERN) 422 return false; 423 424 return true; 425 } 426 427 static void ar9003_mci_observation_set_up(struct ath_hw *ah) 428 { 429 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 430 431 if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) { 432 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA); 433 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK); 434 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); 435 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); 436 } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) { 437 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX); 438 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX); 439 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); 440 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); 441 ath9k_hw_cfg_output(ah, 5, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 442 } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) { 443 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); 444 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); 445 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); 446 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); 447 } else 448 return; 449 450 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 451 452 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1); 453 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0); 454 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); 455 456 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0); 457 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1); 458 REG_WRITE(ah, AR_OBS, 0x4b); 459 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03); 460 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01); 461 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02); 462 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03); 463 REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, 464 AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07); 465 } 466 467 static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done, 468 u8 opcode, u32 bt_flags) 469 { 470 u32 pld[4] = {0, 0, 0, 0}; 471 472 MCI_GPM_SET_TYPE_OPCODE(pld, MCI_GPM_COEX_AGENT, 473 MCI_GPM_COEX_BT_UPDATE_FLAGS); 474 475 *(((u8 *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode; 476 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF; 477 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = (bt_flags >> 8) & 0xFF; 478 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF; 479 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF; 480 481 return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, 482 wait_done, true); 483 } 484 485 static void ar9003_mci_sync_bt_state(struct ath_hw *ah) 486 { 487 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 488 u32 cur_bt_state; 489 490 cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL); 491 492 if (mci->bt_state != cur_bt_state) 493 mci->bt_state = cur_bt_state; 494 495 if (mci->bt_state != MCI_BT_SLEEP) { 496 497 ar9003_mci_send_coex_version_query(ah, true); 498 ar9003_mci_send_coex_wlan_channels(ah, true); 499 500 if (mci->unhalt_bt_gpm == true) 501 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); 502 } 503 } 504 505 void ar9003_mci_check_bt(struct ath_hw *ah) 506 { 507 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 508 509 if (!mci_hw->ready) 510 return; 511 512 /* 513 * check BT state again to make 514 * sure it's not changed. 515 */ 516 ar9003_mci_sync_bt_state(ah); 517 ar9003_mci_2g5g_switch(ah, true); 518 519 if ((mci_hw->bt_state == MCI_BT_AWAKE) && 520 (mci_hw->query_bt == true)) { 521 mci_hw->need_flush_btinfo = true; 522 } 523 } 524 525 static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type, 526 u8 gpm_opcode, u32 *p_gpm) 527 { 528 struct ath_common *common = ath9k_hw_common(ah); 529 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 530 u8 *p_data = (u8 *) p_gpm; 531 532 if (gpm_type != MCI_GPM_COEX_AGENT) 533 return; 534 535 switch (gpm_opcode) { 536 case MCI_GPM_COEX_VERSION_QUERY: 537 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n"); 538 ar9003_mci_send_coex_version_response(ah, true); 539 break; 540 case MCI_GPM_COEX_VERSION_RESPONSE: 541 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n"); 542 mci->bt_ver_major = 543 *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION); 544 mci->bt_ver_minor = 545 *(p_data + MCI_GPM_COEX_B_MINOR_VERSION); 546 mci->bt_version_known = true; 547 ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n", 548 mci->bt_ver_major, mci->bt_ver_minor); 549 break; 550 case MCI_GPM_COEX_STATUS_QUERY: 551 ath_dbg(common, MCI, 552 "MCI Recv GPM COEX Status Query = 0x%02X\n", 553 *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP)); 554 mci->wlan_channels_update = true; 555 ar9003_mci_send_coex_wlan_channels(ah, true); 556 break; 557 case MCI_GPM_COEX_BT_PROFILE_INFO: 558 mci->query_bt = true; 559 ath_dbg(common, MCI, "MCI Recv GPM COEX BT_Profile_Info\n"); 560 break; 561 case MCI_GPM_COEX_BT_STATUS_UPDATE: 562 mci->query_bt = true; 563 ath_dbg(common, MCI, 564 "MCI Recv GPM COEX BT_Status_Update SEQ=%d (drop&query)\n", 565 *(p_gpm + 3)); 566 break; 567 default: 568 break; 569 } 570 } 571 572 static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, 573 u8 gpm_opcode, int time_out) 574 { 575 struct ath_common *common = ath9k_hw_common(ah); 576 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 577 u32 *p_gpm = NULL, mismatch = 0, more_data; 578 u32 offset; 579 u8 recv_type = 0, recv_opcode = 0; 580 bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE); 581 582 more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE; 583 584 while (time_out > 0) { 585 if (p_gpm) { 586 MCI_GPM_RECYCLE(p_gpm); 587 p_gpm = NULL; 588 } 589 590 if (more_data != MCI_GPM_MORE) 591 time_out = ar9003_mci_wait_for_interrupt(ah, 592 AR_MCI_INTERRUPT_RX_MSG_RAW, 593 AR_MCI_INTERRUPT_RX_MSG_GPM, 594 time_out); 595 596 if (!time_out) 597 break; 598 599 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 600 &more_data); 601 602 if (offset == MCI_GPM_INVALID) 603 continue; 604 605 p_gpm = (u32 *) (mci->gpm_buf + offset); 606 recv_type = MCI_GPM_TYPE(p_gpm); 607 recv_opcode = MCI_GPM_OPCODE(p_gpm); 608 609 if (MCI_GPM_IS_CAL_TYPE(recv_type)) { 610 if (recv_type == gpm_type) { 611 if ((gpm_type == MCI_GPM_BT_CAL_DONE) && 612 !b_is_bt_cal_done) { 613 gpm_type = MCI_GPM_BT_CAL_GRANT; 614 continue; 615 } 616 break; 617 } 618 } else if ((recv_type == gpm_type) && (recv_opcode == gpm_opcode)) { 619 break; 620 } 621 622 /* 623 * check if it's cal_grant 624 * 625 * When we're waiting for cal_grant in reset routine, 626 * it's possible that BT sends out cal_request at the 627 * same time. Since BT's calibration doesn't happen 628 * that often, we'll let BT completes calibration then 629 * we continue to wait for cal_grant from BT. 630 * Orginal: Wait BT_CAL_GRANT. 631 * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT->wait 632 * BT_CAL_DONE -> Wait BT_CAL_GRANT. 633 */ 634 635 if ((gpm_type == MCI_GPM_BT_CAL_GRANT) && 636 (recv_type == MCI_GPM_BT_CAL_REQ)) { 637 638 u32 payload[4] = {0, 0, 0, 0}; 639 640 gpm_type = MCI_GPM_BT_CAL_DONE; 641 MCI_GPM_SET_CAL_TYPE(payload, 642 MCI_GPM_WLAN_CAL_GRANT); 643 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 644 false, false); 645 continue; 646 } else { 647 ath_dbg(common, MCI, "MCI GPM subtype not match 0x%x\n", 648 *(p_gpm + 1)); 649 mismatch++; 650 ar9003_mci_process_gpm_extra(ah, recv_type, 651 recv_opcode, p_gpm); 652 } 653 } 654 655 if (p_gpm) { 656 MCI_GPM_RECYCLE(p_gpm); 657 p_gpm = NULL; 658 } 659 660 if (time_out <= 0) 661 time_out = 0; 662 663 while (more_data == MCI_GPM_MORE) { 664 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 665 &more_data); 666 if (offset == MCI_GPM_INVALID) 667 break; 668 669 p_gpm = (u32 *) (mci->gpm_buf + offset); 670 recv_type = MCI_GPM_TYPE(p_gpm); 671 recv_opcode = MCI_GPM_OPCODE(p_gpm); 672 673 if (!MCI_GPM_IS_CAL_TYPE(recv_type)) 674 ar9003_mci_process_gpm_extra(ah, recv_type, 675 recv_opcode, p_gpm); 676 677 MCI_GPM_RECYCLE(p_gpm); 678 } 679 680 return time_out; 681 } 682 683 bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan) 684 { 685 struct ath_common *common = ath9k_hw_common(ah); 686 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 687 u32 payload[4] = {0, 0, 0, 0}; 688 689 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan)); 690 691 if (mci_hw->bt_state != MCI_BT_CAL_START) 692 return false; 693 694 mci_hw->bt_state = MCI_BT_CAL; 695 696 /* 697 * MCI FIX: disable mci interrupt here. This is to avoid 698 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and 699 * lead to mci_intr reentry. 700 */ 701 ar9003_mci_disable_interrupt(ah); 702 703 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); 704 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 705 16, true, false); 706 707 /* Wait BT calibration to be completed for 25ms */ 708 709 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, 710 0, 25000)) 711 ath_dbg(common, MCI, "MCI BT_CAL_DONE received\n"); 712 else 713 ath_dbg(common, MCI, 714 "MCI BT_CAL_DONE not received\n"); 715 716 mci_hw->bt_state = MCI_BT_AWAKE; 717 /* MCI FIX: enable mci interrupt here */ 718 ar9003_mci_enable_interrupt(ah); 719 720 return true; 721 } 722 723 int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, 724 struct ath9k_hw_cal_data *caldata) 725 { 726 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 727 728 if (!mci_hw->ready) 729 return 0; 730 731 if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP)) 732 goto exit; 733 734 if (ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) || 735 ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) { 736 737 /* 738 * BT is sleeping. Check if BT wakes up during 739 * WLAN calibration. If BT wakes up during 740 * WLAN calibration, need to go through all 741 * message exchanges again and recal. 742 */ 743 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 744 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | 745 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); 746 747 ar9003_mci_remote_reset(ah, true); 748 ar9003_mci_send_sys_waking(ah, true); 749 udelay(1); 750 751 if (IS_CHAN_2GHZ(chan)) 752 ar9003_mci_send_lna_transfer(ah, true); 753 754 mci_hw->bt_state = MCI_BT_AWAKE; 755 756 if (caldata) { 757 caldata->done_txiqcal_once = false; 758 caldata->done_txclcal_once = false; 759 caldata->rtt_hist.num_readings = 0; 760 } 761 762 if (!ath9k_hw_init_cal(ah, chan)) 763 return -EIO; 764 765 } 766 exit: 767 ar9003_mci_enable_interrupt(ah); 768 return 0; 769 } 770 771 static void ar9003_mci_mute_bt(struct ath_hw *ah) 772 { 773 /* disable all MCI messages */ 774 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000); 775 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff); 776 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff); 777 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff); 778 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff); 779 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 780 781 /* wait pending HW messages to flush out */ 782 udelay(10); 783 784 /* 785 * Send LNA_TAKE and SYS_SLEEPING when 786 * 1. reset not after resuming from full sleep 787 * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment 788 */ 789 ar9003_mci_send_lna_take(ah, true); 790 791 udelay(5); 792 793 ar9003_mci_send_sys_sleeping(ah, true); 794 } 795 796 static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable) 797 { 798 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 799 u32 thresh; 800 801 if (enable) { 802 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, 803 AR_MCI_SCHD_TABLE_2_HW_BASED, 1); 804 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, 805 AR_MCI_SCHD_TABLE_2_MEM_BASED, 1); 806 807 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) { 808 thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH); 809 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, 810 AR_BTCOEX_CTRL_AGGR_THRESH, thresh); 811 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, 812 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1); 813 } else { 814 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, 815 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0); 816 } 817 818 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL, 819 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1); 820 } else { 821 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, 822 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 823 } 824 } 825 826 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 827 bool is_full_sleep) 828 { 829 struct ath_common *common = ath9k_hw_common(ah); 830 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 831 u32 regval; 832 833 ath_dbg(common, MCI, "MCI Reset (full_sleep = %d, is_2g = %d)\n", 834 is_full_sleep, is_2g); 835 836 if (!mci->gpm_addr && !mci->sched_addr) { 837 ath_dbg(common, MCI, 838 "MCI GPM and schedule buffers are not allocated\n"); 839 return; 840 } 841 842 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { 843 ath_dbg(common, MCI, "BTCOEX control register is dead\n"); 844 return; 845 } 846 847 /* Program MCI DMA related registers */ 848 REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr); 849 REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len); 850 REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr); 851 852 /* 853 * To avoid MCI state machine be affected by incoming remote MCI msgs, 854 * MCI mode will be enabled later, right before reset the MCI TX and RX. 855 */ 856 857 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | 858 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | 859 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | 860 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | 861 SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) | 862 SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) | 863 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | 864 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) | 865 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 866 867 REG_WRITE(ah, AR_BTCOEX_CTRL, regval); 868 869 if (is_2g && !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) 870 ar9003_mci_osla_setup(ah, true); 871 else 872 ar9003_mci_osla_setup(ah, false); 873 874 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, 875 AR_BTCOEX_CTRL_SPDT_ENABLE); 876 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3, 877 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20); 878 879 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1); 880 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 881 882 regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV); 883 REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval); 884 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); 885 886 /* Resetting the Rx and Tx paths of MCI */ 887 regval = REG_READ(ah, AR_MCI_COMMAND2); 888 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX); 889 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 890 891 udelay(1); 892 893 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX); 894 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 895 896 if (is_full_sleep) { 897 ar9003_mci_mute_bt(ah); 898 udelay(100); 899 } 900 901 regval |= SM(1, AR_MCI_COMMAND2_RESET_RX); 902 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 903 udelay(1); 904 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX); 905 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 906 907 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL); 908 909 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 910 (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) | 911 SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM))); 912 913 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, 914 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 915 916 ar9003_mci_observation_set_up(ah); 917 918 mci->ready = true; 919 ar9003_mci_prep_interface(ah); 920 921 if (en_int) 922 ar9003_mci_enable_interrupt(ah); 923 } 924 925 void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep) 926 { 927 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 928 929 ar9003_mci_disable_interrupt(ah); 930 931 if (mci_hw->ready && !save_fullsleep) { 932 ar9003_mci_mute_bt(ah); 933 udelay(20); 934 REG_WRITE(ah, AR_BTCOEX_CTRL, 0); 935 } 936 937 mci_hw->bt_state = MCI_BT_SLEEP; 938 mci_hw->ready = false; 939 } 940 941 static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done) 942 { 943 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 944 u32 new_flags, to_set, to_clear; 945 946 if (mci->update_2g5g && (mci->bt_state != MCI_BT_SLEEP)) { 947 if (mci->is_2g) { 948 new_flags = MCI_2G_FLAGS; 949 to_clear = MCI_2G_FLAGS_CLEAR_MASK; 950 to_set = MCI_2G_FLAGS_SET_MASK; 951 } else { 952 new_flags = MCI_5G_FLAGS; 953 to_clear = MCI_5G_FLAGS_CLEAR_MASK; 954 to_set = MCI_5G_FLAGS_SET_MASK; 955 } 956 957 if (to_clear) 958 ar9003_mci_send_coex_bt_flags(ah, wait_done, 959 MCI_GPM_COEX_BT_FLAGS_CLEAR, 960 to_clear); 961 if (to_set) 962 ar9003_mci_send_coex_bt_flags(ah, wait_done, 963 MCI_GPM_COEX_BT_FLAGS_SET, 964 to_set); 965 } 966 } 967 968 static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, 969 u32 *payload, bool queue) 970 { 971 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 972 u8 type, opcode; 973 974 /* check if the message is to be queued */ 975 if (header != MCI_GPM) 976 return; 977 978 type = MCI_GPM_TYPE(payload); 979 opcode = MCI_GPM_OPCODE(payload); 980 981 if (type != MCI_GPM_COEX_AGENT) 982 return; 983 984 switch (opcode) { 985 case MCI_GPM_COEX_BT_UPDATE_FLAGS: 986 if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) == 987 MCI_GPM_COEX_BT_FLAGS_READ) 988 break; 989 990 mci->update_2g5g = queue; 991 992 break; 993 case MCI_GPM_COEX_WLAN_CHANNELS: 994 mci->wlan_channels_update = queue; 995 break; 996 case MCI_GPM_COEX_HALT_BT_GPM: 997 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) == 998 MCI_GPM_COEX_BT_GPM_UNHALT) { 999 mci->unhalt_bt_gpm = queue; 1000 1001 if (!queue) 1002 mci->halted_bt_gpm = false; 1003 } 1004 1005 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) == 1006 MCI_GPM_COEX_BT_GPM_HALT) { 1007 1008 mci->halted_bt_gpm = !queue; 1009 } 1010 1011 break; 1012 default: 1013 break; 1014 } 1015 } 1016 1017 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) 1018 { 1019 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1020 1021 if (mci->update_2g5g) { 1022 if (mci->is_2g) { 1023 ar9003_mci_send_2g5g_status(ah, true); 1024 ar9003_mci_send_lna_transfer(ah, true); 1025 udelay(5); 1026 1027 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, 1028 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1029 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, 1030 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1031 1032 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { 1033 REG_SET_BIT(ah, AR_BTCOEX_CTRL, 1034 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 1035 } 1036 } else { 1037 ar9003_mci_send_lna_take(ah, true); 1038 udelay(5); 1039 1040 REG_SET_BIT(ah, AR_MCI_TX_CTRL, 1041 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1042 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, 1043 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1044 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, 1045 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 1046 1047 ar9003_mci_send_2g5g_status(ah, true); 1048 } 1049 } 1050 } 1051 1052 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, 1053 u32 *payload, u8 len, bool wait_done, 1054 bool check_bt) 1055 { 1056 struct ath_common *common = ath9k_hw_common(ah); 1057 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1058 bool msg_sent = false; 1059 u32 regval; 1060 u32 saved_mci_int_en; 1061 int i; 1062 1063 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); 1064 regval = REG_READ(ah, AR_BTCOEX_CTRL); 1065 1066 if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { 1067 ath_dbg(common, MCI, 1068 "MCI Not sending 0x%x. MCI is not enabled. full_sleep = %d\n", 1069 header, (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0); 1070 ar9003_mci_queue_unsent_gpm(ah, header, payload, true); 1071 return false; 1072 } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) { 1073 ath_dbg(common, MCI, 1074 "MCI Don't send message 0x%x. BT is in sleep state\n", 1075 header); 1076 ar9003_mci_queue_unsent_gpm(ah, header, payload, true); 1077 return false; 1078 } 1079 1080 if (wait_done) 1081 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); 1082 1083 /* Need to clear SW_MSG_DONE raw bit before wait */ 1084 1085 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 1086 (AR_MCI_INTERRUPT_SW_MSG_DONE | 1087 AR_MCI_INTERRUPT_MSG_FAIL_MASK)); 1088 1089 if (payload) { 1090 for (i = 0; (i * 4) < len; i++) 1091 REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4), 1092 *(payload + i)); 1093 } 1094 1095 REG_WRITE(ah, AR_MCI_COMMAND0, 1096 (SM((flag & MCI_FLAG_DISABLE_TIMESTAMP), 1097 AR_MCI_COMMAND0_DISABLE_TIMESTAMP) | 1098 SM(len, AR_MCI_COMMAND0_LEN) | 1099 SM(header, AR_MCI_COMMAND0_HEADER))); 1100 1101 if (wait_done && 1102 !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW, 1103 AR_MCI_INTERRUPT_SW_MSG_DONE, 500))) 1104 ar9003_mci_queue_unsent_gpm(ah, header, payload, true); 1105 else { 1106 ar9003_mci_queue_unsent_gpm(ah, header, payload, false); 1107 msg_sent = true; 1108 } 1109 1110 if (wait_done) 1111 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en); 1112 1113 return msg_sent; 1114 } 1115 EXPORT_SYMBOL(ar9003_mci_send_message); 1116 1117 void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable) 1118 { 1119 struct ath_common *common = ath9k_hw_common(ah); 1120 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 1121 u32 pld[4] = {0, 0, 0, 0}; 1122 1123 if ((mci_hw->bt_state != MCI_BT_AWAKE) || 1124 (mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) 1125 return; 1126 1127 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ); 1128 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++; 1129 1130 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false); 1131 1132 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) { 1133 ath_dbg(common, MCI, "MCI BT_CAL_GRANT received\n"); 1134 } else { 1135 is_reusable = false; 1136 ath_dbg(common, MCI, "MCI BT_CAL_GRANT not received\n"); 1137 } 1138 } 1139 1140 void ar9003_mci_init_cal_done(struct ath_hw *ah) 1141 { 1142 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 1143 u32 pld[4] = {0, 0, 0, 0}; 1144 1145 if ((mci_hw->bt_state != MCI_BT_AWAKE) || 1146 (mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) 1147 return; 1148 1149 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE); 1150 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++; 1151 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false); 1152 } 1153 1154 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, 1155 u16 len, u32 sched_addr) 1156 { 1157 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1158 1159 mci->gpm_addr = gpm_addr; 1160 mci->gpm_buf = gpm_buf; 1161 mci->gpm_len = len; 1162 mci->sched_addr = sched_addr; 1163 1164 ar9003_mci_reset(ah, true, true, true); 1165 } 1166 EXPORT_SYMBOL(ar9003_mci_setup); 1167 1168 void ar9003_mci_cleanup(struct ath_hw *ah) 1169 { 1170 /* Turn off MCI and Jupiter mode. */ 1171 REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); 1172 ar9003_mci_disable_interrupt(ah); 1173 } 1174 EXPORT_SYMBOL(ar9003_mci_cleanup); 1175 1176 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) 1177 { 1178 struct ath_common *common = ath9k_hw_common(ah); 1179 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1180 u32 value = 0, more_gpm = 0, gpm_ptr; 1181 u8 query_type; 1182 1183 switch (state_type) { 1184 case MCI_STATE_ENABLE: 1185 if (mci->ready) { 1186 value = REG_READ(ah, AR_BTCOEX_CTRL); 1187 1188 if ((value == 0xdeadbeef) || (value == 0xffffffff)) 1189 value = 0; 1190 } 1191 value &= AR_BTCOEX_CTRL_MCI_MODE_EN; 1192 break; 1193 case MCI_STATE_INIT_GPM_OFFSET: 1194 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); 1195 mci->gpm_idx = value; 1196 break; 1197 case MCI_STATE_NEXT_GPM_OFFSET: 1198 case MCI_STATE_LAST_GPM_OFFSET: 1199 /* 1200 * This could be useful to avoid new GPM message interrupt which 1201 * may lead to spurious interrupt after power sleep, or multiple 1202 * entry of ath_mci_intr(). 1203 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can 1204 * alleviate this effect, but clearing GPM RX interrupt bit is 1205 * safe, because whether this is called from hw or driver code 1206 * there must be an interrupt bit set/triggered initially 1207 */ 1208 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 1209 AR_MCI_INTERRUPT_RX_MSG_GPM); 1210 1211 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); 1212 value = gpm_ptr; 1213 1214 if (value == 0) 1215 value = mci->gpm_len - 1; 1216 else if (value >= mci->gpm_len) { 1217 if (value != 0xFFFF) 1218 value = 0; 1219 } else { 1220 value--; 1221 } 1222 1223 if (value == 0xFFFF) { 1224 value = MCI_GPM_INVALID; 1225 more_gpm = MCI_GPM_NOMORE; 1226 } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) { 1227 if (gpm_ptr == mci->gpm_idx) { 1228 value = MCI_GPM_INVALID; 1229 more_gpm = MCI_GPM_NOMORE; 1230 } else { 1231 for (;;) { 1232 u32 temp_index; 1233 1234 /* skip reserved GPM if any */ 1235 1236 if (value != mci->gpm_idx) 1237 more_gpm = MCI_GPM_MORE; 1238 else 1239 more_gpm = MCI_GPM_NOMORE; 1240 1241 temp_index = mci->gpm_idx; 1242 mci->gpm_idx++; 1243 1244 if (mci->gpm_idx >= 1245 mci->gpm_len) 1246 mci->gpm_idx = 0; 1247 1248 if (ar9003_mci_is_gpm_valid(ah, 1249 temp_index)) { 1250 value = temp_index; 1251 break; 1252 } 1253 1254 if (more_gpm == MCI_GPM_NOMORE) { 1255 value = MCI_GPM_INVALID; 1256 break; 1257 } 1258 } 1259 } 1260 if (p_data) 1261 *p_data = more_gpm; 1262 } 1263 1264 if (value != MCI_GPM_INVALID) 1265 value <<= 4; 1266 1267 break; 1268 case MCI_STATE_LAST_SCHD_MSG_OFFSET: 1269 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), 1270 AR_MCI_RX_LAST_SCHD_MSG_INDEX); 1271 /* Make it in bytes */ 1272 value <<= 4; 1273 break; 1274 case MCI_STATE_REMOTE_SLEEP: 1275 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), 1276 AR_MCI_RX_REMOTE_SLEEP) ? 1277 MCI_BT_SLEEP : MCI_BT_AWAKE; 1278 break; 1279 case MCI_STATE_CONT_RSSI_POWER: 1280 value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER); 1281 break; 1282 case MCI_STATE_CONT_PRIORITY: 1283 value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY); 1284 break; 1285 case MCI_STATE_CONT_TXRX: 1286 value = MS(mci->cont_status, AR_MCI_CONT_TXRX); 1287 break; 1288 case MCI_STATE_BT: 1289 value = mci->bt_state; 1290 break; 1291 case MCI_STATE_SET_BT_SLEEP: 1292 mci->bt_state = MCI_BT_SLEEP; 1293 break; 1294 case MCI_STATE_SET_BT_AWAKE: 1295 mci->bt_state = MCI_BT_AWAKE; 1296 ar9003_mci_send_coex_version_query(ah, true); 1297 ar9003_mci_send_coex_wlan_channels(ah, true); 1298 1299 if (mci->unhalt_bt_gpm) 1300 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); 1301 1302 ar9003_mci_2g5g_switch(ah, true); 1303 break; 1304 case MCI_STATE_SET_BT_CAL_START: 1305 mci->bt_state = MCI_BT_CAL_START; 1306 break; 1307 case MCI_STATE_SET_BT_CAL: 1308 mci->bt_state = MCI_BT_CAL; 1309 break; 1310 case MCI_STATE_RESET_REQ_WAKE: 1311 ar9003_mci_reset_req_wakeup(ah); 1312 mci->update_2g5g = true; 1313 1314 if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MASK) { 1315 /* Check if we still have control of the GPIOs */ 1316 if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) & 1317 ATH_MCI_CONFIG_MCI_OBS_GPIO) != 1318 ATH_MCI_CONFIG_MCI_OBS_GPIO) { 1319 ar9003_mci_observation_set_up(ah); 1320 } 1321 } 1322 break; 1323 case MCI_STATE_SEND_WLAN_COEX_VERSION: 1324 ar9003_mci_send_coex_version_response(ah, true); 1325 break; 1326 case MCI_STATE_SET_BT_COEX_VERSION: 1327 if (!p_data) 1328 ath_dbg(common, MCI, 1329 "MCI Set BT Coex version with NULL data!!\n"); 1330 else { 1331 mci->bt_ver_major = (*p_data >> 8) & 0xff; 1332 mci->bt_ver_minor = (*p_data) & 0xff; 1333 mci->bt_version_known = true; 1334 ath_dbg(common, MCI, "MCI BT version set: %d.%d\n", 1335 mci->bt_ver_major, mci->bt_ver_minor); 1336 } 1337 break; 1338 case MCI_STATE_SEND_WLAN_CHANNELS: 1339 if (p_data) { 1340 if (((mci->wlan_channels[1] & 0xffff0000) == 1341 (*(p_data + 1) & 0xffff0000)) && 1342 (mci->wlan_channels[2] == *(p_data + 2)) && 1343 (mci->wlan_channels[3] == *(p_data + 3))) 1344 break; 1345 1346 mci->wlan_channels[0] = *p_data++; 1347 mci->wlan_channels[1] = *p_data++; 1348 mci->wlan_channels[2] = *p_data++; 1349 mci->wlan_channels[3] = *p_data++; 1350 } 1351 mci->wlan_channels_update = true; 1352 ar9003_mci_send_coex_wlan_channels(ah, true); 1353 break; 1354 case MCI_STATE_SEND_VERSION_QUERY: 1355 ar9003_mci_send_coex_version_query(ah, true); 1356 break; 1357 case MCI_STATE_SEND_STATUS_QUERY: 1358 query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY; 1359 ar9003_mci_send_coex_bt_status_query(ah, true, query_type); 1360 break; 1361 case MCI_STATE_NEED_FLUSH_BT_INFO: 1362 /* 1363 * btcoex_hw.mci.unhalt_bt_gpm means whether it's 1364 * needed to send UNHALT message. It's set whenever 1365 * there's a request to send HALT message. 1366 * mci_halted_bt_gpm means whether HALT message is sent 1367 * out successfully. 1368 * 1369 * Checking (mci_unhalt_bt_gpm == false) instead of 1370 * checking (ah->mci_halted_bt_gpm == false) will make 1371 * sure currently is in UNHALT-ed mode and BT can 1372 * respond to status query. 1373 */ 1374 value = (!mci->unhalt_bt_gpm && 1375 mci->need_flush_btinfo) ? 1 : 0; 1376 if (p_data) 1377 mci->need_flush_btinfo = 1378 (*p_data != 0) ? true : false; 1379 break; 1380 case MCI_STATE_RECOVER_RX: 1381 ar9003_mci_prep_interface(ah); 1382 mci->query_bt = true; 1383 mci->need_flush_btinfo = true; 1384 ar9003_mci_send_coex_wlan_channels(ah, true); 1385 ar9003_mci_2g5g_switch(ah, true); 1386 break; 1387 case MCI_STATE_NEED_FTP_STOMP: 1388 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP); 1389 break; 1390 case MCI_STATE_NEED_TUNING: 1391 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING); 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 return value; 1398 } 1399 EXPORT_SYMBOL(ar9003_mci_state); 1400