1 /* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include "hw.h" 17 #include "ar9003_mac.h" 18 19 static void ar9003_hw_rx_enable(struct ath_hw *hw) 20 { 21 REG_WRITE(hw, AR_CR, 0); 22 } 23 24 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) 25 { 26 int checksum; 27 28 checksum = ads->info + ads->link 29 + ads->data0 + ads->ctl3 30 + ads->data1 + ads->ctl5 31 + ads->data2 + ads->ctl7 32 + ads->data3 + ads->ctl9; 33 34 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; 35 } 36 37 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) 38 { 39 struct ar9003_txc *ads = ds; 40 41 ads->link = ds_link; 42 ads->ctl10 &= ~AR_TxPtrChkSum; 43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 44 } 45 46 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link) 47 { 48 struct ar9003_txc *ads = ds; 49 50 *ds_link = &ads->link; 51 } 52 53 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 54 { 55 u32 isr = 0; 56 u32 mask2 = 0; 57 struct ath9k_hw_capabilities *pCap = &ah->caps; 58 u32 sync_cause = 0; 59 struct ath_common *common = ath9k_hw_common(ah); 60 61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 63 == AR_RTC_STATUS_ON) 64 isr = REG_READ(ah, AR_ISR); 65 } 66 67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; 68 69 *masked = 0; 70 71 if (!isr && !sync_cause) 72 return false; 73 74 if (isr) { 75 if (isr & AR_ISR_BCNMISC) { 76 u32 isr2; 77 isr2 = REG_READ(ah, AR_ISR_S2); 78 79 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> 80 MAP_ISR_S2_TIM); 81 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> 82 MAP_ISR_S2_DTIM); 83 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> 84 MAP_ISR_S2_DTIMSYNC); 85 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> 86 MAP_ISR_S2_CABEND); 87 mask2 |= ((isr2 & AR_ISR_S2_GTT) << 88 MAP_ISR_S2_GTT); 89 mask2 |= ((isr2 & AR_ISR_S2_CST) << 90 MAP_ISR_S2_CST); 91 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> 92 MAP_ISR_S2_TSFOOR); 93 94 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 95 REG_WRITE(ah, AR_ISR_S2, isr2); 96 isr &= ~AR_ISR_BCNMISC; 97 } 98 } 99 100 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) 101 isr = REG_READ(ah, AR_ISR_RAC); 102 103 if (isr == 0xffffffff) { 104 *masked = 0; 105 return false; 106 } 107 108 *masked = isr & ATH9K_INT_COMMON; 109 110 if (ah->config.rx_intr_mitigation) 111 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 112 *masked |= ATH9K_INT_RXLP; 113 114 if (ah->config.tx_intr_mitigation) 115 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 116 *masked |= ATH9K_INT_TX; 117 118 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 119 *masked |= ATH9K_INT_RXLP; 120 121 if (isr & AR_ISR_HP_RXOK) 122 *masked |= ATH9K_INT_RXHP; 123 124 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { 125 *masked |= ATH9K_INT_TX; 126 127 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 128 u32 s0, s1; 129 s0 = REG_READ(ah, AR_ISR_S0); 130 REG_WRITE(ah, AR_ISR_S0, s0); 131 s1 = REG_READ(ah, AR_ISR_S1); 132 REG_WRITE(ah, AR_ISR_S1, s1); 133 134 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | 135 AR_ISR_TXEOL); 136 } 137 } 138 139 if (isr & AR_ISR_GENTMR) { 140 u32 s5; 141 142 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) 143 s5 = REG_READ(ah, AR_ISR_S5_S); 144 else 145 s5 = REG_READ(ah, AR_ISR_S5); 146 147 ah->intr_gen_timer_trigger = 148 MS(s5, AR_ISR_S5_GENTIMER_TRIG); 149 150 ah->intr_gen_timer_thresh = 151 MS(s5, AR_ISR_S5_GENTIMER_THRESH); 152 153 if (ah->intr_gen_timer_trigger) 154 *masked |= ATH9K_INT_GENTIMER; 155 156 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 157 REG_WRITE(ah, AR_ISR_S5, s5); 158 isr &= ~AR_ISR_GENTMR; 159 } 160 161 } 162 163 *masked |= mask2; 164 165 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 166 REG_WRITE(ah, AR_ISR, isr); 167 168 (void) REG_READ(ah, AR_ISR); 169 } 170 } 171 172 if (sync_cause) { 173 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 174 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 175 REG_WRITE(ah, AR_RC, 0); 176 *masked |= ATH9K_INT_FATAL; 177 } 178 179 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 180 ath_print(common, ATH_DBG_INTERRUPT, 181 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 182 183 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 184 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 185 186 } 187 return true; 188 } 189 190 static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, 191 bool is_firstseg, bool is_lastseg, 192 const void *ds0, dma_addr_t buf_addr, 193 unsigned int qcu) 194 { 195 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 196 unsigned int descid = 0; 197 198 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) | 199 (1 << AR_TxRxDesc_S) | 200 (1 << AR_CtrlStat_S) | 201 (qcu << AR_TxQcuNum_S) | 0x17; 202 203 ads->data0 = buf_addr; 204 ads->data1 = 0; 205 ads->data2 = 0; 206 ads->data3 = 0; 207 208 ads->ctl3 = (seglen << AR_BufLen_S); 209 ads->ctl3 &= AR_BufLen; 210 211 /* Fill in pointer checksum and descriptor id */ 212 ads->ctl10 = ar9003_calc_ptr_chksum(ads); 213 ads->ctl10 |= (descid << AR_TxDescId_S); 214 215 if (is_firstseg) { 216 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore); 217 } else if (is_lastseg) { 218 ads->ctl11 = 0; 219 ads->ctl12 = 0; 220 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13; 221 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14; 222 } else { 223 /* XXX Intermediate descriptor in a multi-descriptor frame.*/ 224 ads->ctl11 = 0; 225 ads->ctl12 = AR_TxMore; 226 ads->ctl13 = 0; 227 ads->ctl14 = 0; 228 } 229 } 230 231 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 232 struct ath_tx_status *ts) 233 { 234 struct ar9003_txs *ads; 235 236 ads = &ah->ts_ring[ah->ts_tail]; 237 238 if ((ads->status8 & AR_TxDone) == 0) 239 return -EINPROGRESS; 240 241 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 242 243 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 244 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 245 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 246 "Tx Descriptor error %x\n", ads->ds_info); 247 memset(ads, 0, sizeof(*ads)); 248 return -EIO; 249 } 250 251 ts->qid = MS(ads->ds_info, AR_TxQcuNum); 252 ts->desc_id = MS(ads->status1, AR_TxDescId); 253 ts->ts_seqnum = MS(ads->status8, AR_SeqNum); 254 ts->ts_tstamp = ads->status4; 255 ts->ts_status = 0; 256 ts->ts_flags = 0; 257 258 if (ads->status3 & AR_ExcessiveRetries) 259 ts->ts_status |= ATH9K_TXERR_XRETRY; 260 if (ads->status3 & AR_Filtered) 261 ts->ts_status |= ATH9K_TXERR_FILT; 262 if (ads->status3 & AR_FIFOUnderrun) { 263 ts->ts_status |= ATH9K_TXERR_FIFO; 264 ath9k_hw_updatetxtriglevel(ah, true); 265 } 266 if (ads->status8 & AR_TxOpExceeded) 267 ts->ts_status |= ATH9K_TXERR_XTXOP; 268 if (ads->status3 & AR_TxTimerExpired) 269 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 270 271 if (ads->status3 & AR_DescCfgErr) 272 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 273 if (ads->status3 & AR_TxDataUnderrun) { 274 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 275 ath9k_hw_updatetxtriglevel(ah, true); 276 } 277 if (ads->status3 & AR_TxDelimUnderrun) { 278 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 279 ath9k_hw_updatetxtriglevel(ah, true); 280 } 281 if (ads->status2 & AR_TxBaStatus) { 282 ts->ts_flags |= ATH9K_TX_BA; 283 ts->ba_low = ads->status5; 284 ts->ba_high = ads->status6; 285 } 286 287 ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx); 288 289 ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined); 290 ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00); 291 ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01); 292 ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02); 293 ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10); 294 ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11); 295 ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12); 296 ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt); 297 ts->ts_longretry = MS(ads->status3, AR_DataFailCnt); 298 ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt); 299 ts->ts_antenna = 0; 300 301 ts->tid = MS(ads->status8, AR_TxTid); 302 303 memset(ads, 0, sizeof(*ads)); 304 305 return 0; 306 } 307 308 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds, 309 u32 pktlen, enum ath9k_pkt_type type, u32 txpower, 310 u32 keyIx, enum ath9k_key_type keyType, u32 flags) 311 { 312 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 313 314 if (txpower > ah->txpower_limit) 315 txpower = ah->txpower_limit; 316 317 txpower += ah->txpower_indexoffset; 318 if (txpower > 63) 319 txpower = 63; 320 321 ads->ctl11 = (pktlen & AR_FrameLen) 322 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 323 | SM(txpower, AR_XmitPower) 324 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 325 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 326 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 327 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0); 328 329 ads->ctl12 = 330 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) 331 | SM(type, AR_FrameType) 332 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 333 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 334 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 335 336 ads->ctl17 = SM(keyType, AR_EncrType) | 337 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); 338 ads->ctl18 = 0; 339 ads->ctl19 = AR_Not_Sounding; 340 341 ads->ctl20 = 0; 342 ads->ctl21 = 0; 343 ads->ctl22 = 0; 344 } 345 346 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, 347 void *lastds, 348 u32 durUpdateEn, u32 rtsctsRate, 349 u32 rtsctsDuration, 350 struct ath9k_11n_rate_series series[], 351 u32 nseries, u32 flags) 352 { 353 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 354 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds; 355 u_int32_t ctl11; 356 357 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { 358 ctl11 = ads->ctl11; 359 360 if (flags & ATH9K_TXDESC_RTSENA) { 361 ctl11 &= ~AR_CTSEnable; 362 ctl11 |= AR_RTSEnable; 363 } else { 364 ctl11 &= ~AR_RTSEnable; 365 ctl11 |= AR_CTSEnable; 366 } 367 368 ads->ctl11 = ctl11; 369 } else { 370 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable)); 371 } 372 373 ads->ctl13 = set11nTries(series, 0) 374 | set11nTries(series, 1) 375 | set11nTries(series, 2) 376 | set11nTries(series, 3) 377 | (durUpdateEn ? AR_DurUpdateEna : 0) 378 | SM(0, AR_BurstDur); 379 380 ads->ctl14 = set11nRate(series, 0) 381 | set11nRate(series, 1) 382 | set11nRate(series, 2) 383 | set11nRate(series, 3); 384 385 ads->ctl15 = set11nPktDurRTSCTS(series, 0) 386 | set11nPktDurRTSCTS(series, 1); 387 388 ads->ctl16 = set11nPktDurRTSCTS(series, 2) 389 | set11nPktDurRTSCTS(series, 3); 390 391 ads->ctl18 = set11nRateFlags(series, 0) 392 | set11nRateFlags(series, 1) 393 | set11nRateFlags(series, 2) 394 | set11nRateFlags(series, 3) 395 | SM(rtsctsRate, AR_RTSCTSRate); 396 ads->ctl19 = AR_Not_Sounding; 397 398 last_ads->ctl13 = ads->ctl13; 399 last_ads->ctl14 = ads->ctl14; 400 } 401 402 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 403 u32 aggrLen) 404 { 405 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 406 407 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 408 409 ads->ctl17 &= ~AR_AggrLen; 410 ads->ctl17 |= SM(aggrLen, AR_AggrLen); 411 } 412 413 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 414 u32 numDelims) 415 { 416 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 417 unsigned int ctl17; 418 419 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 420 421 /* 422 * We use a stack variable to manipulate ctl6 to reduce uncached 423 * read modify, modfiy, write. 424 */ 425 ctl17 = ads->ctl17; 426 ctl17 &= ~AR_PadDelim; 427 ctl17 |= SM(numDelims, AR_PadDelim); 428 ads->ctl17 = ctl17; 429 } 430 431 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) 432 { 433 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 434 435 ads->ctl12 |= AR_IsAggr; 436 ads->ctl12 &= ~AR_MoreAggr; 437 ads->ctl17 &= ~AR_PadDelim; 438 } 439 440 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds) 441 { 442 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 443 444 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr); 445 } 446 447 static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds, 448 u32 burstDuration) 449 { 450 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 451 452 ads->ctl13 &= ~AR_BurstDur; 453 ads->ctl13 |= SM(burstDuration, AR_BurstDur); 454 455 } 456 457 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds, 458 u32 vmf) 459 { 460 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 461 462 if (vmf) 463 ads->ctl11 |= AR_VirtMoreFrag; 464 else 465 ads->ctl11 &= ~AR_VirtMoreFrag; 466 } 467 468 void ar9003_hw_attach_mac_ops(struct ath_hw *hw) 469 { 470 struct ath_hw_ops *ops = ath9k_hw_ops(hw); 471 472 ops->rx_enable = ar9003_hw_rx_enable; 473 ops->set_desc_link = ar9003_hw_set_desc_link; 474 ops->get_desc_link = ar9003_hw_get_desc_link; 475 ops->get_isr = ar9003_hw_get_isr; 476 ops->fill_txdesc = ar9003_hw_fill_txdesc; 477 ops->proc_txdesc = ar9003_hw_proc_txdesc; 478 ops->set11n_txdesc = ar9003_hw_set11n_txdesc; 479 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario; 480 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first; 481 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle; 482 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last; 483 ops->clr11n_aggr = ar9003_hw_clr11n_aggr; 484 ops->set11n_burstduration = ar9003_hw_set11n_burstduration; 485 ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag; 486 } 487 488 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) 489 { 490 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); 491 } 492 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); 493 494 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 495 enum ath9k_rx_qtype qtype) 496 { 497 if (qtype == ATH9K_RX_QUEUE_HP) 498 REG_WRITE(ah, AR_HP_RXDP, rxdp); 499 else 500 REG_WRITE(ah, AR_LP_RXDP, rxdp); 501 } 502 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); 503 504 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, 505 void *buf_addr) 506 { 507 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr; 508 unsigned int phyerr; 509 510 /* TODO: byte swap on big endian for ar9300_10 */ 511 512 if ((rxsp->status11 & AR_RxDone) == 0) 513 return -EINPROGRESS; 514 515 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) 516 return -EINVAL; 517 518 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) 519 return -EINPROGRESS; 520 521 if (!rxs) 522 return 0; 523 524 rxs->rs_status = 0; 525 rxs->rs_flags = 0; 526 527 rxs->rs_datalen = rxsp->status2 & AR_DataLen; 528 rxs->rs_tstamp = rxsp->status3; 529 530 /* XXX: Keycache */ 531 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); 532 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); 533 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); 534 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); 535 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); 536 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); 537 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); 538 539 if (rxsp->status11 & AR_RxKeyIdxValid) 540 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); 541 else 542 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; 543 544 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); 545 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; 546 547 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; 548 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; 549 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); 550 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0; 551 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0; 552 553 rxs->evm0 = rxsp->status6; 554 rxs->evm1 = rxsp->status7; 555 rxs->evm2 = rxsp->status8; 556 rxs->evm3 = rxsp->status9; 557 rxs->evm4 = (rxsp->status10 & 0xffff); 558 559 if (rxsp->status11 & AR_PreDelimCRCErr) 560 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 561 562 if (rxsp->status11 & AR_PostDelimCRCErr) 563 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 564 565 if (rxsp->status11 & AR_DecryptBusyErr) 566 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 567 568 if ((rxsp->status11 & AR_RxFrameOK) == 0) { 569 if (rxsp->status11 & AR_CRCErr) { 570 rxs->rs_status |= ATH9K_RXERR_CRC; 571 } else if (rxsp->status11 & AR_PHYErr) { 572 rxs->rs_status |= ATH9K_RXERR_PHY; 573 phyerr = MS(rxsp->status11, AR_PHYErrCode); 574 rxs->rs_phyerr = phyerr; 575 } else if (rxsp->status11 & AR_DecryptCRCErr) { 576 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 577 } else if (rxsp->status11 & AR_MichaelErr) { 578 rxs->rs_status |= ATH9K_RXERR_MIC; 579 } 580 } 581 582 return 0; 583 } 584 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); 585 586 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) 587 { 588 ah->ts_tail = 0; 589 590 memset((void *) ah->ts_ring, 0, 591 ah->ts_size * sizeof(struct ar9003_txs)); 592 593 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 594 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 595 ah->ts_paddr_start, ah->ts_paddr_end, 596 ah->ts_ring, ah->ts_size); 597 598 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 599 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 600 } 601 602 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 603 u32 ts_paddr_start, 604 u8 size) 605 { 606 607 ah->ts_paddr_start = ts_paddr_start; 608 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); 609 ah->ts_size = size; 610 ah->ts_ring = (struct ar9003_txs *) ts_start; 611 612 ath9k_hw_reset_txstatus_ring(ah); 613 } 614 EXPORT_SYMBOL(ath9k_hw_setup_statusring); 615