1 /* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include "hw.h" 17 #include "ar9003_mac.h" 18 19 static void ar9003_hw_rx_enable(struct ath_hw *hw) 20 { 21 REG_WRITE(hw, AR_CR, 0); 22 } 23 24 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) 25 { 26 int checksum; 27 28 checksum = ads->info + ads->link 29 + ads->data0 + ads->ctl3 30 + ads->data1 + ads->ctl5 31 + ads->data2 + ads->ctl7 32 + ads->data3 + ads->ctl9; 33 34 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; 35 } 36 37 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) 38 { 39 struct ar9003_txc *ads = ds; 40 41 ads->link = ds_link; 42 ads->ctl10 &= ~AR_TxPtrChkSum; 43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 44 } 45 46 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link) 47 { 48 struct ar9003_txc *ads = ds; 49 50 *ds_link = &ads->link; 51 } 52 53 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 54 { 55 u32 isr = 0; 56 u32 mask2 = 0; 57 struct ath9k_hw_capabilities *pCap = &ah->caps; 58 u32 sync_cause = 0; 59 struct ath_common *common = ath9k_hw_common(ah); 60 61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 63 == AR_RTC_STATUS_ON) 64 isr = REG_READ(ah, AR_ISR); 65 } 66 67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; 68 69 *masked = 0; 70 71 if (!isr && !sync_cause) 72 return false; 73 74 if (isr) { 75 if (isr & AR_ISR_BCNMISC) { 76 u32 isr2; 77 isr2 = REG_READ(ah, AR_ISR_S2); 78 79 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> 80 MAP_ISR_S2_TIM); 81 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> 82 MAP_ISR_S2_DTIM); 83 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> 84 MAP_ISR_S2_DTIMSYNC); 85 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> 86 MAP_ISR_S2_CABEND); 87 mask2 |= ((isr2 & AR_ISR_S2_GTT) << 88 MAP_ISR_S2_GTT); 89 mask2 |= ((isr2 & AR_ISR_S2_CST) << 90 MAP_ISR_S2_CST); 91 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> 92 MAP_ISR_S2_TSFOOR); 93 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> 94 MAP_ISR_S2_BB_WATCHDOG); 95 96 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 97 REG_WRITE(ah, AR_ISR_S2, isr2); 98 isr &= ~AR_ISR_BCNMISC; 99 } 100 } 101 102 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) 103 isr = REG_READ(ah, AR_ISR_RAC); 104 105 if (isr == 0xffffffff) { 106 *masked = 0; 107 return false; 108 } 109 110 *masked = isr & ATH9K_INT_COMMON; 111 112 if (ah->config.rx_intr_mitigation) 113 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 114 *masked |= ATH9K_INT_RXLP; 115 116 if (ah->config.tx_intr_mitigation) 117 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 118 *masked |= ATH9K_INT_TX; 119 120 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 121 *masked |= ATH9K_INT_RXLP; 122 123 if (isr & AR_ISR_HP_RXOK) 124 *masked |= ATH9K_INT_RXHP; 125 126 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { 127 *masked |= ATH9K_INT_TX; 128 129 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 130 u32 s0, s1; 131 s0 = REG_READ(ah, AR_ISR_S0); 132 REG_WRITE(ah, AR_ISR_S0, s0); 133 s1 = REG_READ(ah, AR_ISR_S1); 134 REG_WRITE(ah, AR_ISR_S1, s1); 135 136 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | 137 AR_ISR_TXEOL); 138 } 139 } 140 141 if (isr & AR_ISR_GENTMR) { 142 u32 s5; 143 144 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) 145 s5 = REG_READ(ah, AR_ISR_S5_S); 146 else 147 s5 = REG_READ(ah, AR_ISR_S5); 148 149 ah->intr_gen_timer_trigger = 150 MS(s5, AR_ISR_S5_GENTIMER_TRIG); 151 152 ah->intr_gen_timer_thresh = 153 MS(s5, AR_ISR_S5_GENTIMER_THRESH); 154 155 if (ah->intr_gen_timer_trigger) 156 *masked |= ATH9K_INT_GENTIMER; 157 158 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 159 REG_WRITE(ah, AR_ISR_S5, s5); 160 isr &= ~AR_ISR_GENTMR; 161 } 162 163 } 164 165 *masked |= mask2; 166 167 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 168 REG_WRITE(ah, AR_ISR, isr); 169 170 (void) REG_READ(ah, AR_ISR); 171 } 172 173 if (*masked & ATH9K_INT_BB_WATCHDOG) 174 ar9003_hw_bb_watchdog_read(ah); 175 } 176 177 if (sync_cause) { 178 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 179 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 180 REG_WRITE(ah, AR_RC, 0); 181 *masked |= ATH9K_INT_FATAL; 182 } 183 184 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 185 ath_dbg(common, ATH_DBG_INTERRUPT, 186 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 187 188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 190 191 } 192 return true; 193 } 194 195 static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, 196 bool is_firstseg, bool is_lastseg, 197 const void *ds0, dma_addr_t buf_addr, 198 unsigned int qcu) 199 { 200 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 201 unsigned int descid = 0; 202 203 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) | 204 (1 << AR_TxRxDesc_S) | 205 (1 << AR_CtrlStat_S) | 206 (qcu << AR_TxQcuNum_S) | 0x17; 207 208 ads->data0 = buf_addr; 209 ads->data1 = 0; 210 ads->data2 = 0; 211 ads->data3 = 0; 212 213 ads->ctl3 = (seglen << AR_BufLen_S); 214 ads->ctl3 &= AR_BufLen; 215 216 /* Fill in pointer checksum and descriptor id */ 217 ads->ctl10 = ar9003_calc_ptr_chksum(ads); 218 ads->ctl10 |= (descid << AR_TxDescId_S); 219 220 if (is_firstseg) { 221 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore); 222 } else if (is_lastseg) { 223 ads->ctl11 = 0; 224 ads->ctl12 = 0; 225 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13; 226 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14; 227 } else { 228 /* XXX Intermediate descriptor in a multi-descriptor frame.*/ 229 ads->ctl11 = 0; 230 ads->ctl12 = AR_TxMore; 231 ads->ctl13 = 0; 232 ads->ctl14 = 0; 233 } 234 } 235 236 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 237 struct ath_tx_status *ts) 238 { 239 struct ar9003_txs *ads; 240 u32 status; 241 242 ads = &ah->ts_ring[ah->ts_tail]; 243 244 status = ACCESS_ONCE(ads->status8); 245 if ((status & AR_TxDone) == 0) 246 return -EINPROGRESS; 247 248 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 249 250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 252 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 253 "Tx Descriptor error %x\n", ads->ds_info); 254 memset(ads, 0, sizeof(*ads)); 255 return -EIO; 256 } 257 258 if (status & AR_TxOpExceeded) 259 ts->ts_status |= ATH9K_TXERR_XTXOP; 260 ts->ts_rateindex = MS(status, AR_FinalTxIdx); 261 ts->ts_seqnum = MS(status, AR_SeqNum); 262 ts->tid = MS(status, AR_TxTid); 263 264 ts->qid = MS(ads->ds_info, AR_TxQcuNum); 265 ts->desc_id = MS(ads->status1, AR_TxDescId); 266 ts->ts_tstamp = ads->status4; 267 ts->ts_status = 0; 268 ts->ts_flags = 0; 269 270 status = ACCESS_ONCE(ads->status2); 271 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); 272 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); 273 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); 274 if (status & AR_TxBaStatus) { 275 ts->ts_flags |= ATH9K_TX_BA; 276 ts->ba_low = ads->status5; 277 ts->ba_high = ads->status6; 278 } 279 280 status = ACCESS_ONCE(ads->status3); 281 if (status & AR_ExcessiveRetries) 282 ts->ts_status |= ATH9K_TXERR_XRETRY; 283 if (status & AR_Filtered) 284 ts->ts_status |= ATH9K_TXERR_FILT; 285 if (status & AR_FIFOUnderrun) { 286 ts->ts_status |= ATH9K_TXERR_FIFO; 287 ath9k_hw_updatetxtriglevel(ah, true); 288 } 289 if (status & AR_TxTimerExpired) 290 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 291 if (status & AR_DescCfgErr) 292 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 293 if (status & AR_TxDataUnderrun) { 294 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 295 ath9k_hw_updatetxtriglevel(ah, true); 296 } 297 if (status & AR_TxDelimUnderrun) { 298 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 299 ath9k_hw_updatetxtriglevel(ah, true); 300 } 301 ts->ts_shortretry = MS(status, AR_RTSFailCnt); 302 ts->ts_longretry = MS(status, AR_DataFailCnt); 303 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); 304 305 status = ACCESS_ONCE(ads->status7); 306 ts->ts_rssi = MS(status, AR_TxRSSICombined); 307 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); 308 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); 309 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); 310 311 memset(ads, 0, sizeof(*ads)); 312 313 return 0; 314 } 315 316 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds, 317 u32 pktlen, enum ath9k_pkt_type type, u32 txpower, 318 u32 keyIx, enum ath9k_key_type keyType, u32 flags) 319 { 320 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 321 322 if (txpower > ah->txpower_limit) 323 txpower = ah->txpower_limit; 324 325 if (txpower > 63) 326 txpower = 63; 327 328 ads->ctl11 = (pktlen & AR_FrameLen) 329 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 330 | SM(txpower, AR_XmitPower) 331 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 332 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 333 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 334 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0); 335 336 ads->ctl12 = 337 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) 338 | SM(type, AR_FrameType) 339 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 340 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 341 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 342 343 ads->ctl17 = SM(keyType, AR_EncrType) | 344 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); 345 ads->ctl18 = 0; 346 ads->ctl19 = AR_Not_Sounding; 347 348 ads->ctl20 = 0; 349 ads->ctl21 = 0; 350 ads->ctl22 = 0; 351 } 352 353 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, 354 void *lastds, 355 u32 durUpdateEn, u32 rtsctsRate, 356 u32 rtsctsDuration, 357 struct ath9k_11n_rate_series series[], 358 u32 nseries, u32 flags) 359 { 360 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 361 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds; 362 u_int32_t ctl11; 363 364 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { 365 ctl11 = ads->ctl11; 366 367 if (flags & ATH9K_TXDESC_RTSENA) { 368 ctl11 &= ~AR_CTSEnable; 369 ctl11 |= AR_RTSEnable; 370 } else { 371 ctl11 &= ~AR_RTSEnable; 372 ctl11 |= AR_CTSEnable; 373 } 374 375 ads->ctl11 = ctl11; 376 } else { 377 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable)); 378 } 379 380 ads->ctl13 = set11nTries(series, 0) 381 | set11nTries(series, 1) 382 | set11nTries(series, 2) 383 | set11nTries(series, 3) 384 | (durUpdateEn ? AR_DurUpdateEna : 0) 385 | SM(0, AR_BurstDur); 386 387 ads->ctl14 = set11nRate(series, 0) 388 | set11nRate(series, 1) 389 | set11nRate(series, 2) 390 | set11nRate(series, 3); 391 392 ads->ctl15 = set11nPktDurRTSCTS(series, 0) 393 | set11nPktDurRTSCTS(series, 1); 394 395 ads->ctl16 = set11nPktDurRTSCTS(series, 2) 396 | set11nPktDurRTSCTS(series, 3); 397 398 ads->ctl18 = set11nRateFlags(series, 0) 399 | set11nRateFlags(series, 1) 400 | set11nRateFlags(series, 2) 401 | set11nRateFlags(series, 3) 402 | SM(rtsctsRate, AR_RTSCTSRate); 403 ads->ctl19 = AR_Not_Sounding; 404 405 last_ads->ctl13 = ads->ctl13; 406 last_ads->ctl14 = ads->ctl14; 407 } 408 409 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 410 u32 aggrLen) 411 { 412 #define FIRST_DESC_NDELIMS 60 413 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 414 415 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 416 417 if (ah->ent_mode & AR_ENT_OTP_MPSD) { 418 u32 ctl17, ndelim; 419 /* 420 * Add delimiter when using RTS/CTS with aggregation 421 * and non enterprise AR9003 card 422 */ 423 ctl17 = ads->ctl17; 424 ndelim = MS(ctl17, AR_PadDelim); 425 426 if (ndelim < FIRST_DESC_NDELIMS) { 427 aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4; 428 ndelim = FIRST_DESC_NDELIMS; 429 } 430 431 ctl17 &= ~AR_AggrLen; 432 ctl17 |= SM(aggrLen, AR_AggrLen); 433 434 ctl17 &= ~AR_PadDelim; 435 ctl17 |= SM(ndelim, AR_PadDelim); 436 437 ads->ctl17 = ctl17; 438 } else { 439 ads->ctl17 &= ~AR_AggrLen; 440 ads->ctl17 |= SM(aggrLen, AR_AggrLen); 441 } 442 } 443 444 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 445 u32 numDelims) 446 { 447 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 448 unsigned int ctl17; 449 450 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr); 451 452 /* 453 * We use a stack variable to manipulate ctl6 to reduce uncached 454 * read modify, modfiy, write. 455 */ 456 ctl17 = ads->ctl17; 457 ctl17 &= ~AR_PadDelim; 458 ctl17 |= SM(numDelims, AR_PadDelim); 459 ads->ctl17 = ctl17; 460 } 461 462 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) 463 { 464 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 465 466 ads->ctl12 |= AR_IsAggr; 467 ads->ctl12 &= ~AR_MoreAggr; 468 ads->ctl17 &= ~AR_PadDelim; 469 } 470 471 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds) 472 { 473 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 474 475 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr); 476 } 477 478 static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds, 479 u32 burstDuration) 480 { 481 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 482 483 ads->ctl13 &= ~AR_BurstDur; 484 ads->ctl13 |= SM(burstDuration, AR_BurstDur); 485 486 } 487 488 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds, 489 u32 vmf) 490 { 491 struct ar9003_txc *ads = (struct ar9003_txc *) ds; 492 493 if (vmf) 494 ads->ctl11 |= AR_VirtMoreFrag; 495 else 496 ads->ctl11 &= ~AR_VirtMoreFrag; 497 } 498 499 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains) 500 { 501 struct ar9003_txc *ads = ds; 502 503 ads->ctl12 |= SM(chains, AR_PAPRDChainMask); 504 } 505 EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc); 506 507 void ar9003_hw_attach_mac_ops(struct ath_hw *hw) 508 { 509 struct ath_hw_ops *ops = ath9k_hw_ops(hw); 510 511 ops->rx_enable = ar9003_hw_rx_enable; 512 ops->set_desc_link = ar9003_hw_set_desc_link; 513 ops->get_desc_link = ar9003_hw_get_desc_link; 514 ops->get_isr = ar9003_hw_get_isr; 515 ops->fill_txdesc = ar9003_hw_fill_txdesc; 516 ops->proc_txdesc = ar9003_hw_proc_txdesc; 517 ops->set11n_txdesc = ar9003_hw_set11n_txdesc; 518 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario; 519 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first; 520 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle; 521 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last; 522 ops->clr11n_aggr = ar9003_hw_clr11n_aggr; 523 ops->set11n_burstduration = ar9003_hw_set11n_burstduration; 524 ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag; 525 } 526 527 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) 528 { 529 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); 530 } 531 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); 532 533 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 534 enum ath9k_rx_qtype qtype) 535 { 536 if (qtype == ATH9K_RX_QUEUE_HP) 537 REG_WRITE(ah, AR_HP_RXDP, rxdp); 538 else 539 REG_WRITE(ah, AR_LP_RXDP, rxdp); 540 } 541 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); 542 543 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, 544 void *buf_addr) 545 { 546 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr; 547 unsigned int phyerr; 548 549 /* TODO: byte swap on big endian for ar9300_10 */ 550 551 if ((rxsp->status11 & AR_RxDone) == 0) 552 return -EINPROGRESS; 553 554 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) 555 return -EINVAL; 556 557 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) 558 return -EINPROGRESS; 559 560 if (!rxs) 561 return 0; 562 563 rxs->rs_status = 0; 564 rxs->rs_flags = 0; 565 566 rxs->rs_datalen = rxsp->status2 & AR_DataLen; 567 rxs->rs_tstamp = rxsp->status3; 568 569 /* XXX: Keycache */ 570 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); 571 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); 572 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); 573 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); 574 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); 575 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); 576 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); 577 578 if (rxsp->status11 & AR_RxKeyIdxValid) 579 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); 580 else 581 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; 582 583 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); 584 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; 585 586 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; 587 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; 588 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); 589 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0; 590 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0; 591 592 rxs->evm0 = rxsp->status6; 593 rxs->evm1 = rxsp->status7; 594 rxs->evm2 = rxsp->status8; 595 rxs->evm3 = rxsp->status9; 596 rxs->evm4 = (rxsp->status10 & 0xffff); 597 598 if (rxsp->status11 & AR_PreDelimCRCErr) 599 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 600 601 if (rxsp->status11 & AR_PostDelimCRCErr) 602 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 603 604 if (rxsp->status11 & AR_DecryptBusyErr) 605 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 606 607 if ((rxsp->status11 & AR_RxFrameOK) == 0) { 608 /* 609 * AR_CRCErr will bet set to true if we're on the last 610 * subframe and the AR_PostDelimCRCErr is caught. 611 * In a way this also gives us a guarantee that when 612 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot 613 * possibly be reviewing the last subframe. AR_CRCErr 614 * is the CRC of the actual data. 615 */ 616 if (rxsp->status11 & AR_CRCErr) 617 rxs->rs_status |= ATH9K_RXERR_CRC; 618 else if (rxsp->status11 & AR_PHYErr) { 619 phyerr = MS(rxsp->status11, AR_PHYErrCode); 620 /* 621 * If we reach a point here where AR_PostDelimCRCErr is 622 * true it implies we're *not* on the last subframe. In 623 * in that case that we know already that the CRC of 624 * the frame was OK, and MAC would send an ACK for that 625 * subframe, even if we did get a phy error of type 626 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable 627 * to frame that are prior to the last subframe. 628 * The AR_PostDelimCRCErr is the CRC for the MPDU 629 * delimiter, which contains the 4 reserved bits, 630 * the MPDU length (12 bits), and follows the MPDU 631 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). 632 */ 633 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && 634 (rxsp->status11 & AR_PostDelimCRCErr)) { 635 rxs->rs_phyerr = 0; 636 } else { 637 rxs->rs_status |= ATH9K_RXERR_PHY; 638 rxs->rs_phyerr = phyerr; 639 } 640 641 } else if (rxsp->status11 & AR_DecryptCRCErr) 642 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 643 else if (rxsp->status11 & AR_MichaelErr) 644 rxs->rs_status |= ATH9K_RXERR_MIC; 645 646 if (rxsp->status11 & AR_KeyMiss) 647 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 648 } 649 650 return 0; 651 } 652 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); 653 654 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) 655 { 656 ah->ts_tail = 0; 657 658 memset((void *) ah->ts_ring, 0, 659 ah->ts_size * sizeof(struct ar9003_txs)); 660 661 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 662 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 663 ah->ts_paddr_start, ah->ts_paddr_end, 664 ah->ts_ring, ah->ts_size); 665 666 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 667 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 668 } 669 670 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 671 u32 ts_paddr_start, 672 u8 size) 673 { 674 675 ah->ts_paddr_start = ts_paddr_start; 676 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); 677 ah->ts_size = size; 678 ah->ts_ring = (struct ar9003_txs *) ts_start; 679 680 ath9k_hw_reset_txstatus_ring(ah); 681 } 682 EXPORT_SYMBOL(ath9k_hw_setup_statusring); 683