1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_2p2_initvals.h" 20 #include "ar9485_initvals.h" 21 #include "ar9340_initvals.h" 22 #include "ar9330_1p1_initvals.h" 23 #include "ar9330_1p2_initvals.h" 24 #include "ar955x_1p0_initvals.h" 25 #include "ar9580_1p0_initvals.h" 26 #include "ar9462_2p0_initvals.h" 27 #include "ar9462_2p1_initvals.h" 28 #include "ar9565_1p0_initvals.h" 29 30 /* General hardware code for the AR9003 hadware family */ 31 32 /* 33 * The AR9003 family uses a new INI format (pre, core, post 34 * arrays per subsystem). This provides support for the 35 * AR9003 2.2 chipsets. 36 */ 37 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 38 { 39 if (AR_SREV_9330_11(ah)) { 40 /* mac */ 41 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 42 ar9331_1p1_mac_core); 43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 44 ar9331_1p1_mac_postamble); 45 46 /* bb */ 47 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 48 ar9331_1p1_baseband_core); 49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 50 ar9331_1p1_baseband_postamble); 51 52 /* radio */ 53 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 54 ar9331_1p1_radio_core); 55 56 /* soc */ 57 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 58 ar9331_1p1_soc_preamble); 59 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 60 ar9331_1p1_soc_postamble); 61 62 /* rx/tx gain */ 63 INIT_INI_ARRAY(&ah->iniModesRxGain, 64 ar9331_common_rx_gain_1p1); 65 INIT_INI_ARRAY(&ah->iniModesTxGain, 66 ar9331_modes_lowest_ob_db_tx_gain_1p1); 67 68 /* Japan 2484 Mhz CCK */ 69 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 70 ar9331_1p1_baseband_core_txfir_coeff_japan_2484); 71 72 /* additional clock settings */ 73 if (ah->is_clk_25mhz) 74 INIT_INI_ARRAY(&ah->iniAdditional, 75 ar9331_1p1_xtal_25M); 76 else 77 INIT_INI_ARRAY(&ah->iniAdditional, 78 ar9331_1p1_xtal_40M); 79 } else if (AR_SREV_9330_12(ah)) { 80 /* mac */ 81 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 82 ar9331_1p2_mac_core); 83 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 84 ar9331_1p2_mac_postamble); 85 86 /* bb */ 87 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 88 ar9331_1p2_baseband_core); 89 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 90 ar9331_1p2_baseband_postamble); 91 92 /* radio */ 93 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 94 ar9331_1p2_radio_core); 95 96 /* soc */ 97 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 98 ar9331_1p2_soc_preamble); 99 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 100 ar9331_1p2_soc_postamble); 101 102 /* rx/tx gain */ 103 INIT_INI_ARRAY(&ah->iniModesRxGain, 104 ar9331_common_rx_gain_1p2); 105 INIT_INI_ARRAY(&ah->iniModesTxGain, 106 ar9331_modes_lowest_ob_db_tx_gain_1p2); 107 108 /* Japan 2484 Mhz CCK */ 109 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 110 ar9331_1p2_baseband_core_txfir_coeff_japan_2484); 111 112 /* additional clock settings */ 113 if (ah->is_clk_25mhz) 114 INIT_INI_ARRAY(&ah->iniAdditional, 115 ar9331_1p2_xtal_25M); 116 else 117 INIT_INI_ARRAY(&ah->iniAdditional, 118 ar9331_1p2_xtal_40M); 119 } else if (AR_SREV_9340(ah)) { 120 /* mac */ 121 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 122 ar9340_1p0_mac_core); 123 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 124 ar9340_1p0_mac_postamble); 125 126 /* bb */ 127 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 128 ar9340_1p0_baseband_core); 129 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 130 ar9340_1p0_baseband_postamble); 131 132 /* radio */ 133 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 134 ar9340_1p0_radio_core); 135 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 136 ar9340_1p0_radio_postamble); 137 138 /* soc */ 139 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 140 ar9340_1p0_soc_preamble); 141 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 142 ar9340_1p0_soc_postamble); 143 144 /* rx/tx gain */ 145 INIT_INI_ARRAY(&ah->iniModesRxGain, 146 ar9340Common_wo_xlna_rx_gain_table_1p0); 147 INIT_INI_ARRAY(&ah->iniModesTxGain, 148 ar9340Modes_high_ob_db_tx_gain_table_1p0); 149 150 INIT_INI_ARRAY(&ah->iniModesFastClock, 151 ar9340Modes_fast_clock_1p0); 152 153 if (!ah->is_clk_25mhz) 154 INIT_INI_ARRAY(&ah->iniAdditional, 155 ar9340_1p0_radio_core_40M); 156 } else if (AR_SREV_9485_11(ah)) { 157 /* mac */ 158 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 159 ar9485_1_1_mac_core); 160 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 161 ar9485_1_1_mac_postamble); 162 163 /* bb */ 164 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); 165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 166 ar9485_1_1_baseband_core); 167 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 168 ar9485_1_1_baseband_postamble); 169 170 /* radio */ 171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 172 ar9485_1_1_radio_core); 173 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 174 ar9485_1_1_radio_postamble); 175 176 /* soc */ 177 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 178 ar9485_1_1_soc_preamble); 179 180 /* rx/tx gain */ 181 INIT_INI_ARRAY(&ah->iniModesRxGain, 182 ar9485Common_wo_xlna_rx_gain_1_1); 183 INIT_INI_ARRAY(&ah->iniModesTxGain, 184 ar9485_modes_lowest_ob_db_tx_gain_1_1); 185 186 /* Japan 2484 Mhz CCK */ 187 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 188 ar9485_1_1_baseband_core_txfir_coeff_japan_2484); 189 190 /* Load PCIE SERDES settings from INI */ 191 192 /* Awake Setting */ 193 194 INIT_INI_ARRAY(&ah->iniPcieSerdes, 195 ar9485_1_1_pcie_phy_clkreq_disable_L1); 196 197 /* Sleep Setting */ 198 199 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 200 ar9485_1_1_pcie_phy_clkreq_disable_L1); 201 } else if (AR_SREV_9462_21(ah)) { 202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 203 ar9462_2p1_mac_core); 204 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 205 ar9462_2p1_mac_postamble); 206 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 207 ar9462_2p1_baseband_core); 208 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 209 ar9462_2p1_baseband_postamble); 210 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 211 ar9462_2p1_radio_core); 212 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 213 ar9462_2p1_radio_postamble); 214 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 215 ar9462_2p1_radio_postamble_sys2ant); 216 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 217 ar9462_2p1_soc_preamble); 218 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 219 ar9462_2p1_soc_postamble); 220 INIT_INI_ARRAY(&ah->iniModesRxGain, 221 ar9462_2p1_common_rx_gain); 222 INIT_INI_ARRAY(&ah->iniModesFastClock, 223 ar9462_2p1_modes_fast_clock); 224 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 225 ar9462_2p1_baseband_core_txfir_coeff_japan_2484); 226 } else if (AR_SREV_9462_20(ah)) { 227 228 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); 229 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 230 ar9462_2p0_mac_postamble); 231 232 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 233 ar9462_2p0_baseband_core); 234 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 235 ar9462_2p0_baseband_postamble); 236 237 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 238 ar9462_2p0_radio_core); 239 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 240 ar9462_2p0_radio_postamble); 241 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 242 ar9462_2p0_radio_postamble_sys2ant); 243 244 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 245 ar9462_2p0_soc_preamble); 246 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 247 ar9462_2p0_soc_postamble); 248 249 INIT_INI_ARRAY(&ah->iniModesRxGain, 250 ar9462_common_rx_gain_table_2p0); 251 252 /* Awake -> Sleep Setting */ 253 INIT_INI_ARRAY(&ah->iniPcieSerdes, 254 ar9462_pciephy_clkreq_disable_L1_2p0); 255 /* Sleep -> Awake Setting */ 256 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 257 ar9462_pciephy_clkreq_disable_L1_2p0); 258 259 /* Fast clock modal settings */ 260 INIT_INI_ARRAY(&ah->iniModesFastClock, 261 ar9462_modes_fast_clock_2p0); 262 263 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 264 ar9462_2p0_baseband_core_txfir_coeff_japan_2484); 265 } else if (AR_SREV_9550(ah)) { 266 /* mac */ 267 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 268 ar955x_1p0_mac_core); 269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 270 ar955x_1p0_mac_postamble); 271 272 /* bb */ 273 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 274 ar955x_1p0_baseband_core); 275 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 276 ar955x_1p0_baseband_postamble); 277 278 /* radio */ 279 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 280 ar955x_1p0_radio_core); 281 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 282 ar955x_1p0_radio_postamble); 283 284 /* soc */ 285 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 286 ar955x_1p0_soc_preamble); 287 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 288 ar955x_1p0_soc_postamble); 289 290 /* rx/tx gain */ 291 INIT_INI_ARRAY(&ah->iniModesRxGain, 292 ar955x_1p0_common_wo_xlna_rx_gain_table); 293 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 294 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 295 INIT_INI_ARRAY(&ah->iniModesTxGain, 296 ar955x_1p0_modes_xpa_tx_gain_table); 297 298 /* Fast clock modal settings */ 299 INIT_INI_ARRAY(&ah->iniModesFastClock, 300 ar955x_1p0_modes_fast_clock); 301 } else if (AR_SREV_9580(ah)) { 302 /* mac */ 303 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 304 ar9580_1p0_mac_core); 305 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 306 ar9580_1p0_mac_postamble); 307 308 /* bb */ 309 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 310 ar9580_1p0_baseband_core); 311 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 312 ar9580_1p0_baseband_postamble); 313 314 /* radio */ 315 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 316 ar9580_1p0_radio_core); 317 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 318 ar9580_1p0_radio_postamble); 319 320 /* soc */ 321 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 322 ar9580_1p0_soc_preamble); 323 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 324 ar9580_1p0_soc_postamble); 325 326 /* rx/tx gain */ 327 INIT_INI_ARRAY(&ah->iniModesRxGain, 328 ar9580_1p0_rx_gain_table); 329 INIT_INI_ARRAY(&ah->iniModesTxGain, 330 ar9580_1p0_low_ob_db_tx_gain_table); 331 332 INIT_INI_ARRAY(&ah->iniModesFastClock, 333 ar9580_1p0_modes_fast_clock); 334 } else if (AR_SREV_9565(ah)) { 335 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 336 ar9565_1p0_mac_core); 337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 338 ar9565_1p0_mac_postamble); 339 340 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 341 ar9565_1p0_baseband_core); 342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 343 ar9565_1p0_baseband_postamble); 344 345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 346 ar9565_1p0_radio_core); 347 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 348 ar9565_1p0_radio_postamble); 349 350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 351 ar9565_1p0_soc_preamble); 352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 353 ar9565_1p0_soc_postamble); 354 355 INIT_INI_ARRAY(&ah->iniModesRxGain, 356 ar9565_1p0_Common_rx_gain_table); 357 INIT_INI_ARRAY(&ah->iniModesTxGain, 358 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); 359 360 INIT_INI_ARRAY(&ah->iniPcieSerdes, 361 ar9565_1p0_pciephy_clkreq_disable_L1); 362 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 363 ar9565_1p0_pciephy_clkreq_disable_L1); 364 365 INIT_INI_ARRAY(&ah->iniModesFastClock, 366 ar9565_1p0_modes_fast_clock); 367 } else { 368 /* mac */ 369 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 370 ar9300_2p2_mac_core); 371 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 372 ar9300_2p2_mac_postamble); 373 374 /* bb */ 375 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 376 ar9300_2p2_baseband_core); 377 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 378 ar9300_2p2_baseband_postamble); 379 380 /* radio */ 381 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 382 ar9300_2p2_radio_core); 383 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 384 ar9300_2p2_radio_postamble); 385 386 /* soc */ 387 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 388 ar9300_2p2_soc_preamble); 389 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 390 ar9300_2p2_soc_postamble); 391 392 /* rx/tx gain */ 393 INIT_INI_ARRAY(&ah->iniModesRxGain, 394 ar9300Common_rx_gain_table_2p2); 395 INIT_INI_ARRAY(&ah->iniModesTxGain, 396 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 397 398 /* Load PCIE SERDES settings from INI */ 399 400 /* Awake Setting */ 401 402 INIT_INI_ARRAY(&ah->iniPcieSerdes, 403 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 404 405 /* Sleep Setting */ 406 407 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 408 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 409 410 /* Fast clock modal settings */ 411 INIT_INI_ARRAY(&ah->iniModesFastClock, 412 ar9300Modes_fast_clock_2p2); 413 } 414 } 415 416 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 417 { 418 if (AR_SREV_9330_12(ah)) 419 INIT_INI_ARRAY(&ah->iniModesTxGain, 420 ar9331_modes_lowest_ob_db_tx_gain_1p2); 421 else if (AR_SREV_9330_11(ah)) 422 INIT_INI_ARRAY(&ah->iniModesTxGain, 423 ar9331_modes_lowest_ob_db_tx_gain_1p1); 424 else if (AR_SREV_9340(ah)) 425 INIT_INI_ARRAY(&ah->iniModesTxGain, 426 ar9340Modes_lowest_ob_db_tx_gain_table_1p0); 427 else if (AR_SREV_9485_11(ah)) 428 INIT_INI_ARRAY(&ah->iniModesTxGain, 429 ar9485_modes_lowest_ob_db_tx_gain_1_1); 430 else if (AR_SREV_9550(ah)) 431 INIT_INI_ARRAY(&ah->iniModesTxGain, 432 ar955x_1p0_modes_xpa_tx_gain_table); 433 else if (AR_SREV_9580(ah)) 434 INIT_INI_ARRAY(&ah->iniModesTxGain, 435 ar9580_1p0_lowest_ob_db_tx_gain_table); 436 else if (AR_SREV_9462_21(ah)) 437 INIT_INI_ARRAY(&ah->iniModesTxGain, 438 ar9462_2p1_modes_low_ob_db_tx_gain); 439 else if (AR_SREV_9462_20(ah)) 440 INIT_INI_ARRAY(&ah->iniModesTxGain, 441 ar9462_modes_low_ob_db_tx_gain_table_2p0); 442 else if (AR_SREV_9565(ah)) 443 INIT_INI_ARRAY(&ah->iniModesTxGain, 444 ar9565_1p0_modes_low_ob_db_tx_gain_table); 445 else 446 INIT_INI_ARRAY(&ah->iniModesTxGain, 447 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 448 } 449 450 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 451 { 452 if (AR_SREV_9330_12(ah)) 453 INIT_INI_ARRAY(&ah->iniModesTxGain, 454 ar9331_modes_high_ob_db_tx_gain_1p2); 455 else if (AR_SREV_9330_11(ah)) 456 INIT_INI_ARRAY(&ah->iniModesTxGain, 457 ar9331_modes_high_ob_db_tx_gain_1p1); 458 else if (AR_SREV_9340(ah)) 459 INIT_INI_ARRAY(&ah->iniModesTxGain, 460 ar9340Modes_high_ob_db_tx_gain_table_1p0); 461 else if (AR_SREV_9485_11(ah)) 462 INIT_INI_ARRAY(&ah->iniModesTxGain, 463 ar9485Modes_high_ob_db_tx_gain_1_1); 464 else if (AR_SREV_9580(ah)) 465 INIT_INI_ARRAY(&ah->iniModesTxGain, 466 ar9580_1p0_high_ob_db_tx_gain_table); 467 else if (AR_SREV_9550(ah)) 468 INIT_INI_ARRAY(&ah->iniModesTxGain, 469 ar955x_1p0_modes_no_xpa_tx_gain_table); 470 else if (AR_SREV_9462_21(ah)) 471 INIT_INI_ARRAY(&ah->iniModesTxGain, 472 ar9462_2p1_modes_high_ob_db_tx_gain); 473 else if (AR_SREV_9462_20(ah)) 474 INIT_INI_ARRAY(&ah->iniModesTxGain, 475 ar9462_modes_high_ob_db_tx_gain_table_2p0); 476 else if (AR_SREV_9565(ah)) 477 INIT_INI_ARRAY(&ah->iniModesTxGain, 478 ar9565_1p0_modes_high_ob_db_tx_gain_table); 479 else 480 INIT_INI_ARRAY(&ah->iniModesTxGain, 481 ar9300Modes_high_ob_db_tx_gain_table_2p2); 482 } 483 484 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 485 { 486 if (AR_SREV_9330_12(ah)) 487 INIT_INI_ARRAY(&ah->iniModesTxGain, 488 ar9331_modes_low_ob_db_tx_gain_1p2); 489 else if (AR_SREV_9330_11(ah)) 490 INIT_INI_ARRAY(&ah->iniModesTxGain, 491 ar9331_modes_low_ob_db_tx_gain_1p1); 492 else if (AR_SREV_9340(ah)) 493 INIT_INI_ARRAY(&ah->iniModesTxGain, 494 ar9340Modes_low_ob_db_tx_gain_table_1p0); 495 else if (AR_SREV_9485_11(ah)) 496 INIT_INI_ARRAY(&ah->iniModesTxGain, 497 ar9485Modes_low_ob_db_tx_gain_1_1); 498 else if (AR_SREV_9580(ah)) 499 INIT_INI_ARRAY(&ah->iniModesTxGain, 500 ar9580_1p0_low_ob_db_tx_gain_table); 501 else if (AR_SREV_9565(ah)) 502 INIT_INI_ARRAY(&ah->iniModesTxGain, 503 ar9565_1p0_modes_low_ob_db_tx_gain_table); 504 else 505 INIT_INI_ARRAY(&ah->iniModesTxGain, 506 ar9300Modes_low_ob_db_tx_gain_table_2p2); 507 } 508 509 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 510 { 511 if (AR_SREV_9330_12(ah)) 512 INIT_INI_ARRAY(&ah->iniModesTxGain, 513 ar9331_modes_high_power_tx_gain_1p2); 514 else if (AR_SREV_9330_11(ah)) 515 INIT_INI_ARRAY(&ah->iniModesTxGain, 516 ar9331_modes_high_power_tx_gain_1p1); 517 else if (AR_SREV_9340(ah)) 518 INIT_INI_ARRAY(&ah->iniModesTxGain, 519 ar9340Modes_high_power_tx_gain_table_1p0); 520 else if (AR_SREV_9485_11(ah)) 521 INIT_INI_ARRAY(&ah->iniModesTxGain, 522 ar9485Modes_high_power_tx_gain_1_1); 523 else if (AR_SREV_9580(ah)) 524 INIT_INI_ARRAY(&ah->iniModesTxGain, 525 ar9580_1p0_high_power_tx_gain_table); 526 else if (AR_SREV_9565(ah)) 527 INIT_INI_ARRAY(&ah->iniModesTxGain, 528 ar9565_1p0_modes_high_power_tx_gain_table); 529 else 530 INIT_INI_ARRAY(&ah->iniModesTxGain, 531 ar9300Modes_high_power_tx_gain_table_2p2); 532 } 533 534 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 535 { 536 if (AR_SREV_9340(ah)) 537 INIT_INI_ARRAY(&ah->iniModesTxGain, 538 ar9340Modes_mixed_ob_db_tx_gain_table_1p0); 539 else if (AR_SREV_9580(ah)) 540 INIT_INI_ARRAY(&ah->iniModesTxGain, 541 ar9580_1p0_mixed_ob_db_tx_gain_table); 542 else if (AR_SREV_9462_21(ah)) 543 INIT_INI_ARRAY(&ah->iniModesTxGain, 544 ar9462_2p1_modes_mix_ob_db_tx_gain); 545 else if (AR_SREV_9462_20(ah)) 546 INIT_INI_ARRAY(&ah->iniModesTxGain, 547 ar9462_modes_mix_ob_db_tx_gain_table_2p0); 548 else 549 INIT_INI_ARRAY(&ah->iniModesTxGain, 550 ar9300Modes_mixed_ob_db_tx_gain_table_2p2); 551 } 552 553 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) 554 { 555 if (AR_SREV_9485_11(ah)) 556 INIT_INI_ARRAY(&ah->iniModesTxGain, 557 ar9485Modes_green_ob_db_tx_gain_1_1); 558 else if (AR_SREV_9340(ah)) 559 INIT_INI_ARRAY(&ah->iniModesTxGain, 560 ar9340Modes_ub124_tx_gain_table_1p0); 561 else if (AR_SREV_9580(ah)) 562 INIT_INI_ARRAY(&ah->iniModesTxGain, 563 ar9580_1p0_type5_tx_gain_table); 564 else if (AR_SREV_9300_22(ah)) 565 INIT_INI_ARRAY(&ah->iniModesTxGain, 566 ar9300Modes_type5_tx_gain_table_2p2); 567 } 568 569 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) 570 { 571 if (AR_SREV_9340(ah)) 572 INIT_INI_ARRAY(&ah->iniModesTxGain, 573 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0); 574 else if (AR_SREV_9485_11(ah)) 575 INIT_INI_ARRAY(&ah->iniModesTxGain, 576 ar9485Modes_green_spur_ob_db_tx_gain_1_1); 577 else if (AR_SREV_9580(ah)) 578 INIT_INI_ARRAY(&ah->iniModesTxGain, 579 ar9580_1p0_type6_tx_gain_table); 580 } 581 582 typedef void (*ath_txgain_tab)(struct ath_hw *ah); 583 584 static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 585 { 586 static const ath_txgain_tab modes[] = { 587 ar9003_tx_gain_table_mode0, 588 ar9003_tx_gain_table_mode1, 589 ar9003_tx_gain_table_mode2, 590 ar9003_tx_gain_table_mode3, 591 ar9003_tx_gain_table_mode4, 592 ar9003_tx_gain_table_mode5, 593 ar9003_tx_gain_table_mode6, 594 }; 595 int idx = ar9003_hw_get_tx_gain_idx(ah); 596 597 if (idx >= ARRAY_SIZE(modes)) 598 idx = 0; 599 600 modes[idx](ah); 601 } 602 603 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 604 { 605 if (AR_SREV_9330_12(ah)) 606 INIT_INI_ARRAY(&ah->iniModesRxGain, 607 ar9331_common_rx_gain_1p2); 608 else if (AR_SREV_9330_11(ah)) 609 INIT_INI_ARRAY(&ah->iniModesRxGain, 610 ar9331_common_rx_gain_1p1); 611 else if (AR_SREV_9340(ah)) 612 INIT_INI_ARRAY(&ah->iniModesRxGain, 613 ar9340Common_rx_gain_table_1p0); 614 else if (AR_SREV_9485_11(ah)) 615 INIT_INI_ARRAY(&ah->iniModesRxGain, 616 ar9485_common_rx_gain_1_1); 617 else if (AR_SREV_9550(ah)) { 618 INIT_INI_ARRAY(&ah->iniModesRxGain, 619 ar955x_1p0_common_rx_gain_table); 620 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 621 ar955x_1p0_common_rx_gain_bounds); 622 } else if (AR_SREV_9580(ah)) 623 INIT_INI_ARRAY(&ah->iniModesRxGain, 624 ar9580_1p0_rx_gain_table); 625 else if (AR_SREV_9462_21(ah)) 626 INIT_INI_ARRAY(&ah->iniModesRxGain, 627 ar9462_2p1_common_rx_gain); 628 else if (AR_SREV_9462_20(ah)) 629 INIT_INI_ARRAY(&ah->iniModesRxGain, 630 ar9462_common_rx_gain_table_2p0); 631 else 632 INIT_INI_ARRAY(&ah->iniModesRxGain, 633 ar9300Common_rx_gain_table_2p2); 634 } 635 636 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 637 { 638 if (AR_SREV_9330_12(ah)) 639 INIT_INI_ARRAY(&ah->iniModesRxGain, 640 ar9331_common_wo_xlna_rx_gain_1p2); 641 else if (AR_SREV_9330_11(ah)) 642 INIT_INI_ARRAY(&ah->iniModesRxGain, 643 ar9331_common_wo_xlna_rx_gain_1p1); 644 else if (AR_SREV_9340(ah)) 645 INIT_INI_ARRAY(&ah->iniModesRxGain, 646 ar9340Common_wo_xlna_rx_gain_table_1p0); 647 else if (AR_SREV_9485_11(ah)) 648 INIT_INI_ARRAY(&ah->iniModesRxGain, 649 ar9485Common_wo_xlna_rx_gain_1_1); 650 else if (AR_SREV_9462_21(ah)) 651 INIT_INI_ARRAY(&ah->iniModesRxGain, 652 ar9462_2p1_common_wo_xlna_rx_gain); 653 else if (AR_SREV_9462_20(ah)) 654 INIT_INI_ARRAY(&ah->iniModesRxGain, 655 ar9462_common_wo_xlna_rx_gain_table_2p0); 656 else if (AR_SREV_9550(ah)) { 657 INIT_INI_ARRAY(&ah->iniModesRxGain, 658 ar955x_1p0_common_wo_xlna_rx_gain_table); 659 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 660 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 661 } else if (AR_SREV_9580(ah)) 662 INIT_INI_ARRAY(&ah->iniModesRxGain, 663 ar9580_1p0_wo_xlna_rx_gain_table); 664 else if (AR_SREV_9565(ah)) 665 INIT_INI_ARRAY(&ah->iniModesRxGain, 666 ar9565_1p0_common_wo_xlna_rx_gain_table); 667 else 668 INIT_INI_ARRAY(&ah->iniModesRxGain, 669 ar9300Common_wo_xlna_rx_gain_table_2p2); 670 } 671 672 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 673 { 674 if (AR_SREV_9462_21(ah)) { 675 INIT_INI_ARRAY(&ah->iniModesRxGain, 676 ar9462_2p1_common_mixed_rx_gain); 677 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 678 ar9462_2p1_baseband_core_mix_rxgain); 679 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 680 ar9462_2p1_baseband_postamble_mix_rxgain); 681 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 682 ar9462_2p1_baseband_postamble_5g_xlna); 683 } else if (AR_SREV_9462_20(ah)) { 684 INIT_INI_ARRAY(&ah->iniModesRxGain, 685 ar9462_common_mixed_rx_gain_table_2p0); 686 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 687 ar9462_2p0_baseband_core_mix_rxgain); 688 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 689 ar9462_2p0_baseband_postamble_mix_rxgain); 690 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 691 ar9462_2p0_baseband_postamble_5g_xlna); 692 } 693 } 694 695 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) 696 { 697 if (AR_SREV_9462_21(ah)) { 698 INIT_INI_ARRAY(&ah->iniModesRxGain, 699 ar9462_2p1_common_5g_xlna_only_rx_gain); 700 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 701 ar9462_2p1_baseband_postamble_5g_xlna); 702 } else if (AR_SREV_9462_20(ah)) { 703 INIT_INI_ARRAY(&ah->iniModesRxGain, 704 ar9462_2p0_5g_xlna_only_rxgain); 705 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 706 ar9462_2p0_baseband_postamble_5g_xlna); 707 } 708 } 709 710 static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 711 { 712 switch (ar9003_hw_get_rx_gain_idx(ah)) { 713 case 0: 714 default: 715 ar9003_rx_gain_table_mode0(ah); 716 break; 717 case 1: 718 ar9003_rx_gain_table_mode1(ah); 719 break; 720 case 2: 721 ar9003_rx_gain_table_mode2(ah); 722 break; 723 case 3: 724 ar9003_rx_gain_table_mode3(ah); 725 break; 726 } 727 } 728 729 /* set gain table pointers according to values read from the eeprom */ 730 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) 731 { 732 ar9003_tx_gain_table_apply(ah); 733 ar9003_rx_gain_table_apply(ah); 734 } 735 736 /* 737 * Helper for ASPM support. 738 * 739 * Disable PLL when in L0s as well as receiver clock when in L1. 740 * This power saving option must be enabled through the SerDes. 741 * 742 * Programming the SerDes must go through the same 288 bit serial shift 743 * register as the other analog registers. Hence the 9 writes. 744 */ 745 static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 746 bool power_off) 747 { 748 /* Nothing to do on restore for 11N */ 749 if (!power_off /* !restore */) { 750 /* set bit 19 to allow forcing of pcie core into L1 state */ 751 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 752 753 /* Several PCIe massages to ensure proper behaviour */ 754 if (ah->config.pcie_waen) 755 REG_WRITE(ah, AR_WA, ah->config.pcie_waen); 756 else 757 REG_WRITE(ah, AR_WA, ah->WARegVal); 758 } 759 760 /* 761 * Configire PCIE after Ini init. SERDES values now come from ini file 762 * This enables PCIe low power mode. 763 */ 764 if (ah->config.pcieSerDesWrite) { 765 unsigned int i; 766 struct ar5416IniArray *array; 767 768 array = power_off ? &ah->iniPcieSerdes : 769 &ah->iniPcieSerdesLowPower; 770 771 for (i = 0; i < array->ia_rows; i++) { 772 REG_WRITE(ah, 773 INI_RA(array, i, 0), 774 INI_RA(array, i, 1)); 775 } 776 } 777 } 778 779 /* Sets up the AR9003 hardware familiy callbacks */ 780 void ar9003_hw_attach_ops(struct ath_hw *ah) 781 { 782 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 783 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 784 785 ar9003_hw_init_mode_regs(ah); 786 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 787 788 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 789 790 ar9003_hw_attach_phy_ops(ah); 791 ar9003_hw_attach_calib_ops(ah); 792 ar9003_hw_attach_mac_ops(ah); 793 } 794