1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_2p2_initvals.h" 20 #include "ar9485_initvals.h" 21 #include "ar9340_initvals.h" 22 #include "ar9330_1p1_initvals.h" 23 #include "ar9330_1p2_initvals.h" 24 #include "ar955x_1p0_initvals.h" 25 #include "ar9580_1p0_initvals.h" 26 #include "ar9462_2p0_initvals.h" 27 #include "ar9462_2p1_initvals.h" 28 #include "ar9565_1p0_initvals.h" 29 30 /* General hardware code for the AR9003 hadware family */ 31 32 /* 33 * The AR9003 family uses a new INI format (pre, core, post 34 * arrays per subsystem). This provides support for the 35 * AR9003 2.2 chipsets. 36 */ 37 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 38 { 39 if (AR_SREV_9330_11(ah)) { 40 /* mac */ 41 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 42 ar9331_1p1_mac_core); 43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 44 ar9331_1p1_mac_postamble); 45 46 /* bb */ 47 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 48 ar9331_1p1_baseband_core); 49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 50 ar9331_1p1_baseband_postamble); 51 52 /* radio */ 53 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 54 ar9331_1p1_radio_core); 55 56 /* soc */ 57 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 58 ar9331_1p1_soc_preamble); 59 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 60 ar9331_1p1_soc_postamble); 61 62 /* rx/tx gain */ 63 INIT_INI_ARRAY(&ah->iniModesRxGain, 64 ar9331_common_rx_gain_1p1); 65 INIT_INI_ARRAY(&ah->iniModesTxGain, 66 ar9331_modes_lowest_ob_db_tx_gain_1p1); 67 68 /* Japan 2484 Mhz CCK */ 69 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 70 ar9331_1p1_baseband_core_txfir_coeff_japan_2484); 71 72 /* additional clock settings */ 73 if (ah->is_clk_25mhz) 74 INIT_INI_ARRAY(&ah->iniAdditional, 75 ar9331_1p1_xtal_25M); 76 else 77 INIT_INI_ARRAY(&ah->iniAdditional, 78 ar9331_1p1_xtal_40M); 79 } else if (AR_SREV_9330_12(ah)) { 80 /* mac */ 81 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 82 ar9331_1p2_mac_core); 83 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 84 ar9331_1p2_mac_postamble); 85 86 /* bb */ 87 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 88 ar9331_1p2_baseband_core); 89 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 90 ar9331_1p2_baseband_postamble); 91 92 /* radio */ 93 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 94 ar9331_1p2_radio_core); 95 96 /* soc */ 97 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 98 ar9331_1p2_soc_preamble); 99 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 100 ar9331_1p2_soc_postamble); 101 102 /* rx/tx gain */ 103 INIT_INI_ARRAY(&ah->iniModesRxGain, 104 ar9331_common_rx_gain_1p2); 105 INIT_INI_ARRAY(&ah->iniModesTxGain, 106 ar9331_modes_lowest_ob_db_tx_gain_1p2); 107 108 /* Japan 2484 Mhz CCK */ 109 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 110 ar9331_1p2_baseband_core_txfir_coeff_japan_2484); 111 112 /* additional clock settings */ 113 if (ah->is_clk_25mhz) 114 INIT_INI_ARRAY(&ah->iniAdditional, 115 ar9331_1p2_xtal_25M); 116 else 117 INIT_INI_ARRAY(&ah->iniAdditional, 118 ar9331_1p2_xtal_40M); 119 } else if (AR_SREV_9340(ah)) { 120 /* mac */ 121 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 122 ar9340_1p0_mac_core); 123 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 124 ar9340_1p0_mac_postamble); 125 126 /* bb */ 127 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 128 ar9340_1p0_baseband_core); 129 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 130 ar9340_1p0_baseband_postamble); 131 132 /* radio */ 133 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 134 ar9340_1p0_radio_core); 135 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 136 ar9340_1p0_radio_postamble); 137 138 /* soc */ 139 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 140 ar9340_1p0_soc_preamble); 141 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 142 ar9340_1p0_soc_postamble); 143 144 /* rx/tx gain */ 145 INIT_INI_ARRAY(&ah->iniModesRxGain, 146 ar9340Common_wo_xlna_rx_gain_table_1p0); 147 INIT_INI_ARRAY(&ah->iniModesTxGain, 148 ar9340Modes_high_ob_db_tx_gain_table_1p0); 149 150 INIT_INI_ARRAY(&ah->iniModesFastClock, 151 ar9340Modes_fast_clock_1p0); 152 153 if (!ah->is_clk_25mhz) 154 INIT_INI_ARRAY(&ah->iniAdditional, 155 ar9340_1p0_radio_core_40M); 156 } else if (AR_SREV_9485_11_OR_LATER(ah)) { 157 /* mac */ 158 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 159 ar9485_1_1_mac_core); 160 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 161 ar9485_1_1_mac_postamble); 162 163 /* bb */ 164 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); 165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 166 ar9485_1_1_baseband_core); 167 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 168 ar9485_1_1_baseband_postamble); 169 170 /* radio */ 171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 172 ar9485_1_1_radio_core); 173 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 174 ar9485_1_1_radio_postamble); 175 176 /* soc */ 177 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 178 ar9485_1_1_soc_preamble); 179 180 /* rx/tx gain */ 181 INIT_INI_ARRAY(&ah->iniModesRxGain, 182 ar9485Common_wo_xlna_rx_gain_1_1); 183 INIT_INI_ARRAY(&ah->iniModesTxGain, 184 ar9485_modes_lowest_ob_db_tx_gain_1_1); 185 186 /* Japan 2484 Mhz CCK */ 187 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 188 ar9485_1_1_baseband_core_txfir_coeff_japan_2484); 189 190 if (ah->config.no_pll_pwrsave) { 191 INIT_INI_ARRAY(&ah->iniPcieSerdes, 192 ar9485_1_1_pcie_phy_clkreq_disable_L1); 193 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 194 ar9485_1_1_pcie_phy_clkreq_disable_L1); 195 } else { 196 INIT_INI_ARRAY(&ah->iniPcieSerdes, 197 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); 198 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 199 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); 200 } 201 } else if (AR_SREV_9462_21(ah)) { 202 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 203 ar9462_2p1_mac_core); 204 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 205 ar9462_2p1_mac_postamble); 206 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 207 ar9462_2p1_baseband_core); 208 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 209 ar9462_2p1_baseband_postamble); 210 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 211 ar9462_2p1_radio_core); 212 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 213 ar9462_2p1_radio_postamble); 214 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 215 ar9462_2p1_radio_postamble_sys2ant); 216 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 217 ar9462_2p1_soc_preamble); 218 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 219 ar9462_2p1_soc_postamble); 220 INIT_INI_ARRAY(&ah->iniModesRxGain, 221 ar9462_2p1_common_rx_gain); 222 INIT_INI_ARRAY(&ah->iniModesFastClock, 223 ar9462_2p1_modes_fast_clock); 224 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 225 ar9462_2p1_baseband_core_txfir_coeff_japan_2484); 226 } else if (AR_SREV_9462_20(ah)) { 227 228 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); 229 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 230 ar9462_2p0_mac_postamble); 231 232 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 233 ar9462_2p0_baseband_core); 234 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 235 ar9462_2p0_baseband_postamble); 236 237 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 238 ar9462_2p0_radio_core); 239 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 240 ar9462_2p0_radio_postamble); 241 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 242 ar9462_2p0_radio_postamble_sys2ant); 243 244 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 245 ar9462_2p0_soc_preamble); 246 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 247 ar9462_2p0_soc_postamble); 248 249 INIT_INI_ARRAY(&ah->iniModesRxGain, 250 ar9462_common_rx_gain_table_2p0); 251 252 /* Awake -> Sleep Setting */ 253 INIT_INI_ARRAY(&ah->iniPcieSerdes, 254 ar9462_pciephy_clkreq_disable_L1_2p0); 255 /* Sleep -> Awake Setting */ 256 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 257 ar9462_pciephy_clkreq_disable_L1_2p0); 258 259 /* Fast clock modal settings */ 260 INIT_INI_ARRAY(&ah->iniModesFastClock, 261 ar9462_modes_fast_clock_2p0); 262 263 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 264 ar9462_2p0_baseband_core_txfir_coeff_japan_2484); 265 } else if (AR_SREV_9550(ah)) { 266 /* mac */ 267 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 268 ar955x_1p0_mac_core); 269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 270 ar955x_1p0_mac_postamble); 271 272 /* bb */ 273 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 274 ar955x_1p0_baseband_core); 275 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 276 ar955x_1p0_baseband_postamble); 277 278 /* radio */ 279 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 280 ar955x_1p0_radio_core); 281 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 282 ar955x_1p0_radio_postamble); 283 284 /* soc */ 285 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 286 ar955x_1p0_soc_preamble); 287 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 288 ar955x_1p0_soc_postamble); 289 290 /* rx/tx gain */ 291 INIT_INI_ARRAY(&ah->iniModesRxGain, 292 ar955x_1p0_common_wo_xlna_rx_gain_table); 293 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 294 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 295 INIT_INI_ARRAY(&ah->iniModesTxGain, 296 ar955x_1p0_modes_xpa_tx_gain_table); 297 298 /* Fast clock modal settings */ 299 INIT_INI_ARRAY(&ah->iniModesFastClock, 300 ar955x_1p0_modes_fast_clock); 301 } else if (AR_SREV_9580(ah)) { 302 /* mac */ 303 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 304 ar9580_1p0_mac_core); 305 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 306 ar9580_1p0_mac_postamble); 307 308 /* bb */ 309 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 310 ar9580_1p0_baseband_core); 311 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 312 ar9580_1p0_baseband_postamble); 313 314 /* radio */ 315 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 316 ar9580_1p0_radio_core); 317 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 318 ar9580_1p0_radio_postamble); 319 320 /* soc */ 321 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 322 ar9580_1p0_soc_preamble); 323 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 324 ar9580_1p0_soc_postamble); 325 326 /* rx/tx gain */ 327 INIT_INI_ARRAY(&ah->iniModesRxGain, 328 ar9580_1p0_rx_gain_table); 329 INIT_INI_ARRAY(&ah->iniModesTxGain, 330 ar9580_1p0_low_ob_db_tx_gain_table); 331 332 INIT_INI_ARRAY(&ah->iniModesFastClock, 333 ar9580_1p0_modes_fast_clock); 334 } else if (AR_SREV_9565(ah)) { 335 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 336 ar9565_1p0_mac_core); 337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 338 ar9565_1p0_mac_postamble); 339 340 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 341 ar9565_1p0_baseband_core); 342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 343 ar9565_1p0_baseband_postamble); 344 345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 346 ar9565_1p0_radio_core); 347 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 348 ar9565_1p0_radio_postamble); 349 350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 351 ar9565_1p0_soc_preamble); 352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 353 ar9565_1p0_soc_postamble); 354 355 INIT_INI_ARRAY(&ah->iniModesRxGain, 356 ar9565_1p0_Common_rx_gain_table); 357 INIT_INI_ARRAY(&ah->iniModesTxGain, 358 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); 359 360 INIT_INI_ARRAY(&ah->iniPcieSerdes, 361 ar9565_1p0_pciephy_clkreq_disable_L1); 362 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 363 ar9565_1p0_pciephy_clkreq_disable_L1); 364 365 INIT_INI_ARRAY(&ah->iniModesFastClock, 366 ar9565_1p0_modes_fast_clock); 367 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 368 ar9565_1p0_baseband_core_txfir_coeff_japan_2484); 369 } else { 370 /* mac */ 371 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 372 ar9300_2p2_mac_core); 373 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 374 ar9300_2p2_mac_postamble); 375 376 /* bb */ 377 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 378 ar9300_2p2_baseband_core); 379 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 380 ar9300_2p2_baseband_postamble); 381 382 /* radio */ 383 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 384 ar9300_2p2_radio_core); 385 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 386 ar9300_2p2_radio_postamble); 387 388 /* soc */ 389 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 390 ar9300_2p2_soc_preamble); 391 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 392 ar9300_2p2_soc_postamble); 393 394 /* rx/tx gain */ 395 INIT_INI_ARRAY(&ah->iniModesRxGain, 396 ar9300Common_rx_gain_table_2p2); 397 INIT_INI_ARRAY(&ah->iniModesTxGain, 398 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 399 400 /* Load PCIE SERDES settings from INI */ 401 402 /* Awake Setting */ 403 404 INIT_INI_ARRAY(&ah->iniPcieSerdes, 405 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 406 407 /* Sleep Setting */ 408 409 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 410 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 411 412 /* Fast clock modal settings */ 413 INIT_INI_ARRAY(&ah->iniModesFastClock, 414 ar9300Modes_fast_clock_2p2); 415 } 416 } 417 418 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 419 { 420 if (AR_SREV_9330_12(ah)) 421 INIT_INI_ARRAY(&ah->iniModesTxGain, 422 ar9331_modes_lowest_ob_db_tx_gain_1p2); 423 else if (AR_SREV_9330_11(ah)) 424 INIT_INI_ARRAY(&ah->iniModesTxGain, 425 ar9331_modes_lowest_ob_db_tx_gain_1p1); 426 else if (AR_SREV_9340(ah)) 427 INIT_INI_ARRAY(&ah->iniModesTxGain, 428 ar9340Modes_lowest_ob_db_tx_gain_table_1p0); 429 else if (AR_SREV_9485_11_OR_LATER(ah)) 430 INIT_INI_ARRAY(&ah->iniModesTxGain, 431 ar9485_modes_lowest_ob_db_tx_gain_1_1); 432 else if (AR_SREV_9550(ah)) 433 INIT_INI_ARRAY(&ah->iniModesTxGain, 434 ar955x_1p0_modes_xpa_tx_gain_table); 435 else if (AR_SREV_9580(ah)) 436 INIT_INI_ARRAY(&ah->iniModesTxGain, 437 ar9580_1p0_lowest_ob_db_tx_gain_table); 438 else if (AR_SREV_9462_21(ah)) 439 INIT_INI_ARRAY(&ah->iniModesTxGain, 440 ar9462_2p1_modes_low_ob_db_tx_gain); 441 else if (AR_SREV_9462_20(ah)) 442 INIT_INI_ARRAY(&ah->iniModesTxGain, 443 ar9462_modes_low_ob_db_tx_gain_table_2p0); 444 else if (AR_SREV_9565(ah)) 445 INIT_INI_ARRAY(&ah->iniModesTxGain, 446 ar9565_1p0_modes_low_ob_db_tx_gain_table); 447 else 448 INIT_INI_ARRAY(&ah->iniModesTxGain, 449 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 450 } 451 452 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 453 { 454 if (AR_SREV_9330_12(ah)) 455 INIT_INI_ARRAY(&ah->iniModesTxGain, 456 ar9331_modes_high_ob_db_tx_gain_1p2); 457 else if (AR_SREV_9330_11(ah)) 458 INIT_INI_ARRAY(&ah->iniModesTxGain, 459 ar9331_modes_high_ob_db_tx_gain_1p1); 460 else if (AR_SREV_9340(ah)) 461 INIT_INI_ARRAY(&ah->iniModesTxGain, 462 ar9340Modes_high_ob_db_tx_gain_table_1p0); 463 else if (AR_SREV_9485_11_OR_LATER(ah)) 464 INIT_INI_ARRAY(&ah->iniModesTxGain, 465 ar9485Modes_high_ob_db_tx_gain_1_1); 466 else if (AR_SREV_9580(ah)) 467 INIT_INI_ARRAY(&ah->iniModesTxGain, 468 ar9580_1p0_high_ob_db_tx_gain_table); 469 else if (AR_SREV_9550(ah)) 470 INIT_INI_ARRAY(&ah->iniModesTxGain, 471 ar955x_1p0_modes_no_xpa_tx_gain_table); 472 else if (AR_SREV_9462_21(ah)) 473 INIT_INI_ARRAY(&ah->iniModesTxGain, 474 ar9462_2p1_modes_high_ob_db_tx_gain); 475 else if (AR_SREV_9462_20(ah)) 476 INIT_INI_ARRAY(&ah->iniModesTxGain, 477 ar9462_modes_high_ob_db_tx_gain_table_2p0); 478 else if (AR_SREV_9565(ah)) 479 INIT_INI_ARRAY(&ah->iniModesTxGain, 480 ar9565_1p0_modes_high_ob_db_tx_gain_table); 481 else 482 INIT_INI_ARRAY(&ah->iniModesTxGain, 483 ar9300Modes_high_ob_db_tx_gain_table_2p2); 484 } 485 486 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 487 { 488 if (AR_SREV_9330_12(ah)) 489 INIT_INI_ARRAY(&ah->iniModesTxGain, 490 ar9331_modes_low_ob_db_tx_gain_1p2); 491 else if (AR_SREV_9330_11(ah)) 492 INIT_INI_ARRAY(&ah->iniModesTxGain, 493 ar9331_modes_low_ob_db_tx_gain_1p1); 494 else if (AR_SREV_9340(ah)) 495 INIT_INI_ARRAY(&ah->iniModesTxGain, 496 ar9340Modes_low_ob_db_tx_gain_table_1p0); 497 else if (AR_SREV_9485_11_OR_LATER(ah)) 498 INIT_INI_ARRAY(&ah->iniModesTxGain, 499 ar9485Modes_low_ob_db_tx_gain_1_1); 500 else if (AR_SREV_9580(ah)) 501 INIT_INI_ARRAY(&ah->iniModesTxGain, 502 ar9580_1p0_low_ob_db_tx_gain_table); 503 else if (AR_SREV_9565(ah)) 504 INIT_INI_ARRAY(&ah->iniModesTxGain, 505 ar9565_1p0_modes_low_ob_db_tx_gain_table); 506 else 507 INIT_INI_ARRAY(&ah->iniModesTxGain, 508 ar9300Modes_low_ob_db_tx_gain_table_2p2); 509 } 510 511 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 512 { 513 if (AR_SREV_9330_12(ah)) 514 INIT_INI_ARRAY(&ah->iniModesTxGain, 515 ar9331_modes_high_power_tx_gain_1p2); 516 else if (AR_SREV_9330_11(ah)) 517 INIT_INI_ARRAY(&ah->iniModesTxGain, 518 ar9331_modes_high_power_tx_gain_1p1); 519 else if (AR_SREV_9340(ah)) 520 INIT_INI_ARRAY(&ah->iniModesTxGain, 521 ar9340Modes_high_power_tx_gain_table_1p0); 522 else if (AR_SREV_9485_11_OR_LATER(ah)) 523 INIT_INI_ARRAY(&ah->iniModesTxGain, 524 ar9485Modes_high_power_tx_gain_1_1); 525 else if (AR_SREV_9580(ah)) 526 INIT_INI_ARRAY(&ah->iniModesTxGain, 527 ar9580_1p0_high_power_tx_gain_table); 528 else if (AR_SREV_9565(ah)) 529 INIT_INI_ARRAY(&ah->iniModesTxGain, 530 ar9565_1p0_modes_high_power_tx_gain_table); 531 else 532 INIT_INI_ARRAY(&ah->iniModesTxGain, 533 ar9300Modes_high_power_tx_gain_table_2p2); 534 } 535 536 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 537 { 538 if (AR_SREV_9340(ah)) 539 INIT_INI_ARRAY(&ah->iniModesTxGain, 540 ar9340Modes_mixed_ob_db_tx_gain_table_1p0); 541 else if (AR_SREV_9580(ah)) 542 INIT_INI_ARRAY(&ah->iniModesTxGain, 543 ar9580_1p0_mixed_ob_db_tx_gain_table); 544 else if (AR_SREV_9462_21(ah)) 545 INIT_INI_ARRAY(&ah->iniModesTxGain, 546 ar9462_2p1_modes_mix_ob_db_tx_gain); 547 else if (AR_SREV_9462_20(ah)) 548 INIT_INI_ARRAY(&ah->iniModesTxGain, 549 ar9462_modes_mix_ob_db_tx_gain_table_2p0); 550 else 551 INIT_INI_ARRAY(&ah->iniModesTxGain, 552 ar9300Modes_mixed_ob_db_tx_gain_table_2p2); 553 } 554 555 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) 556 { 557 if (AR_SREV_9485_11_OR_LATER(ah)) 558 INIT_INI_ARRAY(&ah->iniModesTxGain, 559 ar9485Modes_green_ob_db_tx_gain_1_1); 560 else if (AR_SREV_9340(ah)) 561 INIT_INI_ARRAY(&ah->iniModesTxGain, 562 ar9340Modes_ub124_tx_gain_table_1p0); 563 else if (AR_SREV_9580(ah)) 564 INIT_INI_ARRAY(&ah->iniModesTxGain, 565 ar9580_1p0_type5_tx_gain_table); 566 else if (AR_SREV_9300_22(ah)) 567 INIT_INI_ARRAY(&ah->iniModesTxGain, 568 ar9300Modes_type5_tx_gain_table_2p2); 569 } 570 571 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) 572 { 573 if (AR_SREV_9340(ah)) 574 INIT_INI_ARRAY(&ah->iniModesTxGain, 575 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0); 576 else if (AR_SREV_9485_11_OR_LATER(ah)) 577 INIT_INI_ARRAY(&ah->iniModesTxGain, 578 ar9485Modes_green_spur_ob_db_tx_gain_1_1); 579 else if (AR_SREV_9580(ah)) 580 INIT_INI_ARRAY(&ah->iniModesTxGain, 581 ar9580_1p0_type6_tx_gain_table); 582 } 583 584 typedef void (*ath_txgain_tab)(struct ath_hw *ah); 585 586 static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 587 { 588 static const ath_txgain_tab modes[] = { 589 ar9003_tx_gain_table_mode0, 590 ar9003_tx_gain_table_mode1, 591 ar9003_tx_gain_table_mode2, 592 ar9003_tx_gain_table_mode3, 593 ar9003_tx_gain_table_mode4, 594 ar9003_tx_gain_table_mode5, 595 ar9003_tx_gain_table_mode6, 596 }; 597 int idx = ar9003_hw_get_tx_gain_idx(ah); 598 599 if (idx >= ARRAY_SIZE(modes)) 600 idx = 0; 601 602 modes[idx](ah); 603 } 604 605 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 606 { 607 if (AR_SREV_9330_12(ah)) 608 INIT_INI_ARRAY(&ah->iniModesRxGain, 609 ar9331_common_rx_gain_1p2); 610 else if (AR_SREV_9330_11(ah)) 611 INIT_INI_ARRAY(&ah->iniModesRxGain, 612 ar9331_common_rx_gain_1p1); 613 else if (AR_SREV_9340(ah)) 614 INIT_INI_ARRAY(&ah->iniModesRxGain, 615 ar9340Common_rx_gain_table_1p0); 616 else if (AR_SREV_9485_11_OR_LATER(ah)) 617 INIT_INI_ARRAY(&ah->iniModesRxGain, 618 ar9485_common_rx_gain_1_1); 619 else if (AR_SREV_9550(ah)) { 620 INIT_INI_ARRAY(&ah->iniModesRxGain, 621 ar955x_1p0_common_rx_gain_table); 622 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 623 ar955x_1p0_common_rx_gain_bounds); 624 } else if (AR_SREV_9580(ah)) 625 INIT_INI_ARRAY(&ah->iniModesRxGain, 626 ar9580_1p0_rx_gain_table); 627 else if (AR_SREV_9462_21(ah)) 628 INIT_INI_ARRAY(&ah->iniModesRxGain, 629 ar9462_2p1_common_rx_gain); 630 else if (AR_SREV_9462_20(ah)) 631 INIT_INI_ARRAY(&ah->iniModesRxGain, 632 ar9462_common_rx_gain_table_2p0); 633 else if (AR_SREV_9565(ah)) 634 INIT_INI_ARRAY(&ah->iniModesRxGain, 635 ar9565_1p0_Common_rx_gain_table); 636 else 637 INIT_INI_ARRAY(&ah->iniModesRxGain, 638 ar9300Common_rx_gain_table_2p2); 639 } 640 641 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 642 { 643 if (AR_SREV_9330_12(ah)) 644 INIT_INI_ARRAY(&ah->iniModesRxGain, 645 ar9331_common_wo_xlna_rx_gain_1p2); 646 else if (AR_SREV_9330_11(ah)) 647 INIT_INI_ARRAY(&ah->iniModesRxGain, 648 ar9331_common_wo_xlna_rx_gain_1p1); 649 else if (AR_SREV_9340(ah)) 650 INIT_INI_ARRAY(&ah->iniModesRxGain, 651 ar9340Common_wo_xlna_rx_gain_table_1p0); 652 else if (AR_SREV_9485_11_OR_LATER(ah)) 653 INIT_INI_ARRAY(&ah->iniModesRxGain, 654 ar9485Common_wo_xlna_rx_gain_1_1); 655 else if (AR_SREV_9462_21(ah)) 656 INIT_INI_ARRAY(&ah->iniModesRxGain, 657 ar9462_2p1_common_wo_xlna_rx_gain); 658 else if (AR_SREV_9462_20(ah)) 659 INIT_INI_ARRAY(&ah->iniModesRxGain, 660 ar9462_common_wo_xlna_rx_gain_table_2p0); 661 else if (AR_SREV_9550(ah)) { 662 INIT_INI_ARRAY(&ah->iniModesRxGain, 663 ar955x_1p0_common_wo_xlna_rx_gain_table); 664 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 665 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 666 } else if (AR_SREV_9580(ah)) 667 INIT_INI_ARRAY(&ah->iniModesRxGain, 668 ar9580_1p0_wo_xlna_rx_gain_table); 669 else if (AR_SREV_9565(ah)) 670 INIT_INI_ARRAY(&ah->iniModesRxGain, 671 ar9565_1p0_common_wo_xlna_rx_gain_table); 672 else 673 INIT_INI_ARRAY(&ah->iniModesRxGain, 674 ar9300Common_wo_xlna_rx_gain_table_2p2); 675 } 676 677 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 678 { 679 if (AR_SREV_9462_21(ah)) { 680 INIT_INI_ARRAY(&ah->iniModesRxGain, 681 ar9462_2p1_common_mixed_rx_gain); 682 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 683 ar9462_2p1_baseband_core_mix_rxgain); 684 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 685 ar9462_2p1_baseband_postamble_mix_rxgain); 686 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 687 ar9462_2p1_baseband_postamble_5g_xlna); 688 } else if (AR_SREV_9462_20(ah)) { 689 INIT_INI_ARRAY(&ah->iniModesRxGain, 690 ar9462_common_mixed_rx_gain_table_2p0); 691 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 692 ar9462_2p0_baseband_core_mix_rxgain); 693 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 694 ar9462_2p0_baseband_postamble_mix_rxgain); 695 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 696 ar9462_2p0_baseband_postamble_5g_xlna); 697 } 698 } 699 700 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) 701 { 702 if (AR_SREV_9462_21(ah)) { 703 INIT_INI_ARRAY(&ah->iniModesRxGain, 704 ar9462_2p1_common_5g_xlna_only_rx_gain); 705 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 706 ar9462_2p1_baseband_postamble_5g_xlna); 707 } else if (AR_SREV_9462_20(ah)) { 708 INIT_INI_ARRAY(&ah->iniModesRxGain, 709 ar9462_2p0_5g_xlna_only_rxgain); 710 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 711 ar9462_2p0_baseband_postamble_5g_xlna); 712 } 713 } 714 715 static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 716 { 717 switch (ar9003_hw_get_rx_gain_idx(ah)) { 718 case 0: 719 default: 720 ar9003_rx_gain_table_mode0(ah); 721 break; 722 case 1: 723 ar9003_rx_gain_table_mode1(ah); 724 break; 725 case 2: 726 ar9003_rx_gain_table_mode2(ah); 727 break; 728 case 3: 729 ar9003_rx_gain_table_mode3(ah); 730 break; 731 } 732 } 733 734 /* set gain table pointers according to values read from the eeprom */ 735 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) 736 { 737 ar9003_tx_gain_table_apply(ah); 738 ar9003_rx_gain_table_apply(ah); 739 } 740 741 /* 742 * Helper for ASPM support. 743 * 744 * Disable PLL when in L0s as well as receiver clock when in L1. 745 * This power saving option must be enabled through the SerDes. 746 * 747 * Programming the SerDes must go through the same 288 bit serial shift 748 * register as the other analog registers. Hence the 9 writes. 749 */ 750 static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 751 bool power_off) 752 { 753 /* 754 * Increase L1 Entry Latency. Some WB222 boards don't have 755 * this change in eeprom/OTP. 756 * 757 */ 758 if (AR_SREV_9462(ah)) { 759 u32 val = ah->config.aspm_l1_fix; 760 if ((val & 0xff000000) == 0x17000000) { 761 val &= 0x00ffffff; 762 val |= 0x27000000; 763 REG_WRITE(ah, 0x570c, val); 764 } 765 } 766 767 /* Nothing to do on restore for 11N */ 768 if (!power_off /* !restore */) { 769 /* set bit 19 to allow forcing of pcie core into L1 state */ 770 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 771 REG_WRITE(ah, AR_WA, ah->WARegVal); 772 } 773 774 /* 775 * Configire PCIE after Ini init. SERDES values now come from ini file 776 * This enables PCIe low power mode. 777 */ 778 if (ah->config.pcieSerDesWrite) { 779 unsigned int i; 780 struct ar5416IniArray *array; 781 782 array = power_off ? &ah->iniPcieSerdes : 783 &ah->iniPcieSerdesLowPower; 784 785 for (i = 0; i < array->ia_rows; i++) { 786 REG_WRITE(ah, 787 INI_RA(array, i, 0), 788 INI_RA(array, i, 1)); 789 } 790 } 791 } 792 793 /* Sets up the AR9003 hardware familiy callbacks */ 794 void ar9003_hw_attach_ops(struct ath_hw *ah) 795 { 796 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 797 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 798 799 ar9003_hw_init_mode_regs(ah); 800 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 801 802 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 803 804 ar9003_hw_attach_phy_ops(ah); 805 ar9003_hw_attach_calib_ops(ah); 806 ar9003_hw_attach_mac_ops(ah); 807 } 808