1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <asm/unaligned.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 #include "ar9003_eeprom.h" 21 #include "ar9003_mci.h" 22 23 #define COMP_HDR_LEN 4 24 #define COMP_CKSUM_LEN 2 25 26 #define LE16(x) __constant_cpu_to_le16(x) 27 #define LE32(x) __constant_cpu_to_le32(x) 28 29 /* Local defines to distinguish between extension and control CTL's */ 30 #define EXT_ADDITIVE (0x8000) 31 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 32 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 33 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 34 35 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 36 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 37 38 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) 39 40 #define EEPROM_DATA_LEN_9485 1088 41 42 static int ar9003_hw_power_interpolate(int32_t x, 43 int32_t *px, int32_t *py, u_int16_t np); 44 45 static const struct ar9300_eeprom ar9300_default = { 46 .eepromVersion = 2, 47 .templateVersion = 2, 48 .macAddr = {0, 2, 3, 4, 5, 6}, 49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 51 .baseEepHeader = { 52 .regDmn = { LE16(0), LE16(0x1f) }, 53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 54 .opCapFlags = { 55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 56 .eepMisc = 0, 57 }, 58 .rfSilent = 0, 59 .blueToothOptions = 0, 60 .deviceCap = 0, 61 .deviceType = 5, /* takes lower byte in eeprom location */ 62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 63 .params_for_tuning_caps = {0, 0}, 64 .featureEnable = 0x0c, 65 /* 66 * bit0 - enable tx temp comp - disabled 67 * bit1 - enable tx volt comp - disabled 68 * bit2 - enable fastClock - enabled 69 * bit3 - enable doubling - enabled 70 * bit4 - enable internal regulator - disabled 71 * bit5 - enable pa predistortion - disabled 72 */ 73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 74 .eepromWriteEnableGpio = 3, 75 .wlanDisableGpio = 0, 76 .wlanLedGpio = 8, 77 .rxBandSelectGpio = 0xff, 78 .txrxgain = 0, 79 .swreg = 0, 80 }, 81 .modalHeader2G = { 82 /* ar9300_modal_eep_header 2g */ 83 /* 4 idle,t1,t2,b(4 bits per setting) */ 84 .antCtrlCommon = LE32(0x110), 85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 86 .antCtrlCommon2 = LE32(0x22222), 87 88 /* 89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 90 * rx1, rx12, b (2 bits each) 91 */ 92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 93 94 /* 95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 96 * for ar9280 (0xa20c/b20c 5:0) 97 */ 98 .xatten1DB = {0, 0, 0}, 99 100 /* 101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 102 * for ar9280 (0xa20c/b20c 16:12 103 */ 104 .xatten1Margin = {0, 0, 0}, 105 .tempSlope = 36, 106 .voltSlope = 0, 107 108 /* 109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 110 * channels in usual fbin coding format 111 */ 112 .spurChans = {0, 0, 0, 0, 0}, 113 114 /* 115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 116 * if the register is per chain 117 */ 118 .noiseFloorThreshCh = {-1, 0, 0}, 119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 120 .quick_drop = 0, 121 .xpaBiasLvl = 0, 122 .txFrameToDataStart = 0x0e, 123 .txFrameToPaOn = 0x0e, 124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 125 .antennaGain = 0, 126 .switchSettling = 0x2c, 127 .adcDesiredSize = -30, 128 .txEndToXpaOff = 0, 129 .txEndToRxOn = 0x2, 130 .txFrameToXpaOn = 0xe, 131 .thresh62 = 28, 132 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 133 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 134 .xlna_bias_strength = 0, 135 .futureModal = { 136 0, 0, 0, 0, 0, 0, 0, 137 }, 138 }, 139 .base_ext1 = { 140 .ant_div_control = 0, 141 .future = {0, 0, 0}, 142 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} 143 }, 144 .calFreqPier2G = { 145 FREQ2FBIN(2412, 1), 146 FREQ2FBIN(2437, 1), 147 FREQ2FBIN(2472, 1), 148 }, 149 /* ar9300_cal_data_per_freq_op_loop 2g */ 150 .calPierData2G = { 151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 152 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 153 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 154 }, 155 .calTarget_freqbin_Cck = { 156 FREQ2FBIN(2412, 1), 157 FREQ2FBIN(2484, 1), 158 }, 159 .calTarget_freqbin_2G = { 160 FREQ2FBIN(2412, 1), 161 FREQ2FBIN(2437, 1), 162 FREQ2FBIN(2472, 1) 163 }, 164 .calTarget_freqbin_2GHT20 = { 165 FREQ2FBIN(2412, 1), 166 FREQ2FBIN(2437, 1), 167 FREQ2FBIN(2472, 1) 168 }, 169 .calTarget_freqbin_2GHT40 = { 170 FREQ2FBIN(2412, 1), 171 FREQ2FBIN(2437, 1), 172 FREQ2FBIN(2472, 1) 173 }, 174 .calTargetPowerCck = { 175 /* 1L-5L,5S,11L,11S */ 176 { {36, 36, 36, 36} }, 177 { {36, 36, 36, 36} }, 178 }, 179 .calTargetPower2G = { 180 /* 6-24,36,48,54 */ 181 { {32, 32, 28, 24} }, 182 { {32, 32, 28, 24} }, 183 { {32, 32, 28, 24} }, 184 }, 185 .calTargetPower2GHT20 = { 186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 187 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 188 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 189 }, 190 .calTargetPower2GHT40 = { 191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 194 }, 195 .ctlIndex_2G = { 196 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 197 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 198 }, 199 .ctl_freqbin_2G = { 200 { 201 FREQ2FBIN(2412, 1), 202 FREQ2FBIN(2417, 1), 203 FREQ2FBIN(2457, 1), 204 FREQ2FBIN(2462, 1) 205 }, 206 { 207 FREQ2FBIN(2412, 1), 208 FREQ2FBIN(2417, 1), 209 FREQ2FBIN(2462, 1), 210 0xFF, 211 }, 212 213 { 214 FREQ2FBIN(2412, 1), 215 FREQ2FBIN(2417, 1), 216 FREQ2FBIN(2462, 1), 217 0xFF, 218 }, 219 { 220 FREQ2FBIN(2422, 1), 221 FREQ2FBIN(2427, 1), 222 FREQ2FBIN(2447, 1), 223 FREQ2FBIN(2452, 1) 224 }, 225 226 { 227 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 228 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 229 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 230 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 231 }, 232 233 { 234 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 235 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 236 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 237 0, 238 }, 239 240 { 241 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 242 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 243 FREQ2FBIN(2472, 1), 244 0, 245 }, 246 247 { 248 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 249 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 250 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 251 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 252 }, 253 254 { 255 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 256 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 257 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 258 }, 259 260 { 261 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 262 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 263 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 264 0 265 }, 266 267 { 268 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 269 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 270 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 271 0 272 }, 273 274 { 275 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 276 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 277 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 278 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 279 } 280 }, 281 .ctlPowerData_2G = { 282 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 283 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 285 286 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 287 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 289 290 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 291 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 293 294 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 295 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 296 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 297 }, 298 .modalHeader5G = { 299 /* 4 idle,t1,t2,b (4 bits per setting) */ 300 .antCtrlCommon = LE32(0x110), 301 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 302 .antCtrlCommon2 = LE32(0x22222), 303 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 304 .antCtrlChain = { 305 LE16(0x000), LE16(0x000), LE16(0x000), 306 }, 307 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 308 .xatten1DB = {0, 0, 0}, 309 310 /* 311 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 312 * for merlin (0xa20c/b20c 16:12 313 */ 314 .xatten1Margin = {0, 0, 0}, 315 .tempSlope = 68, 316 .voltSlope = 0, 317 /* spurChans spur channels in usual fbin coding format */ 318 .spurChans = {0, 0, 0, 0, 0}, 319 /* noiseFloorThreshCh Check if the register is per chain */ 320 .noiseFloorThreshCh = {-1, 0, 0}, 321 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 322 .quick_drop = 0, 323 .xpaBiasLvl = 0, 324 .txFrameToDataStart = 0x0e, 325 .txFrameToPaOn = 0x0e, 326 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 327 .antennaGain = 0, 328 .switchSettling = 0x2d, 329 .adcDesiredSize = -30, 330 .txEndToXpaOff = 0, 331 .txEndToRxOn = 0x2, 332 .txFrameToXpaOn = 0xe, 333 .thresh62 = 28, 334 .papdRateMaskHt20 = LE32(0x0c80c080), 335 .papdRateMaskHt40 = LE32(0x0080c080), 336 .xlna_bias_strength = 0, 337 .futureModal = { 338 0, 0, 0, 0, 0, 0, 0, 339 }, 340 }, 341 .base_ext2 = { 342 .tempSlopeLow = 0, 343 .tempSlopeHigh = 0, 344 .xatten1DBLow = {0, 0, 0}, 345 .xatten1MarginLow = {0, 0, 0}, 346 .xatten1DBHigh = {0, 0, 0}, 347 .xatten1MarginHigh = {0, 0, 0} 348 }, 349 .calFreqPier5G = { 350 FREQ2FBIN(5180, 0), 351 FREQ2FBIN(5220, 0), 352 FREQ2FBIN(5320, 0), 353 FREQ2FBIN(5400, 0), 354 FREQ2FBIN(5500, 0), 355 FREQ2FBIN(5600, 0), 356 FREQ2FBIN(5725, 0), 357 FREQ2FBIN(5825, 0) 358 }, 359 .calPierData5G = { 360 { 361 {0, 0, 0, 0, 0}, 362 {0, 0, 0, 0, 0}, 363 {0, 0, 0, 0, 0}, 364 {0, 0, 0, 0, 0}, 365 {0, 0, 0, 0, 0}, 366 {0, 0, 0, 0, 0}, 367 {0, 0, 0, 0, 0}, 368 {0, 0, 0, 0, 0}, 369 }, 370 { 371 {0, 0, 0, 0, 0}, 372 {0, 0, 0, 0, 0}, 373 {0, 0, 0, 0, 0}, 374 {0, 0, 0, 0, 0}, 375 {0, 0, 0, 0, 0}, 376 {0, 0, 0, 0, 0}, 377 {0, 0, 0, 0, 0}, 378 {0, 0, 0, 0, 0}, 379 }, 380 { 381 {0, 0, 0, 0, 0}, 382 {0, 0, 0, 0, 0}, 383 {0, 0, 0, 0, 0}, 384 {0, 0, 0, 0, 0}, 385 {0, 0, 0, 0, 0}, 386 {0, 0, 0, 0, 0}, 387 {0, 0, 0, 0, 0}, 388 {0, 0, 0, 0, 0}, 389 }, 390 391 }, 392 .calTarget_freqbin_5G = { 393 FREQ2FBIN(5180, 0), 394 FREQ2FBIN(5220, 0), 395 FREQ2FBIN(5320, 0), 396 FREQ2FBIN(5400, 0), 397 FREQ2FBIN(5500, 0), 398 FREQ2FBIN(5600, 0), 399 FREQ2FBIN(5725, 0), 400 FREQ2FBIN(5825, 0) 401 }, 402 .calTarget_freqbin_5GHT20 = { 403 FREQ2FBIN(5180, 0), 404 FREQ2FBIN(5240, 0), 405 FREQ2FBIN(5320, 0), 406 FREQ2FBIN(5500, 0), 407 FREQ2FBIN(5700, 0), 408 FREQ2FBIN(5745, 0), 409 FREQ2FBIN(5725, 0), 410 FREQ2FBIN(5825, 0) 411 }, 412 .calTarget_freqbin_5GHT40 = { 413 FREQ2FBIN(5180, 0), 414 FREQ2FBIN(5240, 0), 415 FREQ2FBIN(5320, 0), 416 FREQ2FBIN(5500, 0), 417 FREQ2FBIN(5700, 0), 418 FREQ2FBIN(5745, 0), 419 FREQ2FBIN(5725, 0), 420 FREQ2FBIN(5825, 0) 421 }, 422 .calTargetPower5G = { 423 /* 6-24,36,48,54 */ 424 { {20, 20, 20, 10} }, 425 { {20, 20, 20, 10} }, 426 { {20, 20, 20, 10} }, 427 { {20, 20, 20, 10} }, 428 { {20, 20, 20, 10} }, 429 { {20, 20, 20, 10} }, 430 { {20, 20, 20, 10} }, 431 { {20, 20, 20, 10} }, 432 }, 433 .calTargetPower5GHT20 = { 434 /* 435 * 0_8_16,1-3_9-11_17-19, 436 * 4,5,6,7,12,13,14,15,20,21,22,23 437 */ 438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 443 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 446 }, 447 .calTargetPower5GHT40 = { 448 /* 449 * 0_8_16,1-3_9-11_17-19, 450 * 4,5,6,7,12,13,14,15,20,21,22,23 451 */ 452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 460 }, 461 .ctlIndex_5G = { 462 0x10, 0x16, 0x18, 0x40, 0x46, 463 0x48, 0x30, 0x36, 0x38 464 }, 465 .ctl_freqbin_5G = { 466 { 467 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 468 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 469 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 470 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 471 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 472 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 473 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 474 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 475 }, 476 { 477 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 478 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 479 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 480 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 481 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 482 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 483 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 484 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 485 }, 486 487 { 488 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 489 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 490 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 491 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 492 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 493 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 494 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 495 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 496 }, 497 498 { 499 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 500 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 501 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 502 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 503 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 504 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 505 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 506 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 507 }, 508 509 { 510 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 511 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 512 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 513 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 514 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 515 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 516 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 517 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 518 }, 519 520 { 521 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 522 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 523 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 524 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 525 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 526 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 527 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 528 /* Data[5].ctlEdges[7].bChannel */ 0xFF 529 }, 530 531 { 532 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 533 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 534 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 535 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 536 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 537 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 538 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 539 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 540 }, 541 542 { 543 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 544 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 545 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 546 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 547 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 548 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 549 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 550 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 551 }, 552 553 { 554 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 555 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 556 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 557 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 558 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 559 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 560 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 561 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 562 } 563 }, 564 .ctlPowerData_5G = { 565 { 566 { 567 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 568 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 569 } 570 }, 571 { 572 { 573 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 575 } 576 }, 577 { 578 { 579 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 581 } 582 }, 583 { 584 { 585 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 586 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 587 } 588 }, 589 { 590 { 591 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 592 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 593 } 594 }, 595 { 596 { 597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 598 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 599 } 600 }, 601 { 602 { 603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 604 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 605 } 606 }, 607 { 608 { 609 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 611 } 612 }, 613 { 614 { 615 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 616 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 617 } 618 }, 619 } 620 }; 621 622 static const struct ar9300_eeprom ar9300_x113 = { 623 .eepromVersion = 2, 624 .templateVersion = 6, 625 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 626 .custData = {"x113-023-f0000"}, 627 .baseEepHeader = { 628 .regDmn = { LE16(0), LE16(0x1f) }, 629 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 630 .opCapFlags = { 631 .opFlags = AR5416_OPFLAGS_11A, 632 .eepMisc = 0, 633 }, 634 .rfSilent = 0, 635 .blueToothOptions = 0, 636 .deviceCap = 0, 637 .deviceType = 5, /* takes lower byte in eeprom location */ 638 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 639 .params_for_tuning_caps = {0, 0}, 640 .featureEnable = 0x0d, 641 /* 642 * bit0 - enable tx temp comp - disabled 643 * bit1 - enable tx volt comp - disabled 644 * bit2 - enable fastClock - enabled 645 * bit3 - enable doubling - enabled 646 * bit4 - enable internal regulator - disabled 647 * bit5 - enable pa predistortion - disabled 648 */ 649 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 650 .eepromWriteEnableGpio = 6, 651 .wlanDisableGpio = 0, 652 .wlanLedGpio = 8, 653 .rxBandSelectGpio = 0xff, 654 .txrxgain = 0x21, 655 .swreg = 0, 656 }, 657 .modalHeader2G = { 658 /* ar9300_modal_eep_header 2g */ 659 /* 4 idle,t1,t2,b(4 bits per setting) */ 660 .antCtrlCommon = LE32(0x110), 661 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 662 .antCtrlCommon2 = LE32(0x44444), 663 664 /* 665 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 666 * rx1, rx12, b (2 bits each) 667 */ 668 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 669 670 /* 671 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 672 * for ar9280 (0xa20c/b20c 5:0) 673 */ 674 .xatten1DB = {0, 0, 0}, 675 676 /* 677 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 678 * for ar9280 (0xa20c/b20c 16:12 679 */ 680 .xatten1Margin = {0, 0, 0}, 681 .tempSlope = 25, 682 .voltSlope = 0, 683 684 /* 685 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 686 * channels in usual fbin coding format 687 */ 688 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 689 690 /* 691 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 692 * if the register is per chain 693 */ 694 .noiseFloorThreshCh = {-1, 0, 0}, 695 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 696 .quick_drop = 0, 697 .xpaBiasLvl = 0, 698 .txFrameToDataStart = 0x0e, 699 .txFrameToPaOn = 0x0e, 700 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 701 .antennaGain = 0, 702 .switchSettling = 0x2c, 703 .adcDesiredSize = -30, 704 .txEndToXpaOff = 0, 705 .txEndToRxOn = 0x2, 706 .txFrameToXpaOn = 0xe, 707 .thresh62 = 28, 708 .papdRateMaskHt20 = LE32(0x0c80c080), 709 .papdRateMaskHt40 = LE32(0x0080c080), 710 .xlna_bias_strength = 0, 711 .futureModal = { 712 0, 0, 0, 0, 0, 0, 0, 713 }, 714 }, 715 .base_ext1 = { 716 .ant_div_control = 0, 717 .future = {0, 0, 0}, 718 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} 719 }, 720 .calFreqPier2G = { 721 FREQ2FBIN(2412, 1), 722 FREQ2FBIN(2437, 1), 723 FREQ2FBIN(2472, 1), 724 }, 725 /* ar9300_cal_data_per_freq_op_loop 2g */ 726 .calPierData2G = { 727 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 728 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 729 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 730 }, 731 .calTarget_freqbin_Cck = { 732 FREQ2FBIN(2412, 1), 733 FREQ2FBIN(2472, 1), 734 }, 735 .calTarget_freqbin_2G = { 736 FREQ2FBIN(2412, 1), 737 FREQ2FBIN(2437, 1), 738 FREQ2FBIN(2472, 1) 739 }, 740 .calTarget_freqbin_2GHT20 = { 741 FREQ2FBIN(2412, 1), 742 FREQ2FBIN(2437, 1), 743 FREQ2FBIN(2472, 1) 744 }, 745 .calTarget_freqbin_2GHT40 = { 746 FREQ2FBIN(2412, 1), 747 FREQ2FBIN(2437, 1), 748 FREQ2FBIN(2472, 1) 749 }, 750 .calTargetPowerCck = { 751 /* 1L-5L,5S,11L,11S */ 752 { {34, 34, 34, 34} }, 753 { {34, 34, 34, 34} }, 754 }, 755 .calTargetPower2G = { 756 /* 6-24,36,48,54 */ 757 { {34, 34, 32, 32} }, 758 { {34, 34, 32, 32} }, 759 { {34, 34, 32, 32} }, 760 }, 761 .calTargetPower2GHT20 = { 762 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 763 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 764 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 765 }, 766 .calTargetPower2GHT40 = { 767 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 768 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 769 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 770 }, 771 .ctlIndex_2G = { 772 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 773 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 774 }, 775 .ctl_freqbin_2G = { 776 { 777 FREQ2FBIN(2412, 1), 778 FREQ2FBIN(2417, 1), 779 FREQ2FBIN(2457, 1), 780 FREQ2FBIN(2462, 1) 781 }, 782 { 783 FREQ2FBIN(2412, 1), 784 FREQ2FBIN(2417, 1), 785 FREQ2FBIN(2462, 1), 786 0xFF, 787 }, 788 789 { 790 FREQ2FBIN(2412, 1), 791 FREQ2FBIN(2417, 1), 792 FREQ2FBIN(2462, 1), 793 0xFF, 794 }, 795 { 796 FREQ2FBIN(2422, 1), 797 FREQ2FBIN(2427, 1), 798 FREQ2FBIN(2447, 1), 799 FREQ2FBIN(2452, 1) 800 }, 801 802 { 803 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 804 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 805 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 806 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 807 }, 808 809 { 810 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 811 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 812 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 813 0, 814 }, 815 816 { 817 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 818 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 819 FREQ2FBIN(2472, 1), 820 0, 821 }, 822 823 { 824 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 825 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 826 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 827 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 828 }, 829 830 { 831 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 832 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 833 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 834 }, 835 836 { 837 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 838 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 839 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 840 0 841 }, 842 843 { 844 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 845 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 846 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 847 0 848 }, 849 850 { 851 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 852 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 853 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 854 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 855 } 856 }, 857 .ctlPowerData_2G = { 858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 860 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 861 862 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 864 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 865 866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 867 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 868 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 869 870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 871 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 872 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 873 }, 874 .modalHeader5G = { 875 /* 4 idle,t1,t2,b (4 bits per setting) */ 876 .antCtrlCommon = LE32(0x220), 877 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 878 .antCtrlCommon2 = LE32(0x11111), 879 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 880 .antCtrlChain = { 881 LE16(0x150), LE16(0x150), LE16(0x150), 882 }, 883 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 884 .xatten1DB = {0, 0, 0}, 885 886 /* 887 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 888 * for merlin (0xa20c/b20c 16:12 889 */ 890 .xatten1Margin = {0, 0, 0}, 891 .tempSlope = 68, 892 .voltSlope = 0, 893 /* spurChans spur channels in usual fbin coding format */ 894 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0}, 895 /* noiseFloorThreshCh Check if the register is per chain */ 896 .noiseFloorThreshCh = {-1, 0, 0}, 897 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 898 .quick_drop = 0, 899 .xpaBiasLvl = 0xf, 900 .txFrameToDataStart = 0x0e, 901 .txFrameToPaOn = 0x0e, 902 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 903 .antennaGain = 0, 904 .switchSettling = 0x2d, 905 .adcDesiredSize = -30, 906 .txEndToXpaOff = 0, 907 .txEndToRxOn = 0x2, 908 .txFrameToXpaOn = 0xe, 909 .thresh62 = 28, 910 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 911 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 912 .xlna_bias_strength = 0, 913 .futureModal = { 914 0, 0, 0, 0, 0, 0, 0, 915 }, 916 }, 917 .base_ext2 = { 918 .tempSlopeLow = 72, 919 .tempSlopeHigh = 105, 920 .xatten1DBLow = {0, 0, 0}, 921 .xatten1MarginLow = {0, 0, 0}, 922 .xatten1DBHigh = {0, 0, 0}, 923 .xatten1MarginHigh = {0, 0, 0} 924 }, 925 .calFreqPier5G = { 926 FREQ2FBIN(5180, 0), 927 FREQ2FBIN(5240, 0), 928 FREQ2FBIN(5320, 0), 929 FREQ2FBIN(5400, 0), 930 FREQ2FBIN(5500, 0), 931 FREQ2FBIN(5600, 0), 932 FREQ2FBIN(5745, 0), 933 FREQ2FBIN(5785, 0) 934 }, 935 .calPierData5G = { 936 { 937 {0, 0, 0, 0, 0}, 938 {0, 0, 0, 0, 0}, 939 {0, 0, 0, 0, 0}, 940 {0, 0, 0, 0, 0}, 941 {0, 0, 0, 0, 0}, 942 {0, 0, 0, 0, 0}, 943 {0, 0, 0, 0, 0}, 944 {0, 0, 0, 0, 0}, 945 }, 946 { 947 {0, 0, 0, 0, 0}, 948 {0, 0, 0, 0, 0}, 949 {0, 0, 0, 0, 0}, 950 {0, 0, 0, 0, 0}, 951 {0, 0, 0, 0, 0}, 952 {0, 0, 0, 0, 0}, 953 {0, 0, 0, 0, 0}, 954 {0, 0, 0, 0, 0}, 955 }, 956 { 957 {0, 0, 0, 0, 0}, 958 {0, 0, 0, 0, 0}, 959 {0, 0, 0, 0, 0}, 960 {0, 0, 0, 0, 0}, 961 {0, 0, 0, 0, 0}, 962 {0, 0, 0, 0, 0}, 963 {0, 0, 0, 0, 0}, 964 {0, 0, 0, 0, 0}, 965 }, 966 967 }, 968 .calTarget_freqbin_5G = { 969 FREQ2FBIN(5180, 0), 970 FREQ2FBIN(5220, 0), 971 FREQ2FBIN(5320, 0), 972 FREQ2FBIN(5400, 0), 973 FREQ2FBIN(5500, 0), 974 FREQ2FBIN(5600, 0), 975 FREQ2FBIN(5745, 0), 976 FREQ2FBIN(5785, 0) 977 }, 978 .calTarget_freqbin_5GHT20 = { 979 FREQ2FBIN(5180, 0), 980 FREQ2FBIN(5240, 0), 981 FREQ2FBIN(5320, 0), 982 FREQ2FBIN(5400, 0), 983 FREQ2FBIN(5500, 0), 984 FREQ2FBIN(5700, 0), 985 FREQ2FBIN(5745, 0), 986 FREQ2FBIN(5825, 0) 987 }, 988 .calTarget_freqbin_5GHT40 = { 989 FREQ2FBIN(5190, 0), 990 FREQ2FBIN(5230, 0), 991 FREQ2FBIN(5320, 0), 992 FREQ2FBIN(5410, 0), 993 FREQ2FBIN(5510, 0), 994 FREQ2FBIN(5670, 0), 995 FREQ2FBIN(5755, 0), 996 FREQ2FBIN(5825, 0) 997 }, 998 .calTargetPower5G = { 999 /* 6-24,36,48,54 */ 1000 { {42, 40, 40, 34} }, 1001 { {42, 40, 40, 34} }, 1002 { {42, 40, 40, 34} }, 1003 { {42, 40, 40, 34} }, 1004 { {42, 40, 40, 34} }, 1005 { {42, 40, 40, 34} }, 1006 { {42, 40, 40, 34} }, 1007 { {42, 40, 40, 34} }, 1008 }, 1009 .calTargetPower5GHT20 = { 1010 /* 1011 * 0_8_16,1-3_9-11_17-19, 1012 * 4,5,6,7,12,13,14,15,20,21,22,23 1013 */ 1014 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1015 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1016 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1017 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1018 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1019 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1020 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} }, 1021 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} }, 1022 }, 1023 .calTargetPower5GHT40 = { 1024 /* 1025 * 0_8_16,1-3_9-11_17-19, 1026 * 4,5,6,7,12,13,14,15,20,21,22,23 1027 */ 1028 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1029 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1030 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1031 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1032 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1033 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1034 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} }, 1035 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} }, 1036 }, 1037 .ctlIndex_5G = { 1038 0x10, 0x16, 0x18, 0x40, 0x46, 1039 0x48, 0x30, 0x36, 0x38 1040 }, 1041 .ctl_freqbin_5G = { 1042 { 1043 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1044 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1045 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1046 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1047 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 1048 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1049 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1050 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1051 }, 1052 { 1053 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1054 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1055 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1056 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1057 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 1058 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1059 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1060 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1061 }, 1062 1063 { 1064 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1065 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1066 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1067 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 1068 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 1069 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 1070 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 1071 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 1072 }, 1073 1074 { 1075 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1076 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1077 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 1078 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 1079 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1080 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1081 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 1082 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 1083 }, 1084 1085 { 1086 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1087 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1088 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 1089 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 1090 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 1091 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 1092 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 1093 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 1094 }, 1095 1096 { 1097 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1098 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 1099 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 1100 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1101 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 1102 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1103 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 1104 /* Data[5].ctlEdges[7].bChannel */ 0xFF 1105 }, 1106 1107 { 1108 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1109 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1110 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 1111 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 1112 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1113 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 1114 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 1115 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 1116 }, 1117 1118 { 1119 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1120 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1121 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 1122 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1123 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 1124 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1125 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1126 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1127 }, 1128 1129 { 1130 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1131 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1132 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1133 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1134 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 1135 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1136 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 1137 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 1138 } 1139 }, 1140 .ctlPowerData_5G = { 1141 { 1142 { 1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1145 } 1146 }, 1147 { 1148 { 1149 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1151 } 1152 }, 1153 { 1154 { 1155 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1156 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1157 } 1158 }, 1159 { 1160 { 1161 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1162 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1163 } 1164 }, 1165 { 1166 { 1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1168 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1169 } 1170 }, 1171 { 1172 { 1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1174 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1175 } 1176 }, 1177 { 1178 { 1179 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1181 } 1182 }, 1183 { 1184 { 1185 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1186 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1187 } 1188 }, 1189 { 1190 { 1191 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 1192 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1193 } 1194 }, 1195 } 1196 }; 1197 1198 1199 static const struct ar9300_eeprom ar9300_h112 = { 1200 .eepromVersion = 2, 1201 .templateVersion = 3, 1202 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 1203 .custData = {"h112-241-f0000"}, 1204 .baseEepHeader = { 1205 .regDmn = { LE16(0), LE16(0x1f) }, 1206 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1207 .opCapFlags = { 1208 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 1209 .eepMisc = 0, 1210 }, 1211 .rfSilent = 0, 1212 .blueToothOptions = 0, 1213 .deviceCap = 0, 1214 .deviceType = 5, /* takes lower byte in eeprom location */ 1215 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 1216 .params_for_tuning_caps = {0, 0}, 1217 .featureEnable = 0x0d, 1218 /* 1219 * bit0 - enable tx temp comp - disabled 1220 * bit1 - enable tx volt comp - disabled 1221 * bit2 - enable fastClock - enabled 1222 * bit3 - enable doubling - enabled 1223 * bit4 - enable internal regulator - disabled 1224 * bit5 - enable pa predistortion - disabled 1225 */ 1226 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 1227 .eepromWriteEnableGpio = 6, 1228 .wlanDisableGpio = 0, 1229 .wlanLedGpio = 8, 1230 .rxBandSelectGpio = 0xff, 1231 .txrxgain = 0x10, 1232 .swreg = 0, 1233 }, 1234 .modalHeader2G = { 1235 /* ar9300_modal_eep_header 2g */ 1236 /* 4 idle,t1,t2,b(4 bits per setting) */ 1237 .antCtrlCommon = LE32(0x110), 1238 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 1239 .antCtrlCommon2 = LE32(0x44444), 1240 1241 /* 1242 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 1243 * rx1, rx12, b (2 bits each) 1244 */ 1245 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 1246 1247 /* 1248 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 1249 * for ar9280 (0xa20c/b20c 5:0) 1250 */ 1251 .xatten1DB = {0, 0, 0}, 1252 1253 /* 1254 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 1255 * for ar9280 (0xa20c/b20c 16:12 1256 */ 1257 .xatten1Margin = {0, 0, 0}, 1258 .tempSlope = 25, 1259 .voltSlope = 0, 1260 1261 /* 1262 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 1263 * channels in usual fbin coding format 1264 */ 1265 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 1266 1267 /* 1268 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 1269 * if the register is per chain 1270 */ 1271 .noiseFloorThreshCh = {-1, 0, 0}, 1272 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 1273 .quick_drop = 0, 1274 .xpaBiasLvl = 0, 1275 .txFrameToDataStart = 0x0e, 1276 .txFrameToPaOn = 0x0e, 1277 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1278 .antennaGain = 0, 1279 .switchSettling = 0x2c, 1280 .adcDesiredSize = -30, 1281 .txEndToXpaOff = 0, 1282 .txEndToRxOn = 0x2, 1283 .txFrameToXpaOn = 0xe, 1284 .thresh62 = 28, 1285 .papdRateMaskHt20 = LE32(0x0c80c080), 1286 .papdRateMaskHt40 = LE32(0x0080c080), 1287 .xlna_bias_strength = 0, 1288 .futureModal = { 1289 0, 0, 0, 0, 0, 0, 0, 1290 }, 1291 }, 1292 .base_ext1 = { 1293 .ant_div_control = 0, 1294 .future = {0, 0, 0}, 1295 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} 1296 }, 1297 .calFreqPier2G = { 1298 FREQ2FBIN(2412, 1), 1299 FREQ2FBIN(2437, 1), 1300 FREQ2FBIN(2462, 1), 1301 }, 1302 /* ar9300_cal_data_per_freq_op_loop 2g */ 1303 .calPierData2G = { 1304 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1305 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1306 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1307 }, 1308 .calTarget_freqbin_Cck = { 1309 FREQ2FBIN(2412, 1), 1310 FREQ2FBIN(2472, 1), 1311 }, 1312 .calTarget_freqbin_2G = { 1313 FREQ2FBIN(2412, 1), 1314 FREQ2FBIN(2437, 1), 1315 FREQ2FBIN(2472, 1) 1316 }, 1317 .calTarget_freqbin_2GHT20 = { 1318 FREQ2FBIN(2412, 1), 1319 FREQ2FBIN(2437, 1), 1320 FREQ2FBIN(2472, 1) 1321 }, 1322 .calTarget_freqbin_2GHT40 = { 1323 FREQ2FBIN(2412, 1), 1324 FREQ2FBIN(2437, 1), 1325 FREQ2FBIN(2472, 1) 1326 }, 1327 .calTargetPowerCck = { 1328 /* 1L-5L,5S,11L,11S */ 1329 { {34, 34, 34, 34} }, 1330 { {34, 34, 34, 34} }, 1331 }, 1332 .calTargetPower2G = { 1333 /* 6-24,36,48,54 */ 1334 { {34, 34, 32, 32} }, 1335 { {34, 34, 32, 32} }, 1336 { {34, 34, 32, 32} }, 1337 }, 1338 .calTargetPower2GHT20 = { 1339 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1340 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1341 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1342 }, 1343 .calTargetPower2GHT40 = { 1344 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1345 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1346 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1347 }, 1348 .ctlIndex_2G = { 1349 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 1350 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 1351 }, 1352 .ctl_freqbin_2G = { 1353 { 1354 FREQ2FBIN(2412, 1), 1355 FREQ2FBIN(2417, 1), 1356 FREQ2FBIN(2457, 1), 1357 FREQ2FBIN(2462, 1) 1358 }, 1359 { 1360 FREQ2FBIN(2412, 1), 1361 FREQ2FBIN(2417, 1), 1362 FREQ2FBIN(2462, 1), 1363 0xFF, 1364 }, 1365 1366 { 1367 FREQ2FBIN(2412, 1), 1368 FREQ2FBIN(2417, 1), 1369 FREQ2FBIN(2462, 1), 1370 0xFF, 1371 }, 1372 { 1373 FREQ2FBIN(2422, 1), 1374 FREQ2FBIN(2427, 1), 1375 FREQ2FBIN(2447, 1), 1376 FREQ2FBIN(2452, 1) 1377 }, 1378 1379 { 1380 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1381 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1382 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1383 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 1384 }, 1385 1386 { 1387 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1388 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1389 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1390 0, 1391 }, 1392 1393 { 1394 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1395 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1396 FREQ2FBIN(2472, 1), 1397 0, 1398 }, 1399 1400 { 1401 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 1402 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 1403 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 1404 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 1405 }, 1406 1407 { 1408 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1409 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1410 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1411 }, 1412 1413 { 1414 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1415 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1416 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1417 0 1418 }, 1419 1420 { 1421 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1422 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1423 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1424 0 1425 }, 1426 1427 { 1428 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 1429 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 1430 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 1431 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 1432 } 1433 }, 1434 .ctlPowerData_2G = { 1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1437 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 1438 1439 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1442 1443 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 1444 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1445 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1446 1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 1449 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 1450 }, 1451 .modalHeader5G = { 1452 /* 4 idle,t1,t2,b (4 bits per setting) */ 1453 .antCtrlCommon = LE32(0x220), 1454 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 1455 .antCtrlCommon2 = LE32(0x44444), 1456 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 1457 .antCtrlChain = { 1458 LE16(0x150), LE16(0x150), LE16(0x150), 1459 }, 1460 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 1461 .xatten1DB = {0, 0, 0}, 1462 1463 /* 1464 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 1465 * for merlin (0xa20c/b20c 16:12 1466 */ 1467 .xatten1Margin = {0, 0, 0}, 1468 .tempSlope = 45, 1469 .voltSlope = 0, 1470 /* spurChans spur channels in usual fbin coding format */ 1471 .spurChans = {0, 0, 0, 0, 0}, 1472 /* noiseFloorThreshCh Check if the register is per chain */ 1473 .noiseFloorThreshCh = {-1, 0, 0}, 1474 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 1475 .quick_drop = 0, 1476 .xpaBiasLvl = 0, 1477 .txFrameToDataStart = 0x0e, 1478 .txFrameToPaOn = 0x0e, 1479 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1480 .antennaGain = 0, 1481 .switchSettling = 0x2d, 1482 .adcDesiredSize = -30, 1483 .txEndToXpaOff = 0, 1484 .txEndToRxOn = 0x2, 1485 .txFrameToXpaOn = 0xe, 1486 .thresh62 = 28, 1487 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 1488 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 1489 .xlna_bias_strength = 0, 1490 .futureModal = { 1491 0, 0, 0, 0, 0, 0, 0, 1492 }, 1493 }, 1494 .base_ext2 = { 1495 .tempSlopeLow = 40, 1496 .tempSlopeHigh = 50, 1497 .xatten1DBLow = {0, 0, 0}, 1498 .xatten1MarginLow = {0, 0, 0}, 1499 .xatten1DBHigh = {0, 0, 0}, 1500 .xatten1MarginHigh = {0, 0, 0} 1501 }, 1502 .calFreqPier5G = { 1503 FREQ2FBIN(5180, 0), 1504 FREQ2FBIN(5220, 0), 1505 FREQ2FBIN(5320, 0), 1506 FREQ2FBIN(5400, 0), 1507 FREQ2FBIN(5500, 0), 1508 FREQ2FBIN(5600, 0), 1509 FREQ2FBIN(5700, 0), 1510 FREQ2FBIN(5785, 0) 1511 }, 1512 .calPierData5G = { 1513 { 1514 {0, 0, 0, 0, 0}, 1515 {0, 0, 0, 0, 0}, 1516 {0, 0, 0, 0, 0}, 1517 {0, 0, 0, 0, 0}, 1518 {0, 0, 0, 0, 0}, 1519 {0, 0, 0, 0, 0}, 1520 {0, 0, 0, 0, 0}, 1521 {0, 0, 0, 0, 0}, 1522 }, 1523 { 1524 {0, 0, 0, 0, 0}, 1525 {0, 0, 0, 0, 0}, 1526 {0, 0, 0, 0, 0}, 1527 {0, 0, 0, 0, 0}, 1528 {0, 0, 0, 0, 0}, 1529 {0, 0, 0, 0, 0}, 1530 {0, 0, 0, 0, 0}, 1531 {0, 0, 0, 0, 0}, 1532 }, 1533 { 1534 {0, 0, 0, 0, 0}, 1535 {0, 0, 0, 0, 0}, 1536 {0, 0, 0, 0, 0}, 1537 {0, 0, 0, 0, 0}, 1538 {0, 0, 0, 0, 0}, 1539 {0, 0, 0, 0, 0}, 1540 {0, 0, 0, 0, 0}, 1541 {0, 0, 0, 0, 0}, 1542 }, 1543 1544 }, 1545 .calTarget_freqbin_5G = { 1546 FREQ2FBIN(5180, 0), 1547 FREQ2FBIN(5240, 0), 1548 FREQ2FBIN(5320, 0), 1549 FREQ2FBIN(5400, 0), 1550 FREQ2FBIN(5500, 0), 1551 FREQ2FBIN(5600, 0), 1552 FREQ2FBIN(5700, 0), 1553 FREQ2FBIN(5825, 0) 1554 }, 1555 .calTarget_freqbin_5GHT20 = { 1556 FREQ2FBIN(5180, 0), 1557 FREQ2FBIN(5240, 0), 1558 FREQ2FBIN(5320, 0), 1559 FREQ2FBIN(5400, 0), 1560 FREQ2FBIN(5500, 0), 1561 FREQ2FBIN(5700, 0), 1562 FREQ2FBIN(5745, 0), 1563 FREQ2FBIN(5825, 0) 1564 }, 1565 .calTarget_freqbin_5GHT40 = { 1566 FREQ2FBIN(5180, 0), 1567 FREQ2FBIN(5240, 0), 1568 FREQ2FBIN(5320, 0), 1569 FREQ2FBIN(5400, 0), 1570 FREQ2FBIN(5500, 0), 1571 FREQ2FBIN(5700, 0), 1572 FREQ2FBIN(5745, 0), 1573 FREQ2FBIN(5825, 0) 1574 }, 1575 .calTargetPower5G = { 1576 /* 6-24,36,48,54 */ 1577 { {30, 30, 28, 24} }, 1578 { {30, 30, 28, 24} }, 1579 { {30, 30, 28, 24} }, 1580 { {30, 30, 28, 24} }, 1581 { {30, 30, 28, 24} }, 1582 { {30, 30, 28, 24} }, 1583 { {30, 30, 28, 24} }, 1584 { {30, 30, 28, 24} }, 1585 }, 1586 .calTargetPower5GHT20 = { 1587 /* 1588 * 0_8_16,1-3_9-11_17-19, 1589 * 4,5,6,7,12,13,14,15,20,21,22,23 1590 */ 1591 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, 1592 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, 1593 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, 1594 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, 1595 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, 1596 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, 1597 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, 1598 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, 1599 }, 1600 .calTargetPower5GHT40 = { 1601 /* 1602 * 0_8_16,1-3_9-11_17-19, 1603 * 4,5,6,7,12,13,14,15,20,21,22,23 1604 */ 1605 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, 1606 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, 1607 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, 1608 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, 1609 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, 1610 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, 1611 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, 1612 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, 1613 }, 1614 .ctlIndex_5G = { 1615 0x10, 0x16, 0x18, 0x40, 0x46, 1616 0x48, 0x30, 0x36, 0x38 1617 }, 1618 .ctl_freqbin_5G = { 1619 { 1620 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1621 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1622 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1623 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1624 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 1625 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1626 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1627 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1628 }, 1629 { 1630 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1631 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1632 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1633 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1634 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 1635 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1636 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1637 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1638 }, 1639 1640 { 1641 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1642 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1643 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1644 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 1645 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 1646 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 1647 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 1648 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 1649 }, 1650 1651 { 1652 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1653 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1654 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 1655 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 1656 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1657 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1658 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 1659 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 1660 }, 1661 1662 { 1663 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1664 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1665 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 1666 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 1667 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 1668 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 1669 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 1670 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 1671 }, 1672 1673 { 1674 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1675 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 1676 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 1677 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1678 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 1679 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1680 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 1681 /* Data[5].ctlEdges[7].bChannel */ 0xFF 1682 }, 1683 1684 { 1685 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1686 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1687 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 1688 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 1689 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1690 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 1691 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 1692 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 1693 }, 1694 1695 { 1696 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1697 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1698 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 1699 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1700 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 1701 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1702 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1703 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1704 }, 1705 1706 { 1707 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1708 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1709 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1710 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1711 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 1712 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1713 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 1714 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 1715 } 1716 }, 1717 .ctlPowerData_5G = { 1718 { 1719 { 1720 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1721 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1722 } 1723 }, 1724 { 1725 { 1726 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1727 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1728 } 1729 }, 1730 { 1731 { 1732 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1733 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1734 } 1735 }, 1736 { 1737 { 1738 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1739 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1740 } 1741 }, 1742 { 1743 { 1744 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1745 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1746 } 1747 }, 1748 { 1749 { 1750 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1751 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1752 } 1753 }, 1754 { 1755 { 1756 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1757 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1758 } 1759 }, 1760 { 1761 { 1762 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1763 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1764 } 1765 }, 1766 { 1767 { 1768 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 1769 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1770 } 1771 }, 1772 } 1773 }; 1774 1775 1776 static const struct ar9300_eeprom ar9300_x112 = { 1777 .eepromVersion = 2, 1778 .templateVersion = 5, 1779 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 1780 .custData = {"x112-041-f0000"}, 1781 .baseEepHeader = { 1782 .regDmn = { LE16(0), LE16(0x1f) }, 1783 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1784 .opCapFlags = { 1785 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 1786 .eepMisc = 0, 1787 }, 1788 .rfSilent = 0, 1789 .blueToothOptions = 0, 1790 .deviceCap = 0, 1791 .deviceType = 5, /* takes lower byte in eeprom location */ 1792 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 1793 .params_for_tuning_caps = {0, 0}, 1794 .featureEnable = 0x0d, 1795 /* 1796 * bit0 - enable tx temp comp - disabled 1797 * bit1 - enable tx volt comp - disabled 1798 * bit2 - enable fastclock - enabled 1799 * bit3 - enable doubling - enabled 1800 * bit4 - enable internal regulator - disabled 1801 * bit5 - enable pa predistortion - disabled 1802 */ 1803 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 1804 .eepromWriteEnableGpio = 6, 1805 .wlanDisableGpio = 0, 1806 .wlanLedGpio = 8, 1807 .rxBandSelectGpio = 0xff, 1808 .txrxgain = 0x0, 1809 .swreg = 0, 1810 }, 1811 .modalHeader2G = { 1812 /* ar9300_modal_eep_header 2g */ 1813 /* 4 idle,t1,t2,b(4 bits per setting) */ 1814 .antCtrlCommon = LE32(0x110), 1815 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 1816 .antCtrlCommon2 = LE32(0x22222), 1817 1818 /* 1819 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, 1820 * rx1, rx12, b (2 bits each) 1821 */ 1822 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, 1823 1824 /* 1825 * xatten1DB[AR9300_max_chains]; 3 xatten1_db 1826 * for ar9280 (0xa20c/b20c 5:0) 1827 */ 1828 .xatten1DB = {0x1b, 0x1b, 0x1b}, 1829 1830 /* 1831 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin 1832 * for ar9280 (0xa20c/b20c 16:12 1833 */ 1834 .xatten1Margin = {0x15, 0x15, 0x15}, 1835 .tempSlope = 50, 1836 .voltSlope = 0, 1837 1838 /* 1839 * spurChans[OSPrey_eeprom_modal_sPURS]; spur 1840 * channels in usual fbin coding format 1841 */ 1842 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 1843 1844 /* 1845 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check 1846 * if the register is per chain 1847 */ 1848 .noiseFloorThreshCh = {-1, 0, 0}, 1849 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 1850 .quick_drop = 0, 1851 .xpaBiasLvl = 0, 1852 .txFrameToDataStart = 0x0e, 1853 .txFrameToPaOn = 0x0e, 1854 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1855 .antennaGain = 0, 1856 .switchSettling = 0x2c, 1857 .adcDesiredSize = -30, 1858 .txEndToXpaOff = 0, 1859 .txEndToRxOn = 0x2, 1860 .txFrameToXpaOn = 0xe, 1861 .thresh62 = 28, 1862 .papdRateMaskHt20 = LE32(0x0c80c080), 1863 .papdRateMaskHt40 = LE32(0x0080c080), 1864 .xlna_bias_strength = 0, 1865 .futureModal = { 1866 0, 0, 0, 0, 0, 0, 0, 1867 }, 1868 }, 1869 .base_ext1 = { 1870 .ant_div_control = 0, 1871 .future = {0, 0, 0}, 1872 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} 1873 }, 1874 .calFreqPier2G = { 1875 FREQ2FBIN(2412, 1), 1876 FREQ2FBIN(2437, 1), 1877 FREQ2FBIN(2472, 1), 1878 }, 1879 /* ar9300_cal_data_per_freq_op_loop 2g */ 1880 .calPierData2G = { 1881 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1882 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1883 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1884 }, 1885 .calTarget_freqbin_Cck = { 1886 FREQ2FBIN(2412, 1), 1887 FREQ2FBIN(2472, 1), 1888 }, 1889 .calTarget_freqbin_2G = { 1890 FREQ2FBIN(2412, 1), 1891 FREQ2FBIN(2437, 1), 1892 FREQ2FBIN(2472, 1) 1893 }, 1894 .calTarget_freqbin_2GHT20 = { 1895 FREQ2FBIN(2412, 1), 1896 FREQ2FBIN(2437, 1), 1897 FREQ2FBIN(2472, 1) 1898 }, 1899 .calTarget_freqbin_2GHT40 = { 1900 FREQ2FBIN(2412, 1), 1901 FREQ2FBIN(2437, 1), 1902 FREQ2FBIN(2472, 1) 1903 }, 1904 .calTargetPowerCck = { 1905 /* 1L-5L,5S,11L,11s */ 1906 { {38, 38, 38, 38} }, 1907 { {38, 38, 38, 38} }, 1908 }, 1909 .calTargetPower2G = { 1910 /* 6-24,36,48,54 */ 1911 { {38, 38, 36, 34} }, 1912 { {38, 38, 36, 34} }, 1913 { {38, 38, 34, 32} }, 1914 }, 1915 .calTargetPower2GHT20 = { 1916 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, 1917 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} }, 1918 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, 1919 }, 1920 .calTargetPower2GHT40 = { 1921 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, 1922 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} }, 1923 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, 1924 }, 1925 .ctlIndex_2G = { 1926 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 1927 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 1928 }, 1929 .ctl_freqbin_2G = { 1930 { 1931 FREQ2FBIN(2412, 1), 1932 FREQ2FBIN(2417, 1), 1933 FREQ2FBIN(2457, 1), 1934 FREQ2FBIN(2462, 1) 1935 }, 1936 { 1937 FREQ2FBIN(2412, 1), 1938 FREQ2FBIN(2417, 1), 1939 FREQ2FBIN(2462, 1), 1940 0xFF, 1941 }, 1942 1943 { 1944 FREQ2FBIN(2412, 1), 1945 FREQ2FBIN(2417, 1), 1946 FREQ2FBIN(2462, 1), 1947 0xFF, 1948 }, 1949 { 1950 FREQ2FBIN(2422, 1), 1951 FREQ2FBIN(2427, 1), 1952 FREQ2FBIN(2447, 1), 1953 FREQ2FBIN(2452, 1) 1954 }, 1955 1956 { 1957 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1958 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1959 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1960 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), 1961 }, 1962 1963 { 1964 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1965 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1966 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1967 0, 1968 }, 1969 1970 { 1971 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1972 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1973 FREQ2FBIN(2472, 1), 1974 0, 1975 }, 1976 1977 { 1978 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), 1979 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), 1980 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), 1981 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), 1982 }, 1983 1984 { 1985 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1986 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1987 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1988 }, 1989 1990 { 1991 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1992 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1993 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1994 0 1995 }, 1996 1997 { 1998 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1999 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 2000 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 2001 0 2002 }, 2003 2004 { 2005 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), 2006 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), 2007 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), 2008 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), 2009 } 2010 }, 2011 .ctlPowerData_2G = { 2012 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2014 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2015 2016 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 2017 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2018 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2019 2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2022 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2023 2024 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2027 }, 2028 .modalHeader5G = { 2029 /* 4 idle,t1,t2,b (4 bits per setting) */ 2030 .antCtrlCommon = LE32(0x110), 2031 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 2032 .antCtrlCommon2 = LE32(0x22222), 2033 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 2034 .antCtrlChain = { 2035 LE16(0x0), LE16(0x0), LE16(0x0), 2036 }, 2037 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ 2038 .xatten1DB = {0x13, 0x19, 0x17}, 2039 2040 /* 2041 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin 2042 * for merlin (0xa20c/b20c 16:12 2043 */ 2044 .xatten1Margin = {0x19, 0x19, 0x19}, 2045 .tempSlope = 70, 2046 .voltSlope = 15, 2047 /* spurChans spur channels in usual fbin coding format */ 2048 .spurChans = {0, 0, 0, 0, 0}, 2049 /* noiseFloorThreshch check if the register is per chain */ 2050 .noiseFloorThreshCh = {-1, 0, 0}, 2051 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2052 .quick_drop = 0, 2053 .xpaBiasLvl = 0, 2054 .txFrameToDataStart = 0x0e, 2055 .txFrameToPaOn = 0x0e, 2056 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2057 .antennaGain = 0, 2058 .switchSettling = 0x2d, 2059 .adcDesiredSize = -30, 2060 .txEndToXpaOff = 0, 2061 .txEndToRxOn = 0x2, 2062 .txFrameToXpaOn = 0xe, 2063 .thresh62 = 28, 2064 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2065 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2066 .xlna_bias_strength = 0, 2067 .futureModal = { 2068 0, 0, 0, 0, 0, 0, 0, 2069 }, 2070 }, 2071 .base_ext2 = { 2072 .tempSlopeLow = 72, 2073 .tempSlopeHigh = 105, 2074 .xatten1DBLow = {0x10, 0x14, 0x10}, 2075 .xatten1MarginLow = {0x19, 0x19 , 0x19}, 2076 .xatten1DBHigh = {0x1d, 0x20, 0x24}, 2077 .xatten1MarginHigh = {0x10, 0x10, 0x10} 2078 }, 2079 .calFreqPier5G = { 2080 FREQ2FBIN(5180, 0), 2081 FREQ2FBIN(5220, 0), 2082 FREQ2FBIN(5320, 0), 2083 FREQ2FBIN(5400, 0), 2084 FREQ2FBIN(5500, 0), 2085 FREQ2FBIN(5600, 0), 2086 FREQ2FBIN(5700, 0), 2087 FREQ2FBIN(5785, 0) 2088 }, 2089 .calPierData5G = { 2090 { 2091 {0, 0, 0, 0, 0}, 2092 {0, 0, 0, 0, 0}, 2093 {0, 0, 0, 0, 0}, 2094 {0, 0, 0, 0, 0}, 2095 {0, 0, 0, 0, 0}, 2096 {0, 0, 0, 0, 0}, 2097 {0, 0, 0, 0, 0}, 2098 {0, 0, 0, 0, 0}, 2099 }, 2100 { 2101 {0, 0, 0, 0, 0}, 2102 {0, 0, 0, 0, 0}, 2103 {0, 0, 0, 0, 0}, 2104 {0, 0, 0, 0, 0}, 2105 {0, 0, 0, 0, 0}, 2106 {0, 0, 0, 0, 0}, 2107 {0, 0, 0, 0, 0}, 2108 {0, 0, 0, 0, 0}, 2109 }, 2110 { 2111 {0, 0, 0, 0, 0}, 2112 {0, 0, 0, 0, 0}, 2113 {0, 0, 0, 0, 0}, 2114 {0, 0, 0, 0, 0}, 2115 {0, 0, 0, 0, 0}, 2116 {0, 0, 0, 0, 0}, 2117 {0, 0, 0, 0, 0}, 2118 {0, 0, 0, 0, 0}, 2119 }, 2120 2121 }, 2122 .calTarget_freqbin_5G = { 2123 FREQ2FBIN(5180, 0), 2124 FREQ2FBIN(5220, 0), 2125 FREQ2FBIN(5320, 0), 2126 FREQ2FBIN(5400, 0), 2127 FREQ2FBIN(5500, 0), 2128 FREQ2FBIN(5600, 0), 2129 FREQ2FBIN(5725, 0), 2130 FREQ2FBIN(5825, 0) 2131 }, 2132 .calTarget_freqbin_5GHT20 = { 2133 FREQ2FBIN(5180, 0), 2134 FREQ2FBIN(5220, 0), 2135 FREQ2FBIN(5320, 0), 2136 FREQ2FBIN(5400, 0), 2137 FREQ2FBIN(5500, 0), 2138 FREQ2FBIN(5600, 0), 2139 FREQ2FBIN(5725, 0), 2140 FREQ2FBIN(5825, 0) 2141 }, 2142 .calTarget_freqbin_5GHT40 = { 2143 FREQ2FBIN(5180, 0), 2144 FREQ2FBIN(5220, 0), 2145 FREQ2FBIN(5320, 0), 2146 FREQ2FBIN(5400, 0), 2147 FREQ2FBIN(5500, 0), 2148 FREQ2FBIN(5600, 0), 2149 FREQ2FBIN(5725, 0), 2150 FREQ2FBIN(5825, 0) 2151 }, 2152 .calTargetPower5G = { 2153 /* 6-24,36,48,54 */ 2154 { {32, 32, 28, 26} }, 2155 { {32, 32, 28, 26} }, 2156 { {32, 32, 28, 26} }, 2157 { {32, 32, 26, 24} }, 2158 { {32, 32, 26, 24} }, 2159 { {32, 32, 24, 22} }, 2160 { {30, 30, 24, 22} }, 2161 { {30, 30, 24, 22} }, 2162 }, 2163 .calTargetPower5GHT20 = { 2164 /* 2165 * 0_8_16,1-3_9-11_17-19, 2166 * 4,5,6,7,12,13,14,15,20,21,22,23 2167 */ 2168 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2169 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2170 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2171 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} }, 2172 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} }, 2173 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} }, 2174 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, 2175 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, 2176 }, 2177 .calTargetPower5GHT40 = { 2178 /* 2179 * 0_8_16,1-3_9-11_17-19, 2180 * 4,5,6,7,12,13,14,15,20,21,22,23 2181 */ 2182 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2183 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2184 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2185 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} }, 2186 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} }, 2187 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2188 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2189 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2190 }, 2191 .ctlIndex_5G = { 2192 0x10, 0x16, 0x18, 0x40, 0x46, 2193 0x48, 0x30, 0x36, 0x38 2194 }, 2195 .ctl_freqbin_5G = { 2196 { 2197 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2198 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2199 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), 2200 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2201 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), 2202 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2203 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2204 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2205 }, 2206 { 2207 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2208 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2209 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), 2210 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2211 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), 2212 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2213 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2214 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2215 }, 2216 2217 { 2218 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2219 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), 2220 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), 2221 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), 2222 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), 2223 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), 2224 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), 2225 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) 2226 }, 2227 2228 { 2229 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2230 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), 2231 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), 2232 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), 2233 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), 2234 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2235 /* Data[3].ctledges[6].bchannel */ 0xFF, 2236 /* Data[3].ctledges[7].bchannel */ 0xFF, 2237 }, 2238 2239 { 2240 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2241 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2242 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), 2243 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), 2244 /* Data[4].ctledges[4].bchannel */ 0xFF, 2245 /* Data[4].ctledges[5].bchannel */ 0xFF, 2246 /* Data[4].ctledges[6].bchannel */ 0xFF, 2247 /* Data[4].ctledges[7].bchannel */ 0xFF, 2248 }, 2249 2250 { 2251 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2252 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), 2253 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), 2254 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), 2255 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), 2256 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), 2257 /* Data[5].ctledges[6].bchannel */ 0xFF, 2258 /* Data[5].ctledges[7].bchannel */ 0xFF 2259 }, 2260 2261 { 2262 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2263 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), 2264 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), 2265 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), 2266 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), 2267 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), 2268 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), 2269 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) 2270 }, 2271 2272 { 2273 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2274 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2275 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), 2276 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2277 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), 2278 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2279 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2280 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2281 }, 2282 2283 { 2284 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2285 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), 2286 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), 2287 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), 2288 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), 2289 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), 2290 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), 2291 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) 2292 } 2293 }, 2294 .ctlPowerData_5G = { 2295 { 2296 { 2297 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2299 } 2300 }, 2301 { 2302 { 2303 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2304 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2305 } 2306 }, 2307 { 2308 { 2309 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2310 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2311 } 2312 }, 2313 { 2314 { 2315 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2317 } 2318 }, 2319 { 2320 { 2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2322 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2323 } 2324 }, 2325 { 2326 { 2327 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2328 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2329 } 2330 }, 2331 { 2332 { 2333 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2334 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2335 } 2336 }, 2337 { 2338 { 2339 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2340 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2341 } 2342 }, 2343 { 2344 { 2345 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 2346 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2347 } 2348 }, 2349 } 2350 }; 2351 2352 static const struct ar9300_eeprom ar9300_h116 = { 2353 .eepromVersion = 2, 2354 .templateVersion = 4, 2355 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 2356 .custData = {"h116-041-f0000"}, 2357 .baseEepHeader = { 2358 .regDmn = { LE16(0), LE16(0x1f) }, 2359 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ 2360 .opCapFlags = { 2361 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 2362 .eepMisc = 0, 2363 }, 2364 .rfSilent = 0, 2365 .blueToothOptions = 0, 2366 .deviceCap = 0, 2367 .deviceType = 5, /* takes lower byte in eeprom location */ 2368 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 2369 .params_for_tuning_caps = {0, 0}, 2370 .featureEnable = 0x0d, 2371 /* 2372 * bit0 - enable tx temp comp - disabled 2373 * bit1 - enable tx volt comp - disabled 2374 * bit2 - enable fastClock - enabled 2375 * bit3 - enable doubling - enabled 2376 * bit4 - enable internal regulator - disabled 2377 * bit5 - enable pa predistortion - disabled 2378 */ 2379 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 2380 .eepromWriteEnableGpio = 6, 2381 .wlanDisableGpio = 0, 2382 .wlanLedGpio = 8, 2383 .rxBandSelectGpio = 0xff, 2384 .txrxgain = 0x10, 2385 .swreg = 0, 2386 }, 2387 .modalHeader2G = { 2388 /* ar9300_modal_eep_header 2g */ 2389 /* 4 idle,t1,t2,b(4 bits per setting) */ 2390 .antCtrlCommon = LE32(0x110), 2391 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 2392 .antCtrlCommon2 = LE32(0x44444), 2393 2394 /* 2395 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 2396 * rx1, rx12, b (2 bits each) 2397 */ 2398 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, 2399 2400 /* 2401 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 2402 * for ar9280 (0xa20c/b20c 5:0) 2403 */ 2404 .xatten1DB = {0x1f, 0x1f, 0x1f}, 2405 2406 /* 2407 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 2408 * for ar9280 (0xa20c/b20c 16:12 2409 */ 2410 .xatten1Margin = {0x12, 0x12, 0x12}, 2411 .tempSlope = 25, 2412 .voltSlope = 0, 2413 2414 /* 2415 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 2416 * channels in usual fbin coding format 2417 */ 2418 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 2419 2420 /* 2421 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 2422 * if the register is per chain 2423 */ 2424 .noiseFloorThreshCh = {-1, 0, 0}, 2425 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2426 .quick_drop = 0, 2427 .xpaBiasLvl = 0, 2428 .txFrameToDataStart = 0x0e, 2429 .txFrameToPaOn = 0x0e, 2430 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2431 .antennaGain = 0, 2432 .switchSettling = 0x2c, 2433 .adcDesiredSize = -30, 2434 .txEndToXpaOff = 0, 2435 .txEndToRxOn = 0x2, 2436 .txFrameToXpaOn = 0xe, 2437 .thresh62 = 28, 2438 .papdRateMaskHt20 = LE32(0x0c80C080), 2439 .papdRateMaskHt40 = LE32(0x0080C080), 2440 .xlna_bias_strength = 0, 2441 .futureModal = { 2442 0, 0, 0, 0, 0, 0, 0, 2443 }, 2444 }, 2445 .base_ext1 = { 2446 .ant_div_control = 0, 2447 .future = {0, 0, 0}, 2448 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0} 2449 }, 2450 .calFreqPier2G = { 2451 FREQ2FBIN(2412, 1), 2452 FREQ2FBIN(2437, 1), 2453 FREQ2FBIN(2462, 1), 2454 }, 2455 /* ar9300_cal_data_per_freq_op_loop 2g */ 2456 .calPierData2G = { 2457 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2458 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2459 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2460 }, 2461 .calTarget_freqbin_Cck = { 2462 FREQ2FBIN(2412, 1), 2463 FREQ2FBIN(2472, 1), 2464 }, 2465 .calTarget_freqbin_2G = { 2466 FREQ2FBIN(2412, 1), 2467 FREQ2FBIN(2437, 1), 2468 FREQ2FBIN(2472, 1) 2469 }, 2470 .calTarget_freqbin_2GHT20 = { 2471 FREQ2FBIN(2412, 1), 2472 FREQ2FBIN(2437, 1), 2473 FREQ2FBIN(2472, 1) 2474 }, 2475 .calTarget_freqbin_2GHT40 = { 2476 FREQ2FBIN(2412, 1), 2477 FREQ2FBIN(2437, 1), 2478 FREQ2FBIN(2472, 1) 2479 }, 2480 .calTargetPowerCck = { 2481 /* 1L-5L,5S,11L,11S */ 2482 { {34, 34, 34, 34} }, 2483 { {34, 34, 34, 34} }, 2484 }, 2485 .calTargetPower2G = { 2486 /* 6-24,36,48,54 */ 2487 { {34, 34, 32, 32} }, 2488 { {34, 34, 32, 32} }, 2489 { {34, 34, 32, 32} }, 2490 }, 2491 .calTargetPower2GHT20 = { 2492 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2493 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2494 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2495 }, 2496 .calTargetPower2GHT40 = { 2497 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2498 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2499 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2500 }, 2501 .ctlIndex_2G = { 2502 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 2503 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 2504 }, 2505 .ctl_freqbin_2G = { 2506 { 2507 FREQ2FBIN(2412, 1), 2508 FREQ2FBIN(2417, 1), 2509 FREQ2FBIN(2457, 1), 2510 FREQ2FBIN(2462, 1) 2511 }, 2512 { 2513 FREQ2FBIN(2412, 1), 2514 FREQ2FBIN(2417, 1), 2515 FREQ2FBIN(2462, 1), 2516 0xFF, 2517 }, 2518 2519 { 2520 FREQ2FBIN(2412, 1), 2521 FREQ2FBIN(2417, 1), 2522 FREQ2FBIN(2462, 1), 2523 0xFF, 2524 }, 2525 { 2526 FREQ2FBIN(2422, 1), 2527 FREQ2FBIN(2427, 1), 2528 FREQ2FBIN(2447, 1), 2529 FREQ2FBIN(2452, 1) 2530 }, 2531 2532 { 2533 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2534 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2535 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2536 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 2537 }, 2538 2539 { 2540 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2541 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2542 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2543 0, 2544 }, 2545 2546 { 2547 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2548 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2549 FREQ2FBIN(2472, 1), 2550 0, 2551 }, 2552 2553 { 2554 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 2555 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 2556 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 2557 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 2558 }, 2559 2560 { 2561 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2562 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2563 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2564 }, 2565 2566 { 2567 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2568 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2569 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2570 0 2571 }, 2572 2573 { 2574 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2575 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2576 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2577 0 2578 }, 2579 2580 { 2581 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 2582 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 2583 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 2584 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 2585 } 2586 }, 2587 .ctlPowerData_2G = { 2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2589 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2590 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2591 2592 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 2593 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2594 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2595 2596 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2599 2600 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2601 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2603 }, 2604 .modalHeader5G = { 2605 /* 4 idle,t1,t2,b (4 bits per setting) */ 2606 .antCtrlCommon = LE32(0x220), 2607 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 2608 .antCtrlCommon2 = LE32(0x44444), 2609 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 2610 .antCtrlChain = { 2611 LE16(0x150), LE16(0x150), LE16(0x150), 2612 }, 2613 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 2614 .xatten1DB = {0x19, 0x19, 0x19}, 2615 2616 /* 2617 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 2618 * for merlin (0xa20c/b20c 16:12 2619 */ 2620 .xatten1Margin = {0x14, 0x14, 0x14}, 2621 .tempSlope = 70, 2622 .voltSlope = 0, 2623 /* spurChans spur channels in usual fbin coding format */ 2624 .spurChans = {0, 0, 0, 0, 0}, 2625 /* noiseFloorThreshCh Check if the register is per chain */ 2626 .noiseFloorThreshCh = {-1, 0, 0}, 2627 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2628 .quick_drop = 0, 2629 .xpaBiasLvl = 0, 2630 .txFrameToDataStart = 0x0e, 2631 .txFrameToPaOn = 0x0e, 2632 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2633 .antennaGain = 0, 2634 .switchSettling = 0x2d, 2635 .adcDesiredSize = -30, 2636 .txEndToXpaOff = 0, 2637 .txEndToRxOn = 0x2, 2638 .txFrameToXpaOn = 0xe, 2639 .thresh62 = 28, 2640 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2641 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2642 .xlna_bias_strength = 0, 2643 .futureModal = { 2644 0, 0, 0, 0, 0, 0, 0, 2645 }, 2646 }, 2647 .base_ext2 = { 2648 .tempSlopeLow = 35, 2649 .tempSlopeHigh = 50, 2650 .xatten1DBLow = {0, 0, 0}, 2651 .xatten1MarginLow = {0, 0, 0}, 2652 .xatten1DBHigh = {0, 0, 0}, 2653 .xatten1MarginHigh = {0, 0, 0} 2654 }, 2655 .calFreqPier5G = { 2656 FREQ2FBIN(5160, 0), 2657 FREQ2FBIN(5220, 0), 2658 FREQ2FBIN(5320, 0), 2659 FREQ2FBIN(5400, 0), 2660 FREQ2FBIN(5500, 0), 2661 FREQ2FBIN(5600, 0), 2662 FREQ2FBIN(5700, 0), 2663 FREQ2FBIN(5785, 0) 2664 }, 2665 .calPierData5G = { 2666 { 2667 {0, 0, 0, 0, 0}, 2668 {0, 0, 0, 0, 0}, 2669 {0, 0, 0, 0, 0}, 2670 {0, 0, 0, 0, 0}, 2671 {0, 0, 0, 0, 0}, 2672 {0, 0, 0, 0, 0}, 2673 {0, 0, 0, 0, 0}, 2674 {0, 0, 0, 0, 0}, 2675 }, 2676 { 2677 {0, 0, 0, 0, 0}, 2678 {0, 0, 0, 0, 0}, 2679 {0, 0, 0, 0, 0}, 2680 {0, 0, 0, 0, 0}, 2681 {0, 0, 0, 0, 0}, 2682 {0, 0, 0, 0, 0}, 2683 {0, 0, 0, 0, 0}, 2684 {0, 0, 0, 0, 0}, 2685 }, 2686 { 2687 {0, 0, 0, 0, 0}, 2688 {0, 0, 0, 0, 0}, 2689 {0, 0, 0, 0, 0}, 2690 {0, 0, 0, 0, 0}, 2691 {0, 0, 0, 0, 0}, 2692 {0, 0, 0, 0, 0}, 2693 {0, 0, 0, 0, 0}, 2694 {0, 0, 0, 0, 0}, 2695 }, 2696 2697 }, 2698 .calTarget_freqbin_5G = { 2699 FREQ2FBIN(5180, 0), 2700 FREQ2FBIN(5240, 0), 2701 FREQ2FBIN(5320, 0), 2702 FREQ2FBIN(5400, 0), 2703 FREQ2FBIN(5500, 0), 2704 FREQ2FBIN(5600, 0), 2705 FREQ2FBIN(5700, 0), 2706 FREQ2FBIN(5825, 0) 2707 }, 2708 .calTarget_freqbin_5GHT20 = { 2709 FREQ2FBIN(5180, 0), 2710 FREQ2FBIN(5240, 0), 2711 FREQ2FBIN(5320, 0), 2712 FREQ2FBIN(5400, 0), 2713 FREQ2FBIN(5500, 0), 2714 FREQ2FBIN(5700, 0), 2715 FREQ2FBIN(5745, 0), 2716 FREQ2FBIN(5825, 0) 2717 }, 2718 .calTarget_freqbin_5GHT40 = { 2719 FREQ2FBIN(5180, 0), 2720 FREQ2FBIN(5240, 0), 2721 FREQ2FBIN(5320, 0), 2722 FREQ2FBIN(5400, 0), 2723 FREQ2FBIN(5500, 0), 2724 FREQ2FBIN(5700, 0), 2725 FREQ2FBIN(5745, 0), 2726 FREQ2FBIN(5825, 0) 2727 }, 2728 .calTargetPower5G = { 2729 /* 6-24,36,48,54 */ 2730 { {30, 30, 28, 24} }, 2731 { {30, 30, 28, 24} }, 2732 { {30, 30, 28, 24} }, 2733 { {30, 30, 28, 24} }, 2734 { {30, 30, 28, 24} }, 2735 { {30, 30, 28, 24} }, 2736 { {30, 30, 28, 24} }, 2737 { {30, 30, 28, 24} }, 2738 }, 2739 .calTargetPower5GHT20 = { 2740 /* 2741 * 0_8_16,1-3_9-11_17-19, 2742 * 4,5,6,7,12,13,14,15,20,21,22,23 2743 */ 2744 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, 2745 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, 2746 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, 2747 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, 2748 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, 2749 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, 2750 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, 2751 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, 2752 }, 2753 .calTargetPower5GHT40 = { 2754 /* 2755 * 0_8_16,1-3_9-11_17-19, 2756 * 4,5,6,7,12,13,14,15,20,21,22,23 2757 */ 2758 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, 2759 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, 2760 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, 2761 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, 2762 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, 2763 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, 2764 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, 2765 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, 2766 }, 2767 .ctlIndex_5G = { 2768 0x10, 0x16, 0x18, 0x40, 0x46, 2769 0x48, 0x30, 0x36, 0x38 2770 }, 2771 .ctl_freqbin_5G = { 2772 { 2773 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2774 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2775 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 2776 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2777 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 2778 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2779 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2780 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2781 }, 2782 { 2783 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2784 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2785 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 2786 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2787 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 2788 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2789 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2790 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2791 }, 2792 2793 { 2794 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2795 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 2796 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 2797 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 2798 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 2799 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 2800 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 2801 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 2802 }, 2803 2804 { 2805 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2806 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 2807 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 2808 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 2809 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 2810 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2811 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 2812 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 2813 }, 2814 2815 { 2816 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2817 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2818 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 2819 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 2820 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 2821 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 2822 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 2823 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 2824 }, 2825 2826 { 2827 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2828 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 2829 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 2830 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 2831 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 2832 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 2833 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 2834 /* Data[5].ctlEdges[7].bChannel */ 0xFF 2835 }, 2836 2837 { 2838 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2839 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 2840 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 2841 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 2842 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 2843 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 2844 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 2845 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 2846 }, 2847 2848 { 2849 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2850 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2851 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 2852 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2853 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 2854 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2855 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2856 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2857 }, 2858 2859 { 2860 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2861 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 2862 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 2863 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 2864 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 2865 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 2866 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 2867 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 2868 } 2869 }, 2870 .ctlPowerData_5G = { 2871 { 2872 { 2873 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2874 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2875 } 2876 }, 2877 { 2878 { 2879 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2880 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2881 } 2882 }, 2883 { 2884 { 2885 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2886 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2887 } 2888 }, 2889 { 2890 { 2891 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2892 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2893 } 2894 }, 2895 { 2896 { 2897 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2898 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2899 } 2900 }, 2901 { 2902 { 2903 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2904 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2905 } 2906 }, 2907 { 2908 { 2909 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2910 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2911 } 2912 }, 2913 { 2914 { 2915 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2916 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2917 } 2918 }, 2919 { 2920 { 2921 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 2922 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2923 } 2924 }, 2925 } 2926 }; 2927 2928 2929 static const struct ar9300_eeprom *ar9300_eep_templates[] = { 2930 &ar9300_default, 2931 &ar9300_x112, 2932 &ar9300_h116, 2933 &ar9300_h112, 2934 &ar9300_x113, 2935 }; 2936 2937 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) 2938 { 2939 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) 2940 int it; 2941 2942 for (it = 0; it < N_LOOP; it++) 2943 if (ar9300_eep_templates[it]->templateVersion == id) 2944 return ar9300_eep_templates[it]; 2945 return NULL; 2946 #undef N_LOOP 2947 } 2948 2949 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) 2950 { 2951 return 0; 2952 } 2953 2954 static int interpolate(int x, int xa, int xb, int ya, int yb) 2955 { 2956 int bf, factor, plus; 2957 2958 bf = 2 * (yb - ya) * (x - xa) / (xb - xa); 2959 factor = bf / 2; 2960 plus = bf % 2; 2961 return ya + factor + plus; 2962 } 2963 2964 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, 2965 enum eeprom_param param) 2966 { 2967 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 2968 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 2969 2970 switch (param) { 2971 case EEP_MAC_LSW: 2972 return get_unaligned_be16(eep->macAddr); 2973 case EEP_MAC_MID: 2974 return get_unaligned_be16(eep->macAddr + 2); 2975 case EEP_MAC_MSW: 2976 return get_unaligned_be16(eep->macAddr + 4); 2977 case EEP_REG_0: 2978 return le16_to_cpu(pBase->regDmn[0]); 2979 case EEP_OP_CAP: 2980 return pBase->deviceCap; 2981 case EEP_OP_MODE: 2982 return pBase->opCapFlags.opFlags; 2983 case EEP_RF_SILENT: 2984 return pBase->rfSilent; 2985 case EEP_TX_MASK: 2986 return (pBase->txrxMask >> 4) & 0xf; 2987 case EEP_RX_MASK: 2988 return pBase->txrxMask & 0xf; 2989 case EEP_PAPRD: 2990 return !!(pBase->featureEnable & BIT(5)); 2991 case EEP_CHAIN_MASK_REDUCE: 2992 return (pBase->miscConfiguration >> 0x3) & 0x1; 2993 case EEP_ANT_DIV_CTL1: 2994 return eep->base_ext1.ant_div_control; 2995 case EEP_ANTENNA_GAIN_5G: 2996 return eep->modalHeader5G.antennaGain; 2997 case EEP_ANTENNA_GAIN_2G: 2998 return eep->modalHeader2G.antennaGain; 2999 default: 3000 return 0; 3001 } 3002 } 3003 3004 static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address, 3005 u8 *buffer) 3006 { 3007 u16 val; 3008 3009 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) 3010 return false; 3011 3012 *buffer = (val >> (8 * (address % 2))) & 0xff; 3013 return true; 3014 } 3015 3016 static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address, 3017 u8 *buffer) 3018 { 3019 u16 val; 3020 3021 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) 3022 return false; 3023 3024 buffer[0] = val >> 8; 3025 buffer[1] = val & 0xff; 3026 3027 return true; 3028 } 3029 3030 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, 3031 int count) 3032 { 3033 struct ath_common *common = ath9k_hw_common(ah); 3034 int i; 3035 3036 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { 3037 ath_dbg(common, EEPROM, "eeprom address not in range\n"); 3038 return false; 3039 } 3040 3041 /* 3042 * Since we're reading the bytes in reverse order from a little-endian 3043 * word stream, an even address means we only use the lower half of 3044 * the 16-bit word at that address 3045 */ 3046 if (address % 2 == 0) { 3047 if (!ar9300_eeprom_read_byte(ah, address--, buffer++)) 3048 goto error; 3049 3050 count--; 3051 } 3052 3053 for (i = 0; i < count / 2; i++) { 3054 if (!ar9300_eeprom_read_word(ah, address, buffer)) 3055 goto error; 3056 3057 address -= 2; 3058 buffer += 2; 3059 } 3060 3061 if (count % 2) 3062 if (!ar9300_eeprom_read_byte(ah, address, buffer)) 3063 goto error; 3064 3065 return true; 3066 3067 error: 3068 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n", 3069 address); 3070 return false; 3071 } 3072 3073 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) 3074 { 3075 REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); 3076 3077 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, 3078 AR9300_OTP_STATUS_VALID, 1000)) 3079 return false; 3080 3081 *data = REG_READ(ah, AR9300_OTP_READ_DATA); 3082 return true; 3083 } 3084 3085 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, 3086 int count) 3087 { 3088 u32 data; 3089 int i; 3090 3091 for (i = 0; i < count; i++) { 3092 int offset = 8 * ((address - i) % 4); 3093 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) 3094 return false; 3095 3096 buffer[i] = (data >> offset) & 0xff; 3097 } 3098 3099 return true; 3100 } 3101 3102 3103 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, 3104 int *length, int *major, int *minor) 3105 { 3106 unsigned long value[4]; 3107 3108 value[0] = best[0]; 3109 value[1] = best[1]; 3110 value[2] = best[2]; 3111 value[3] = best[3]; 3112 *code = ((value[0] >> 5) & 0x0007); 3113 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); 3114 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); 3115 *major = (value[2] & 0x000f); 3116 *minor = (value[3] & 0x00ff); 3117 } 3118 3119 static u16 ar9300_comp_cksum(u8 *data, int dsize) 3120 { 3121 int it, checksum = 0; 3122 3123 for (it = 0; it < dsize; it++) { 3124 checksum += data[it]; 3125 checksum &= 0xffff; 3126 } 3127 3128 return checksum; 3129 } 3130 3131 static bool ar9300_uncompress_block(struct ath_hw *ah, 3132 u8 *mptr, 3133 int mdataSize, 3134 u8 *block, 3135 int size) 3136 { 3137 int it; 3138 int spot; 3139 int offset; 3140 int length; 3141 struct ath_common *common = ath9k_hw_common(ah); 3142 3143 spot = 0; 3144 3145 for (it = 0; it < size; it += (length+2)) { 3146 offset = block[it]; 3147 offset &= 0xff; 3148 spot += offset; 3149 length = block[it+1]; 3150 length &= 0xff; 3151 3152 if (length > 0 && spot >= 0 && spot+length <= mdataSize) { 3153 ath_dbg(common, EEPROM, 3154 "Restore at %d: spot=%d offset=%d length=%d\n", 3155 it, spot, offset, length); 3156 memcpy(&mptr[spot], &block[it+2], length); 3157 spot += length; 3158 } else if (length > 0) { 3159 ath_dbg(common, EEPROM, 3160 "Bad restore at %d: spot=%d offset=%d length=%d\n", 3161 it, spot, offset, length); 3162 return false; 3163 } 3164 } 3165 return true; 3166 } 3167 3168 static int ar9300_compress_decision(struct ath_hw *ah, 3169 int it, 3170 int code, 3171 int reference, 3172 u8 *mptr, 3173 u8 *word, int length, int mdata_size) 3174 { 3175 struct ath_common *common = ath9k_hw_common(ah); 3176 const struct ar9300_eeprom *eep = NULL; 3177 3178 switch (code) { 3179 case _CompressNone: 3180 if (length != mdata_size) { 3181 ath_dbg(common, EEPROM, 3182 "EEPROM structure size mismatch memory=%d eeprom=%d\n", 3183 mdata_size, length); 3184 return -1; 3185 } 3186 memcpy(mptr, word + COMP_HDR_LEN, length); 3187 ath_dbg(common, EEPROM, 3188 "restored eeprom %d: uncompressed, length %d\n", 3189 it, length); 3190 break; 3191 case _CompressBlock: 3192 if (reference == 0) { 3193 } else { 3194 eep = ar9003_eeprom_struct_find_by_id(reference); 3195 if (eep == NULL) { 3196 ath_dbg(common, EEPROM, 3197 "can't find reference eeprom struct %d\n", 3198 reference); 3199 return -1; 3200 } 3201 memcpy(mptr, eep, mdata_size); 3202 } 3203 ath_dbg(common, EEPROM, 3204 "restore eeprom %d: block, reference %d, length %d\n", 3205 it, reference, length); 3206 ar9300_uncompress_block(ah, mptr, mdata_size, 3207 (word + COMP_HDR_LEN), length); 3208 break; 3209 default: 3210 ath_dbg(common, EEPROM, "unknown compression code %d\n", code); 3211 return -1; 3212 } 3213 return 0; 3214 } 3215 3216 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, 3217 int count); 3218 3219 static bool ar9300_check_header(void *data) 3220 { 3221 u32 *word = data; 3222 return !(*word == 0 || *word == ~0); 3223 } 3224 3225 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, 3226 int base_addr) 3227 { 3228 u8 header[4]; 3229 3230 if (!read(ah, base_addr, header, 4)) 3231 return false; 3232 3233 return ar9300_check_header(header); 3234 } 3235 3236 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, 3237 int mdata_size) 3238 { 3239 u16 *data = (u16 *) mptr; 3240 int i; 3241 3242 for (i = 0; i < mdata_size / 2; i++, data++) 3243 ath9k_hw_nvram_read(ah, i, data); 3244 3245 return 0; 3246 } 3247 /* 3248 * Read the configuration data from the eeprom. 3249 * The data can be put in any specified memory buffer. 3250 * 3251 * Returns -1 on error. 3252 * Returns address of next memory location on success. 3253 */ 3254 static int ar9300_eeprom_restore_internal(struct ath_hw *ah, 3255 u8 *mptr, int mdata_size) 3256 { 3257 #define MDEFAULT 15 3258 #define MSTATE 100 3259 int cptr; 3260 u8 *word; 3261 int code; 3262 int reference, length, major, minor; 3263 int osize; 3264 int it; 3265 u16 checksum, mchecksum; 3266 struct ath_common *common = ath9k_hw_common(ah); 3267 struct ar9300_eeprom *eep; 3268 eeprom_read_op read; 3269 3270 if (ath9k_hw_use_flash(ah)) { 3271 u8 txrx; 3272 3273 ar9300_eeprom_restore_flash(ah, mptr, mdata_size); 3274 3275 /* check if eeprom contains valid data */ 3276 eep = (struct ar9300_eeprom *) mptr; 3277 txrx = eep->baseEepHeader.txrxMask; 3278 if (txrx != 0 && txrx != 0xff) 3279 return 0; 3280 } 3281 3282 word = kzalloc(2048, GFP_KERNEL); 3283 if (!word) 3284 return -ENOMEM; 3285 3286 memcpy(mptr, &ar9300_default, mdata_size); 3287 3288 read = ar9300_read_eeprom; 3289 if (AR_SREV_9485(ah)) 3290 cptr = AR9300_BASE_ADDR_4K; 3291 else if (AR_SREV_9330(ah)) 3292 cptr = AR9300_BASE_ADDR_512; 3293 else 3294 cptr = AR9300_BASE_ADDR; 3295 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", 3296 cptr); 3297 if (ar9300_check_eeprom_header(ah, read, cptr)) 3298 goto found; 3299 3300 cptr = AR9300_BASE_ADDR_512; 3301 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", 3302 cptr); 3303 if (ar9300_check_eeprom_header(ah, read, cptr)) 3304 goto found; 3305 3306 read = ar9300_read_otp; 3307 cptr = AR9300_BASE_ADDR; 3308 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); 3309 if (ar9300_check_eeprom_header(ah, read, cptr)) 3310 goto found; 3311 3312 cptr = AR9300_BASE_ADDR_512; 3313 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); 3314 if (ar9300_check_eeprom_header(ah, read, cptr)) 3315 goto found; 3316 3317 goto fail; 3318 3319 found: 3320 ath_dbg(common, EEPROM, "Found valid EEPROM data\n"); 3321 3322 for (it = 0; it < MSTATE; it++) { 3323 if (!read(ah, cptr, word, COMP_HDR_LEN)) 3324 goto fail; 3325 3326 if (!ar9300_check_header(word)) 3327 break; 3328 3329 ar9300_comp_hdr_unpack(word, &code, &reference, 3330 &length, &major, &minor); 3331 ath_dbg(common, EEPROM, 3332 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", 3333 cptr, code, reference, length, major, minor); 3334 if ((!AR_SREV_9485(ah) && length >= 1024) || 3335 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { 3336 ath_dbg(common, EEPROM, "Skipping bad header\n"); 3337 cptr -= COMP_HDR_LEN; 3338 continue; 3339 } 3340 3341 osize = length; 3342 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3343 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); 3344 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]); 3345 ath_dbg(common, EEPROM, "checksum %x %x\n", 3346 checksum, mchecksum); 3347 if (checksum == mchecksum) { 3348 ar9300_compress_decision(ah, it, code, reference, mptr, 3349 word, length, mdata_size); 3350 } else { 3351 ath_dbg(common, EEPROM, 3352 "skipping block with bad checksum\n"); 3353 } 3354 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3355 } 3356 3357 kfree(word); 3358 return cptr; 3359 3360 fail: 3361 kfree(word); 3362 return -1; 3363 } 3364 3365 /* 3366 * Restore the configuration structure by reading the eeprom. 3367 * This function destroys any existing in-memory structure 3368 * content. 3369 */ 3370 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) 3371 { 3372 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; 3373 3374 if (ar9300_eeprom_restore_internal(ah, mptr, 3375 sizeof(struct ar9300_eeprom)) < 0) 3376 return false; 3377 3378 return true; 3379 } 3380 3381 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) 3382 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, 3383 struct ar9300_modal_eep_header *modal_hdr) 3384 { 3385 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); 3386 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); 3387 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); 3388 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); 3389 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); 3390 PR_EEP("Ant. Gain", modal_hdr->antennaGain); 3391 PR_EEP("Switch Settle", modal_hdr->switchSettling); 3392 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); 3393 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); 3394 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); 3395 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); 3396 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); 3397 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); 3398 PR_EEP("Temp Slope", modal_hdr->tempSlope); 3399 PR_EEP("Volt Slope", modal_hdr->voltSlope); 3400 PR_EEP("spur Channels0", modal_hdr->spurChans[0]); 3401 PR_EEP("spur Channels1", modal_hdr->spurChans[1]); 3402 PR_EEP("spur Channels2", modal_hdr->spurChans[2]); 3403 PR_EEP("spur Channels3", modal_hdr->spurChans[3]); 3404 PR_EEP("spur Channels4", modal_hdr->spurChans[4]); 3405 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); 3406 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); 3407 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); 3408 PR_EEP("Quick Drop", modal_hdr->quick_drop); 3409 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); 3410 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); 3411 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); 3412 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); 3413 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); 3414 PR_EEP("txClip", modal_hdr->txClip); 3415 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); 3416 3417 return len; 3418 } 3419 3420 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 3421 u8 *buf, u32 len, u32 size) 3422 { 3423 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3424 struct ar9300_base_eep_hdr *pBase; 3425 3426 if (!dump_base_hdr) { 3427 len += snprintf(buf + len, size - len, 3428 "%20s :\n", "2GHz modal Header"); 3429 len = ar9003_dump_modal_eeprom(buf, len, size, 3430 &eep->modalHeader2G); 3431 len += snprintf(buf + len, size - len, 3432 "%20s :\n", "5GHz modal Header"); 3433 len = ar9003_dump_modal_eeprom(buf, len, size, 3434 &eep->modalHeader5G); 3435 goto out; 3436 } 3437 3438 pBase = &eep->baseEepHeader; 3439 3440 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); 3441 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); 3442 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); 3443 PR_EEP("TX Mask", (pBase->txrxMask >> 4)); 3444 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f)); 3445 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags & 3446 AR5416_OPFLAGS_11A)); 3447 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags & 3448 AR5416_OPFLAGS_11G)); 3449 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags & 3450 AR5416_OPFLAGS_N_2G_HT20)); 3451 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags & 3452 AR5416_OPFLAGS_N_2G_HT40)); 3453 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & 3454 AR5416_OPFLAGS_N_5G_HT20)); 3455 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & 3456 AR5416_OPFLAGS_N_5G_HT40)); 3457 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01)); 3458 PR_EEP("RF Silent", pBase->rfSilent); 3459 PR_EEP("BT option", pBase->blueToothOptions); 3460 PR_EEP("Device Cap", pBase->deviceCap); 3461 PR_EEP("Device Type", pBase->deviceType); 3462 PR_EEP("Power Table Offset", pBase->pwrTableOffset); 3463 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]); 3464 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]); 3465 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); 3466 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); 3467 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); 3468 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); 3469 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); 3470 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); 3471 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); 3472 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1))); 3473 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1); 3474 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio); 3475 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio); 3476 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio); 3477 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio); 3478 PR_EEP("Tx Gain", pBase->txrxgain >> 4); 3479 PR_EEP("Rx Gain", pBase->txrxgain & 0xf); 3480 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); 3481 3482 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", 3483 ah->eeprom.ar9300_eep.macAddr); 3484 out: 3485 if (len > size) 3486 len = size; 3487 3488 return len; 3489 } 3490 #else 3491 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 3492 u8 *buf, u32 len, u32 size) 3493 { 3494 return 0; 3495 } 3496 #endif 3497 3498 /* XXX: review hardware docs */ 3499 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) 3500 { 3501 return ah->eeprom.ar9300_eep.eepromVersion; 3502 } 3503 3504 /* XXX: could be read from the eepromVersion, not sure yet */ 3505 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) 3506 { 3507 return 0; 3508 } 3509 3510 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, 3511 bool is2ghz) 3512 { 3513 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3514 3515 if (is2ghz) 3516 return &eep->modalHeader2G; 3517 else 3518 return &eep->modalHeader5G; 3519 } 3520 3521 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 3522 { 3523 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; 3524 3525 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3526 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3527 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) 3528 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3529 else { 3530 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3531 REG_RMW_FIELD(ah, AR_CH0_THERM, 3532 AR_CH0_THERM_XPABIASLVL_MSB, 3533 bias >> 2); 3534 REG_RMW_FIELD(ah, AR_CH0_THERM, 3535 AR_CH0_THERM_XPASHORT2GND, 1); 3536 } 3537 } 3538 3539 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) 3540 { 3541 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); 3542 } 3543 3544 3545 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) 3546 { 3547 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); 3548 } 3549 3550 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) 3551 { 3552 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); 3553 } 3554 3555 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, 3556 bool is2ghz) 3557 { 3558 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; 3559 return le16_to_cpu(val); 3560 } 3561 3562 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 3563 { 3564 struct ath9k_hw_capabilities *pCap = &ah->caps; 3565 int chain; 3566 u32 regval, value, gpio; 3567 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { 3568 AR_PHY_SWITCH_CHAIN_0, 3569 AR_PHY_SWITCH_CHAIN_1, 3570 AR_PHY_SWITCH_CHAIN_2, 3571 }; 3572 3573 if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) { 3574 if (ah->config.xlna_gpio) 3575 gpio = ah->config.xlna_gpio; 3576 else 3577 gpio = AR9300_EXT_LNA_CTL_GPIO_AR9485; 3578 3579 ath9k_hw_cfg_output(ah, gpio, 3580 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED); 3581 } 3582 3583 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); 3584 3585 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3586 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3587 AR_SWITCH_TABLE_COM_AR9462_ALL, value); 3588 } else if (AR_SREV_9550(ah)) { 3589 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3590 AR_SWITCH_TABLE_COM_AR9550_ALL, value); 3591 } else 3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3593 AR_SWITCH_TABLE_COM_ALL, value); 3594 3595 3596 /* 3597 * AR9462 defines new switch table for BT/WLAN, 3598 * here's new field name in XXX.ref for both 2G and 5G. 3599 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) 3600 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX 3601 * SWITCH_TABLE_COM_SPDT_WLAN_RX 3602 * 3603 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX 3604 * SWITCH_TABLE_COM_SPDT_WLAN_TX 3605 * 3606 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3607 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3608 */ 3609 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) { 3610 value = ar9003_switch_com_spdt_get(ah, is2ghz); 3611 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, 3612 AR_SWITCH_TABLE_COM_SPDT_ALL, value); 3613 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); 3614 } 3615 3616 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); 3617 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); 3618 3619 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { 3620 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); 3621 REG_RMW_FIELD(ah, switch_chain_reg[0], 3622 AR_SWITCH_TABLE_ALL, value); 3623 } 3624 3625 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 3626 if ((ah->rxchainmask & BIT(chain)) || 3627 (ah->txchainmask & BIT(chain))) { 3628 value = ar9003_hw_ant_ctrl_chain_get(ah, chain, 3629 is2ghz); 3630 REG_RMW_FIELD(ah, switch_chain_reg[chain], 3631 AR_SWITCH_TABLE_ALL, value); 3632 } 3633 } 3634 3635 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 3636 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); 3637 /* 3638 * main_lnaconf, alt_lnaconf, main_tb, alt_tb 3639 * are the fields present 3640 */ 3641 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3642 regval &= (~AR_ANT_DIV_CTRL_ALL); 3643 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 3644 /* enable_lnadiv */ 3645 regval &= (~AR_PHY_ANT_DIV_LNADIV); 3646 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; 3647 3648 if (AR_SREV_9565(ah)) { 3649 if (ah->shared_chain_lnadiv) { 3650 regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S); 3651 } else { 3652 regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S); 3653 regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S); 3654 } 3655 } 3656 3657 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3658 3659 /*enable fast_div */ 3660 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 3661 regval &= (~AR_FAST_DIV_ENABLE); 3662 regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; 3663 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 3664 3665 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { 3666 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3667 /* 3668 * clear bits 25-30 main_lnaconf, alt_lnaconf, 3669 * main_tb, alt_tb 3670 */ 3671 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | 3672 AR_PHY_ANT_DIV_ALT_LNACONF | 3673 AR_PHY_ANT_DIV_ALT_GAINTB | 3674 AR_PHY_ANT_DIV_MAIN_GAINTB)); 3675 /* by default use LNA1 for the main antenna */ 3676 regval |= (AR_PHY_ANT_DIV_LNA1 << 3677 AR_PHY_ANT_DIV_MAIN_LNACONF_S); 3678 regval |= (AR_PHY_ANT_DIV_LNA2 << 3679 AR_PHY_ANT_DIV_ALT_LNACONF_S); 3680 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3681 } 3682 } 3683 } 3684 3685 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3686 { 3687 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3688 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 3689 int drive_strength; 3690 unsigned long reg; 3691 3692 drive_strength = pBase->miscConfiguration & BIT(0); 3693 if (!drive_strength) 3694 return; 3695 3696 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); 3697 reg &= ~0x00ffffc0; 3698 reg |= 0x5 << 21; 3699 reg |= 0x5 << 18; 3700 reg |= 0x5 << 15; 3701 reg |= 0x5 << 12; 3702 reg |= 0x5 << 9; 3703 reg |= 0x5 << 6; 3704 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); 3705 3706 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); 3707 reg &= ~0xffffffe0; 3708 reg |= 0x5 << 29; 3709 reg |= 0x5 << 26; 3710 reg |= 0x5 << 23; 3711 reg |= 0x5 << 20; 3712 reg |= 0x5 << 17; 3713 reg |= 0x5 << 14; 3714 reg |= 0x5 << 11; 3715 reg |= 0x5 << 8; 3716 reg |= 0x5 << 5; 3717 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); 3718 3719 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); 3720 reg &= ~0xff800000; 3721 reg |= 0x5 << 29; 3722 reg |= 0x5 << 26; 3723 reg |= 0x5 << 23; 3724 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); 3725 } 3726 3727 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, 3728 struct ath9k_channel *chan) 3729 { 3730 int f[3], t[3]; 3731 u16 value; 3732 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3733 3734 if (chain >= 0 && chain < 3) { 3735 if (IS_CHAN_2GHZ(chan)) 3736 return eep->modalHeader2G.xatten1DB[chain]; 3737 else if (eep->base_ext2.xatten1DBLow[chain] != 0) { 3738 t[0] = eep->base_ext2.xatten1DBLow[chain]; 3739 f[0] = 5180; 3740 t[1] = eep->modalHeader5G.xatten1DB[chain]; 3741 f[1] = 5500; 3742 t[2] = eep->base_ext2.xatten1DBHigh[chain]; 3743 f[2] = 5785; 3744 value = ar9003_hw_power_interpolate((s32) chan->channel, 3745 f, t, 3); 3746 return value; 3747 } else 3748 return eep->modalHeader5G.xatten1DB[chain]; 3749 } 3750 3751 return 0; 3752 } 3753 3754 3755 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, 3756 struct ath9k_channel *chan) 3757 { 3758 int f[3], t[3]; 3759 u16 value; 3760 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3761 3762 if (chain >= 0 && chain < 3) { 3763 if (IS_CHAN_2GHZ(chan)) 3764 return eep->modalHeader2G.xatten1Margin[chain]; 3765 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { 3766 t[0] = eep->base_ext2.xatten1MarginLow[chain]; 3767 f[0] = 5180; 3768 t[1] = eep->modalHeader5G.xatten1Margin[chain]; 3769 f[1] = 5500; 3770 t[2] = eep->base_ext2.xatten1MarginHigh[chain]; 3771 f[2] = 5785; 3772 value = ar9003_hw_power_interpolate((s32) chan->channel, 3773 f, t, 3); 3774 return value; 3775 } else 3776 return eep->modalHeader5G.xatten1Margin[chain]; 3777 } 3778 3779 return 0; 3780 } 3781 3782 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) 3783 { 3784 int i; 3785 u16 value; 3786 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0, 3787 AR_PHY_EXT_ATTEN_CTL_1, 3788 AR_PHY_EXT_ATTEN_CTL_2, 3789 }; 3790 3791 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { 3792 value = ar9003_hw_atten_chain_get(ah, 1, chan); 3793 REG_RMW_FIELD(ah, ext_atten_reg[0], 3794 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); 3795 3796 value = ar9003_hw_atten_chain_get_margin(ah, 1, chan); 3797 REG_RMW_FIELD(ah, ext_atten_reg[0], 3798 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, 3799 value); 3800 } 3801 3802 /* Test value. if 0 then attenuation is unused. Don't load anything. */ 3803 for (i = 0; i < 3; i++) { 3804 if (ah->txchainmask & BIT(i)) { 3805 value = ar9003_hw_atten_chain_get(ah, i, chan); 3806 REG_RMW_FIELD(ah, ext_atten_reg[i], 3807 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); 3808 3809 if (AR_SREV_9485(ah) && 3810 (ar9003_hw_get_rx_gain_idx(ah) == 0) && 3811 ah->config.xatten_margin_cfg) 3812 value = 5; 3813 else 3814 value = ar9003_hw_atten_chain_get_margin(ah, i, chan); 3815 3816 REG_RMW_FIELD(ah, ext_atten_reg[i], 3817 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, 3818 value); 3819 } 3820 } 3821 } 3822 3823 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) 3824 { 3825 int timeout = 100; 3826 3827 while (pmu_set != REG_READ(ah, pmu_reg)) { 3828 if (timeout-- == 0) 3829 return false; 3830 REG_WRITE(ah, pmu_reg, pmu_set); 3831 udelay(10); 3832 } 3833 3834 return true; 3835 } 3836 3837 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 3838 { 3839 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3840 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 3841 u32 reg_val; 3842 3843 if (pBase->featureEnable & BIT(4)) { 3844 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3845 int reg_pmu_set; 3846 3847 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; 3848 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3849 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3850 return; 3851 3852 if (AR_SREV_9330(ah)) { 3853 if (ah->is_clk_25mhz) { 3854 reg_pmu_set = (3 << 1) | (8 << 4) | 3855 (3 << 8) | (1 << 14) | 3856 (6 << 17) | (1 << 20) | 3857 (3 << 24); 3858 } else { 3859 reg_pmu_set = (4 << 1) | (7 << 4) | 3860 (3 << 8) | (1 << 14) | 3861 (6 << 17) | (1 << 20) | 3862 (3 << 24); 3863 } 3864 } else { 3865 reg_pmu_set = (5 << 1) | (7 << 4) | 3866 (2 << 8) | (2 << 14) | 3867 (6 << 17) | (1 << 20) | 3868 (3 << 24) | (1 << 28); 3869 } 3870 3871 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); 3872 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) 3873 return; 3874 3875 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) 3876 | (4 << 26); 3877 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3878 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3879 return; 3880 3881 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) 3882 | (1 << 21); 3883 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3884 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3885 return; 3886 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3887 reg_val = le32_to_cpu(pBase->swreg); 3888 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3889 } else { 3890 /* Internal regulator is ON. Write swreg register. */ 3891 reg_val = le32_to_cpu(pBase->swreg); 3892 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3893 REG_READ(ah, AR_RTC_REG_CONTROL1) & 3894 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); 3895 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); 3896 /* Set REG_CONTROL1.SWREG_PROGRAM */ 3897 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3898 REG_READ(ah, 3899 AR_RTC_REG_CONTROL1) | 3900 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 3901 } 3902 } else { 3903 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3904 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); 3905 while (REG_READ_FIELD(ah, AR_PHY_PMU2, 3906 AR_PHY_PMU2_PGM)) 3907 udelay(10); 3908 3909 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3910 while (!REG_READ_FIELD(ah, AR_PHY_PMU1, 3911 AR_PHY_PMU1_PWD)) 3912 udelay(10); 3913 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); 3914 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, 3915 AR_PHY_PMU2_PGM)) 3916 udelay(10); 3917 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 3918 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3919 else { 3920 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | 3921 AR_RTC_FORCE_SWREG_PRD; 3922 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); 3923 } 3924 } 3925 3926 } 3927 3928 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) 3929 { 3930 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3931 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; 3932 3933 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3934 return; 3935 3936 if (eep->baseEepHeader.featureEnable & 0x40) { 3937 tuning_caps_param &= 0x7f; 3938 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, 3939 tuning_caps_param); 3940 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC, 3941 tuning_caps_param); 3942 } 3943 } 3944 3945 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) 3946 { 3947 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3948 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 3949 int quick_drop; 3950 s32 t[3], f[3] = {5180, 5500, 5785}; 3951 3952 if (!(pBase->miscConfiguration & BIT(1))) 3953 return; 3954 3955 if (freq < 4000) 3956 quick_drop = eep->modalHeader2G.quick_drop; 3957 else { 3958 t[0] = eep->base_ext1.quick_drop_low; 3959 t[1] = eep->modalHeader5G.quick_drop; 3960 t[2] = eep->base_ext1.quick_drop_high; 3961 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3); 3962 } 3963 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); 3964 } 3965 3966 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) 3967 { 3968 u32 value; 3969 3970 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; 3971 3972 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, 3973 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value); 3974 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, 3975 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value); 3976 } 3977 3978 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) 3979 { 3980 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3981 u8 xpa_ctl; 3982 3983 if (!(eep->baseEepHeader.featureEnable & 0x80)) 3984 return; 3985 3986 if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah)) 3987 return; 3988 3989 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; 3990 if (is2ghz) 3991 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, 3992 AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl); 3993 else 3994 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, 3995 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl); 3996 } 3997 3998 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) 3999 { 4000 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4001 u8 bias; 4002 4003 if (!(eep->baseEepHeader.featureEnable & 0x40)) 4004 return; 4005 4006 if (!AR_SREV_9300(ah)) 4007 return; 4008 4009 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; 4010 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, 4011 bias & 0x3); 4012 bias >>= 2; 4013 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, 4014 bias & 0x3); 4015 bias >>= 2; 4016 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, 4017 bias & 0x3); 4018 } 4019 4020 static int ar9003_hw_get_thermometer(struct ath_hw *ah) 4021 { 4022 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4023 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 4024 int thermometer = (pBase->miscConfiguration >> 1) & 0x3; 4025 4026 return --thermometer; 4027 } 4028 4029 static void ar9003_hw_thermometer_apply(struct ath_hw *ah) 4030 { 4031 int thermometer = ar9003_hw_get_thermometer(ah); 4032 u8 therm_on = (thermometer < 0) ? 0 : 1; 4033 4034 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, 4035 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); 4036 if (ah->caps.tx_chainmask & BIT(1)) 4037 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, 4038 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); 4039 if (ah->caps.tx_chainmask & BIT(2)) 4040 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, 4041 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on); 4042 4043 therm_on = (thermometer < 0) ? 0 : (thermometer == 0); 4044 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, 4045 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); 4046 if (ah->caps.tx_chainmask & BIT(1)) { 4047 therm_on = (thermometer < 0) ? 0 : (thermometer == 1); 4048 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, 4049 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); 4050 } 4051 if (ah->caps.tx_chainmask & BIT(2)) { 4052 therm_on = (thermometer < 0) ? 0 : (thermometer == 2); 4053 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, 4054 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on); 4055 } 4056 } 4057 4058 static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) 4059 { 4060 u32 data, ko, kg; 4061 4062 if (!AR_SREV_9462_20_OR_LATER(ah)) 4063 return; 4064 4065 ar9300_otp_read_word(ah, 1, &data); 4066 ko = data & 0xff; 4067 kg = (data >> 8) & 0xff; 4068 if (ko || kg) { 4069 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, 4070 AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko); 4071 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, 4072 AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN, 4073 kg + 256); 4074 } 4075 } 4076 4077 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 4078 struct ath9k_channel *chan) 4079 { 4080 bool is2ghz = IS_CHAN_2GHZ(chan); 4081 ar9003_hw_xpa_timing_control_apply(ah, is2ghz); 4082 ar9003_hw_xpa_bias_level_apply(ah, is2ghz); 4083 ar9003_hw_ant_ctrl_apply(ah, is2ghz); 4084 ar9003_hw_drive_strength_apply(ah); 4085 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz); 4086 ar9003_hw_atten_apply(ah, chan); 4087 ar9003_hw_quick_drop_apply(ah, chan->channel); 4088 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah)) 4089 ar9003_hw_internal_regulator_apply(ah); 4090 ar9003_hw_apply_tuning_caps(ah); 4091 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); 4092 ar9003_hw_thermometer_apply(ah); 4093 ar9003_hw_thermo_cal_apply(ah); 4094 } 4095 4096 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, 4097 struct ath9k_channel *chan) 4098 { 4099 } 4100 4101 /* 4102 * Returns the interpolated y value corresponding to the specified x value 4103 * from the np ordered pairs of data (px,py). 4104 * The pairs do not have to be in any order. 4105 * If the specified x value is less than any of the px, 4106 * the returned y value is equal to the py for the lowest px. 4107 * If the specified x value is greater than any of the px, 4108 * the returned y value is equal to the py for the highest px. 4109 */ 4110 static int ar9003_hw_power_interpolate(int32_t x, 4111 int32_t *px, int32_t *py, u_int16_t np) 4112 { 4113 int ip = 0; 4114 int lx = 0, ly = 0, lhave = 0; 4115 int hx = 0, hy = 0, hhave = 0; 4116 int dx = 0; 4117 int y = 0; 4118 4119 lhave = 0; 4120 hhave = 0; 4121 4122 /* identify best lower and higher x calibration measurement */ 4123 for (ip = 0; ip < np; ip++) { 4124 dx = x - px[ip]; 4125 4126 /* this measurement is higher than our desired x */ 4127 if (dx <= 0) { 4128 if (!hhave || dx > (x - hx)) { 4129 /* new best higher x measurement */ 4130 hx = px[ip]; 4131 hy = py[ip]; 4132 hhave = 1; 4133 } 4134 } 4135 /* this measurement is lower than our desired x */ 4136 if (dx >= 0) { 4137 if (!lhave || dx < (x - lx)) { 4138 /* new best lower x measurement */ 4139 lx = px[ip]; 4140 ly = py[ip]; 4141 lhave = 1; 4142 } 4143 } 4144 } 4145 4146 /* the low x is good */ 4147 if (lhave) { 4148 /* so is the high x */ 4149 if (hhave) { 4150 /* they're the same, so just pick one */ 4151 if (hx == lx) 4152 y = ly; 4153 else /* interpolate */ 4154 y = interpolate(x, lx, hx, ly, hy); 4155 } else /* only low is good, use it */ 4156 y = ly; 4157 } else if (hhave) /* only high is good, use it */ 4158 y = hy; 4159 else /* nothing is good,this should never happen unless np=0, ???? */ 4160 y = -(1 << 30); 4161 return y; 4162 } 4163 4164 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, 4165 u16 rateIndex, u16 freq, bool is2GHz) 4166 { 4167 u16 numPiers, i; 4168 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4169 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4170 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4171 struct cal_tgt_pow_legacy *pEepromTargetPwr; 4172 u8 *pFreqBin; 4173 4174 if (is2GHz) { 4175 numPiers = AR9300_NUM_2G_20_TARGET_POWERS; 4176 pEepromTargetPwr = eep->calTargetPower2G; 4177 pFreqBin = eep->calTarget_freqbin_2G; 4178 } else { 4179 numPiers = AR9300_NUM_5G_20_TARGET_POWERS; 4180 pEepromTargetPwr = eep->calTargetPower5G; 4181 pFreqBin = eep->calTarget_freqbin_5G; 4182 } 4183 4184 /* 4185 * create array of channels and targetpower from 4186 * targetpower piers stored on eeprom 4187 */ 4188 for (i = 0; i < numPiers; i++) { 4189 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); 4190 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4191 } 4192 4193 /* interpolate to get target power for given frequency */ 4194 return (u8) ar9003_hw_power_interpolate((s32) freq, 4195 freqArray, 4196 targetPowerArray, numPiers); 4197 } 4198 4199 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, 4200 u16 rateIndex, 4201 u16 freq, bool is2GHz) 4202 { 4203 u16 numPiers, i; 4204 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4205 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4206 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4207 struct cal_tgt_pow_ht *pEepromTargetPwr; 4208 u8 *pFreqBin; 4209 4210 if (is2GHz) { 4211 numPiers = AR9300_NUM_2G_20_TARGET_POWERS; 4212 pEepromTargetPwr = eep->calTargetPower2GHT20; 4213 pFreqBin = eep->calTarget_freqbin_2GHT20; 4214 } else { 4215 numPiers = AR9300_NUM_5G_20_TARGET_POWERS; 4216 pEepromTargetPwr = eep->calTargetPower5GHT20; 4217 pFreqBin = eep->calTarget_freqbin_5GHT20; 4218 } 4219 4220 /* 4221 * create array of channels and targetpower 4222 * from targetpower piers stored on eeprom 4223 */ 4224 for (i = 0; i < numPiers; i++) { 4225 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); 4226 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4227 } 4228 4229 /* interpolate to get target power for given frequency */ 4230 return (u8) ar9003_hw_power_interpolate((s32) freq, 4231 freqArray, 4232 targetPowerArray, numPiers); 4233 } 4234 4235 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, 4236 u16 rateIndex, 4237 u16 freq, bool is2GHz) 4238 { 4239 u16 numPiers, i; 4240 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; 4241 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; 4242 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4243 struct cal_tgt_pow_ht *pEepromTargetPwr; 4244 u8 *pFreqBin; 4245 4246 if (is2GHz) { 4247 numPiers = AR9300_NUM_2G_40_TARGET_POWERS; 4248 pEepromTargetPwr = eep->calTargetPower2GHT40; 4249 pFreqBin = eep->calTarget_freqbin_2GHT40; 4250 } else { 4251 numPiers = AR9300_NUM_5G_40_TARGET_POWERS; 4252 pEepromTargetPwr = eep->calTargetPower5GHT40; 4253 pFreqBin = eep->calTarget_freqbin_5GHT40; 4254 } 4255 4256 /* 4257 * create array of channels and targetpower from 4258 * targetpower piers stored on eeprom 4259 */ 4260 for (i = 0; i < numPiers; i++) { 4261 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); 4262 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4263 } 4264 4265 /* interpolate to get target power for given frequency */ 4266 return (u8) ar9003_hw_power_interpolate((s32) freq, 4267 freqArray, 4268 targetPowerArray, numPiers); 4269 } 4270 4271 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, 4272 u16 rateIndex, u16 freq) 4273 { 4274 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; 4275 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; 4276 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; 4277 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4278 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; 4279 u8 *pFreqBin = eep->calTarget_freqbin_Cck; 4280 4281 /* 4282 * create array of channels and targetpower from 4283 * targetpower piers stored on eeprom 4284 */ 4285 for (i = 0; i < numPiers; i++) { 4286 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1); 4287 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4288 } 4289 4290 /* interpolate to get target power for given frequency */ 4291 return (u8) ar9003_hw_power_interpolate((s32) freq, 4292 freqArray, 4293 targetPowerArray, numPiers); 4294 } 4295 4296 /* Set tx power registers to array of values passed in */ 4297 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) 4298 { 4299 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 4300 /* make sure forced gain is not set */ 4301 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); 4302 4303 /* Write the OFDM power per rate set */ 4304 4305 /* 6 (LSB), 9, 12, 18 (MSB) */ 4306 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), 4307 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | 4308 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) | 4309 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | 4310 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); 4311 4312 /* 24 (LSB), 36, 48, 54 (MSB) */ 4313 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), 4314 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) | 4315 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) | 4316 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) | 4317 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); 4318 4319 /* Write the CCK power per rate set */ 4320 4321 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 4322 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), 4323 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | 4324 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | 4325 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ 4326 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); 4327 4328 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 4329 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), 4330 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) | 4331 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) | 4332 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) | 4333 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 4334 ); 4335 4336 /* Write the power for duplicated frames - HT40 */ 4337 4338 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */ 4339 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), 4340 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | 4341 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | 4342 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | 4343 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 4344 ); 4345 4346 /* Write the HT20 power per rate set */ 4347 4348 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 4349 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), 4350 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) | 4351 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) | 4352 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) | 4353 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) 4354 ); 4355 4356 /* 6 (LSB), 7, 12, 13 (MSB) */ 4357 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), 4358 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) | 4359 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) | 4360 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) | 4361 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0) 4362 ); 4363 4364 /* 14 (LSB), 15, 20, 21 */ 4365 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), 4366 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) | 4367 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) | 4368 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) | 4369 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0) 4370 ); 4371 4372 /* Mixed HT20 and HT40 rates */ 4373 4374 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 4375 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), 4376 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) | 4377 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) | 4378 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) | 4379 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) 4380 ); 4381 4382 /* 4383 * Write the HT40 power per rate set 4384 * correct PAR difference between HT40 and HT20/LEGACY 4385 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) 4386 */ 4387 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), 4388 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | 4389 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | 4390 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | 4391 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) 4392 ); 4393 4394 /* 6 (LSB), 7, 12, 13 (MSB) */ 4395 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), 4396 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) | 4397 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) | 4398 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) | 4399 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0) 4400 ); 4401 4402 /* 14 (LSB), 15, 20, 21 */ 4403 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), 4404 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) | 4405 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) | 4406 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) | 4407 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0) 4408 ); 4409 4410 return 0; 4411 #undef POW_SM 4412 } 4413 4414 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq, 4415 u8 *targetPowerValT2, 4416 bool is2GHz) 4417 { 4418 targetPowerValT2[ALL_TARGET_LEGACY_6_24] = 4419 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, 4420 is2GHz); 4421 targetPowerValT2[ALL_TARGET_LEGACY_36] = 4422 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, 4423 is2GHz); 4424 targetPowerValT2[ALL_TARGET_LEGACY_48] = 4425 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, 4426 is2GHz); 4427 targetPowerValT2[ALL_TARGET_LEGACY_54] = 4428 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, 4429 is2GHz); 4430 } 4431 4432 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq, 4433 u8 *targetPowerValT2) 4434 { 4435 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = 4436 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, 4437 freq); 4438 targetPowerValT2[ALL_TARGET_LEGACY_5S] = 4439 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); 4440 targetPowerValT2[ALL_TARGET_LEGACY_11L] = 4441 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); 4442 targetPowerValT2[ALL_TARGET_LEGACY_11S] = 4443 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); 4444 } 4445 4446 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq, 4447 u8 *targetPowerValT2, bool is2GHz) 4448 { 4449 targetPowerValT2[ALL_TARGET_HT20_0_8_16] = 4450 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, 4451 is2GHz); 4452 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = 4453 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, 4454 freq, is2GHz); 4455 targetPowerValT2[ALL_TARGET_HT20_4] = 4456 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, 4457 is2GHz); 4458 targetPowerValT2[ALL_TARGET_HT20_5] = 4459 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, 4460 is2GHz); 4461 targetPowerValT2[ALL_TARGET_HT20_6] = 4462 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, 4463 is2GHz); 4464 targetPowerValT2[ALL_TARGET_HT20_7] = 4465 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, 4466 is2GHz); 4467 targetPowerValT2[ALL_TARGET_HT20_12] = 4468 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, 4469 is2GHz); 4470 targetPowerValT2[ALL_TARGET_HT20_13] = 4471 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, 4472 is2GHz); 4473 targetPowerValT2[ALL_TARGET_HT20_14] = 4474 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, 4475 is2GHz); 4476 targetPowerValT2[ALL_TARGET_HT20_15] = 4477 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, 4478 is2GHz); 4479 targetPowerValT2[ALL_TARGET_HT20_20] = 4480 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, 4481 is2GHz); 4482 targetPowerValT2[ALL_TARGET_HT20_21] = 4483 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, 4484 is2GHz); 4485 targetPowerValT2[ALL_TARGET_HT20_22] = 4486 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, 4487 is2GHz); 4488 targetPowerValT2[ALL_TARGET_HT20_23] = 4489 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, 4490 is2GHz); 4491 } 4492 4493 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah, 4494 u16 freq, 4495 u8 *targetPowerValT2, 4496 bool is2GHz) 4497 { 4498 /* XXX: hard code for now, need to get from eeprom struct */ 4499 u8 ht40PowerIncForPdadc = 0; 4500 4501 targetPowerValT2[ALL_TARGET_HT40_0_8_16] = 4502 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, 4503 is2GHz) + ht40PowerIncForPdadc; 4504 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = 4505 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, 4506 freq, 4507 is2GHz) + ht40PowerIncForPdadc; 4508 targetPowerValT2[ALL_TARGET_HT40_4] = 4509 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, 4510 is2GHz) + ht40PowerIncForPdadc; 4511 targetPowerValT2[ALL_TARGET_HT40_5] = 4512 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, 4513 is2GHz) + ht40PowerIncForPdadc; 4514 targetPowerValT2[ALL_TARGET_HT40_6] = 4515 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, 4516 is2GHz) + ht40PowerIncForPdadc; 4517 targetPowerValT2[ALL_TARGET_HT40_7] = 4518 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, 4519 is2GHz) + ht40PowerIncForPdadc; 4520 targetPowerValT2[ALL_TARGET_HT40_12] = 4521 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, 4522 is2GHz) + ht40PowerIncForPdadc; 4523 targetPowerValT2[ALL_TARGET_HT40_13] = 4524 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, 4525 is2GHz) + ht40PowerIncForPdadc; 4526 targetPowerValT2[ALL_TARGET_HT40_14] = 4527 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, 4528 is2GHz) + ht40PowerIncForPdadc; 4529 targetPowerValT2[ALL_TARGET_HT40_15] = 4530 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, 4531 is2GHz) + ht40PowerIncForPdadc; 4532 targetPowerValT2[ALL_TARGET_HT40_20] = 4533 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, 4534 is2GHz) + ht40PowerIncForPdadc; 4535 targetPowerValT2[ALL_TARGET_HT40_21] = 4536 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, 4537 is2GHz) + ht40PowerIncForPdadc; 4538 targetPowerValT2[ALL_TARGET_HT40_22] = 4539 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, 4540 is2GHz) + ht40PowerIncForPdadc; 4541 targetPowerValT2[ALL_TARGET_HT40_23] = 4542 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, 4543 is2GHz) + ht40PowerIncForPdadc; 4544 } 4545 4546 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah, 4547 struct ath9k_channel *chan, 4548 u8 *targetPowerValT2) 4549 { 4550 bool is2GHz = IS_CHAN_2GHZ(chan); 4551 unsigned int i = 0; 4552 struct ath_common *common = ath9k_hw_common(ah); 4553 u16 freq = chan->channel; 4554 4555 if (is2GHz) 4556 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2); 4557 4558 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz); 4559 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz); 4560 4561 if (IS_CHAN_HT40(chan)) 4562 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2, 4563 is2GHz); 4564 4565 for (i = 0; i < ar9300RateSize; i++) { 4566 ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n", 4567 i, targetPowerValT2[i]); 4568 } 4569 } 4570 4571 static int ar9003_hw_cal_pier_get(struct ath_hw *ah, 4572 int mode, 4573 int ipier, 4574 int ichain, 4575 int *pfrequency, 4576 int *pcorrection, 4577 int *ptemperature, int *pvoltage) 4578 { 4579 u8 *pCalPier; 4580 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; 4581 int is2GHz; 4582 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4583 struct ath_common *common = ath9k_hw_common(ah); 4584 4585 if (ichain >= AR9300_MAX_CHAINS) { 4586 ath_dbg(common, EEPROM, 4587 "Invalid chain index, must be less than %d\n", 4588 AR9300_MAX_CHAINS); 4589 return -1; 4590 } 4591 4592 if (mode) { /* 5GHz */ 4593 if (ipier >= AR9300_NUM_5G_CAL_PIERS) { 4594 ath_dbg(common, EEPROM, 4595 "Invalid 5GHz cal pier index, must be less than %d\n", 4596 AR9300_NUM_5G_CAL_PIERS); 4597 return -1; 4598 } 4599 pCalPier = &(eep->calFreqPier5G[ipier]); 4600 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); 4601 is2GHz = 0; 4602 } else { 4603 if (ipier >= AR9300_NUM_2G_CAL_PIERS) { 4604 ath_dbg(common, EEPROM, 4605 "Invalid 2GHz cal pier index, must be less than %d\n", 4606 AR9300_NUM_2G_CAL_PIERS); 4607 return -1; 4608 } 4609 4610 pCalPier = &(eep->calFreqPier2G[ipier]); 4611 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); 4612 is2GHz = 1; 4613 } 4614 4615 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz); 4616 *pcorrection = pCalPierStruct->refPower; 4617 *ptemperature = pCalPierStruct->tempMeas; 4618 *pvoltage = pCalPierStruct->voltMeas; 4619 4620 return 0; 4621 } 4622 4623 static void ar9003_hw_power_control_override(struct ath_hw *ah, 4624 int frequency, 4625 int *correction, 4626 int *voltage, int *temperature) 4627 { 4628 int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0; 4629 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4630 int f[8], t[8], t1[3], t2[3], i; 4631 4632 REG_RMW(ah, AR_PHY_TPC_11_B0, 4633 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4634 AR_PHY_TPC_OLPC_GAIN_DELTA); 4635 if (ah->caps.tx_chainmask & BIT(1)) 4636 REG_RMW(ah, AR_PHY_TPC_11_B1, 4637 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4638 AR_PHY_TPC_OLPC_GAIN_DELTA); 4639 if (ah->caps.tx_chainmask & BIT(2)) 4640 REG_RMW(ah, AR_PHY_TPC_11_B2, 4641 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4642 AR_PHY_TPC_OLPC_GAIN_DELTA); 4643 4644 /* enable open loop power control on chip */ 4645 REG_RMW(ah, AR_PHY_TPC_6_B0, 4646 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4647 AR_PHY_TPC_6_ERROR_EST_MODE); 4648 if (ah->caps.tx_chainmask & BIT(1)) 4649 REG_RMW(ah, AR_PHY_TPC_6_B1, 4650 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4651 AR_PHY_TPC_6_ERROR_EST_MODE); 4652 if (ah->caps.tx_chainmask & BIT(2)) 4653 REG_RMW(ah, AR_PHY_TPC_6_B2, 4654 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4655 AR_PHY_TPC_6_ERROR_EST_MODE); 4656 4657 /* 4658 * enable temperature compensation 4659 * Need to use register names 4660 */ 4661 if (frequency < 4000) { 4662 temp_slope = eep->modalHeader2G.tempSlope; 4663 } else { 4664 if (AR_SREV_9550(ah)) { 4665 t[0] = eep->base_ext1.tempslopextension[2]; 4666 t1[0] = eep->base_ext1.tempslopextension[3]; 4667 t2[0] = eep->base_ext1.tempslopextension[4]; 4668 f[0] = 5180; 4669 4670 t[1] = eep->modalHeader5G.tempSlope; 4671 t1[1] = eep->base_ext1.tempslopextension[0]; 4672 t2[1] = eep->base_ext1.tempslopextension[1]; 4673 f[1] = 5500; 4674 4675 t[2] = eep->base_ext1.tempslopextension[5]; 4676 t1[2] = eep->base_ext1.tempslopextension[6]; 4677 t2[2] = eep->base_ext1.tempslopextension[7]; 4678 f[2] = 5785; 4679 4680 temp_slope = ar9003_hw_power_interpolate(frequency, 4681 f, t, 3); 4682 temp_slope1 = ar9003_hw_power_interpolate(frequency, 4683 f, t1, 3); 4684 temp_slope2 = ar9003_hw_power_interpolate(frequency, 4685 f, t2, 3); 4686 4687 goto tempslope; 4688 } 4689 4690 if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) { 4691 for (i = 0; i < 8; i++) { 4692 t[i] = eep->base_ext1.tempslopextension[i]; 4693 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0); 4694 } 4695 temp_slope = ar9003_hw_power_interpolate((s32) frequency, 4696 f, t, 8); 4697 } else if (eep->base_ext2.tempSlopeLow != 0) { 4698 t[0] = eep->base_ext2.tempSlopeLow; 4699 f[0] = 5180; 4700 t[1] = eep->modalHeader5G.tempSlope; 4701 f[1] = 5500; 4702 t[2] = eep->base_ext2.tempSlopeHigh; 4703 f[2] = 5785; 4704 temp_slope = ar9003_hw_power_interpolate((s32) frequency, 4705 f, t, 3); 4706 } else { 4707 temp_slope = eep->modalHeader5G.tempSlope; 4708 } 4709 } 4710 4711 tempslope: 4712 if (AR_SREV_9550(ah)) { 4713 /* 4714 * AR955x has tempSlope register for each chain. 4715 * Check whether temp_compensation feature is enabled or not. 4716 */ 4717 if (eep->baseEepHeader.featureEnable & 0x1) { 4718 if (frequency < 4000) { 4719 REG_RMW_FIELD(ah, AR_PHY_TPC_19, 4720 AR_PHY_TPC_19_ALPHA_THERM, 4721 eep->base_ext2.tempSlopeLow); 4722 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4723 AR_PHY_TPC_19_ALPHA_THERM, 4724 temp_slope); 4725 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, 4726 AR_PHY_TPC_19_ALPHA_THERM, 4727 eep->base_ext2.tempSlopeHigh); 4728 } else { 4729 REG_RMW_FIELD(ah, AR_PHY_TPC_19, 4730 AR_PHY_TPC_19_ALPHA_THERM, 4731 temp_slope); 4732 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4733 AR_PHY_TPC_19_ALPHA_THERM, 4734 temp_slope1); 4735 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, 4736 AR_PHY_TPC_19_ALPHA_THERM, 4737 temp_slope2); 4738 } 4739 } else { 4740 /* 4741 * If temp compensation is not enabled, 4742 * set all registers to 0. 4743 */ 4744 REG_RMW_FIELD(ah, AR_PHY_TPC_19, 4745 AR_PHY_TPC_19_ALPHA_THERM, 0); 4746 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4747 AR_PHY_TPC_19_ALPHA_THERM, 0); 4748 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, 4749 AR_PHY_TPC_19_ALPHA_THERM, 0); 4750 } 4751 } else { 4752 REG_RMW_FIELD(ah, AR_PHY_TPC_19, 4753 AR_PHY_TPC_19_ALPHA_THERM, temp_slope); 4754 } 4755 4756 if (AR_SREV_9462_20_OR_LATER(ah)) 4757 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4758 AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope); 4759 4760 4761 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, 4762 temperature[0]); 4763 } 4764 4765 /* Apply the recorded correction values. */ 4766 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) 4767 { 4768 int ichain, ipier, npier; 4769 int mode; 4770 int lfrequency[AR9300_MAX_CHAINS], 4771 lcorrection[AR9300_MAX_CHAINS], 4772 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS]; 4773 int hfrequency[AR9300_MAX_CHAINS], 4774 hcorrection[AR9300_MAX_CHAINS], 4775 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS]; 4776 int fdiff; 4777 int correction[AR9300_MAX_CHAINS], 4778 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS]; 4779 int pfrequency, pcorrection, ptemperature, pvoltage; 4780 struct ath_common *common = ath9k_hw_common(ah); 4781 4782 mode = (frequency >= 4000); 4783 if (mode) 4784 npier = AR9300_NUM_5G_CAL_PIERS; 4785 else 4786 npier = AR9300_NUM_2G_CAL_PIERS; 4787 4788 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4789 lfrequency[ichain] = 0; 4790 hfrequency[ichain] = 100000; 4791 } 4792 /* identify best lower and higher frequency calibration measurement */ 4793 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4794 for (ipier = 0; ipier < npier; ipier++) { 4795 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, 4796 &pfrequency, &pcorrection, 4797 &ptemperature, &pvoltage)) { 4798 fdiff = frequency - pfrequency; 4799 4800 /* 4801 * this measurement is higher than 4802 * our desired frequency 4803 */ 4804 if (fdiff <= 0) { 4805 if (hfrequency[ichain] <= 0 || 4806 hfrequency[ichain] >= 100000 || 4807 fdiff > 4808 (frequency - hfrequency[ichain])) { 4809 /* 4810 * new best higher 4811 * frequency measurement 4812 */ 4813 hfrequency[ichain] = pfrequency; 4814 hcorrection[ichain] = 4815 pcorrection; 4816 htemperature[ichain] = 4817 ptemperature; 4818 hvoltage[ichain] = pvoltage; 4819 } 4820 } 4821 if (fdiff >= 0) { 4822 if (lfrequency[ichain] <= 0 4823 || fdiff < 4824 (frequency - lfrequency[ichain])) { 4825 /* 4826 * new best lower 4827 * frequency measurement 4828 */ 4829 lfrequency[ichain] = pfrequency; 4830 lcorrection[ichain] = 4831 pcorrection; 4832 ltemperature[ichain] = 4833 ptemperature; 4834 lvoltage[ichain] = pvoltage; 4835 } 4836 } 4837 } 4838 } 4839 } 4840 4841 /* interpolate */ 4842 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4843 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n", 4844 ichain, frequency, lfrequency[ichain], 4845 lcorrection[ichain], hfrequency[ichain], 4846 hcorrection[ichain]); 4847 /* they're the same, so just pick one */ 4848 if (hfrequency[ichain] == lfrequency[ichain]) { 4849 correction[ichain] = lcorrection[ichain]; 4850 voltage[ichain] = lvoltage[ichain]; 4851 temperature[ichain] = ltemperature[ichain]; 4852 } 4853 /* the low frequency is good */ 4854 else if (frequency - lfrequency[ichain] < 1000) { 4855 /* so is the high frequency, interpolate */ 4856 if (hfrequency[ichain] - frequency < 1000) { 4857 4858 correction[ichain] = interpolate(frequency, 4859 lfrequency[ichain], 4860 hfrequency[ichain], 4861 lcorrection[ichain], 4862 hcorrection[ichain]); 4863 4864 temperature[ichain] = interpolate(frequency, 4865 lfrequency[ichain], 4866 hfrequency[ichain], 4867 ltemperature[ichain], 4868 htemperature[ichain]); 4869 4870 voltage[ichain] = interpolate(frequency, 4871 lfrequency[ichain], 4872 hfrequency[ichain], 4873 lvoltage[ichain], 4874 hvoltage[ichain]); 4875 } 4876 /* only low is good, use it */ 4877 else { 4878 correction[ichain] = lcorrection[ichain]; 4879 temperature[ichain] = ltemperature[ichain]; 4880 voltage[ichain] = lvoltage[ichain]; 4881 } 4882 } 4883 /* only high is good, use it */ 4884 else if (hfrequency[ichain] - frequency < 1000) { 4885 correction[ichain] = hcorrection[ichain]; 4886 temperature[ichain] = htemperature[ichain]; 4887 voltage[ichain] = hvoltage[ichain]; 4888 } else { /* nothing is good, presume 0???? */ 4889 correction[ichain] = 0; 4890 temperature[ichain] = 0; 4891 voltage[ichain] = 0; 4892 } 4893 } 4894 4895 ar9003_hw_power_control_override(ah, frequency, correction, voltage, 4896 temperature); 4897 4898 ath_dbg(common, EEPROM, 4899 "for frequency=%d, calibration correction = %d %d %d\n", 4900 frequency, correction[0], correction[1], correction[2]); 4901 4902 return 0; 4903 } 4904 4905 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, 4906 int idx, 4907 int edge, 4908 bool is2GHz) 4909 { 4910 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; 4911 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; 4912 4913 if (is2GHz) 4914 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]); 4915 else 4916 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]); 4917 } 4918 4919 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, 4920 int idx, 4921 unsigned int edge, 4922 u16 freq, 4923 bool is2GHz) 4924 { 4925 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; 4926 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; 4927 4928 u8 *ctl_freqbin = is2GHz ? 4929 &eep->ctl_freqbin_2G[idx][0] : 4930 &eep->ctl_freqbin_5G[idx][0]; 4931 4932 if (is2GHz) { 4933 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && 4934 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) 4935 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); 4936 } else { 4937 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && 4938 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) 4939 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); 4940 } 4941 4942 return MAX_RATE_POWER; 4943 } 4944 4945 /* 4946 * Find the maximum conformance test limit for the given channel and CTL info 4947 */ 4948 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, 4949 u16 freq, int idx, bool is2GHz) 4950 { 4951 u16 twiceMaxEdgePower = MAX_RATE_POWER; 4952 u8 *ctl_freqbin = is2GHz ? 4953 &eep->ctl_freqbin_2G[idx][0] : 4954 &eep->ctl_freqbin_5G[idx][0]; 4955 u16 num_edges = is2GHz ? 4956 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; 4957 unsigned int edge; 4958 4959 /* Get the edge power */ 4960 for (edge = 0; 4961 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); 4962 edge++) { 4963 /* 4964 * If there's an exact channel match or an inband flag set 4965 * on the lower channel use the given rdEdgePower 4966 */ 4967 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { 4968 twiceMaxEdgePower = 4969 ar9003_hw_get_direct_edge_power(eep, idx, 4970 edge, is2GHz); 4971 break; 4972 } else if ((edge > 0) && 4973 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], 4974 is2GHz))) { 4975 twiceMaxEdgePower = 4976 ar9003_hw_get_indirect_edge_power(eep, idx, 4977 edge, freq, 4978 is2GHz); 4979 /* 4980 * Leave loop - no more affecting edges possible in 4981 * this monotonic increasing list 4982 */ 4983 break; 4984 } 4985 } 4986 return twiceMaxEdgePower; 4987 } 4988 4989 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, 4990 struct ath9k_channel *chan, 4991 u8 *pPwrArray, u16 cfgCtl, 4992 u8 antenna_reduction, 4993 u16 powerLimit) 4994 { 4995 struct ath_common *common = ath9k_hw_common(ah); 4996 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; 4997 u16 twiceMaxEdgePower; 4998 int i; 4999 u16 scaledPower = 0, minCtlPower; 5000 static const u16 ctlModesFor11a[] = { 5001 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 5002 }; 5003 static const u16 ctlModesFor11g[] = { 5004 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, 5005 CTL_11G_EXT, CTL_2GHT40 5006 }; 5007 u16 numCtlModes; 5008 const u16 *pCtlMode; 5009 u16 ctlMode, freq; 5010 struct chan_centers centers; 5011 u8 *ctlIndex; 5012 u8 ctlNum; 5013 u16 twiceMinEdgePower; 5014 bool is2ghz = IS_CHAN_2GHZ(chan); 5015 5016 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 5017 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, 5018 antenna_reduction); 5019 5020 if (is2ghz) { 5021 /* Setup for CTL modes */ 5022 /* CTL_11B, CTL_11G, CTL_2GHT20 */ 5023 numCtlModes = 5024 ARRAY_SIZE(ctlModesFor11g) - 5025 SUB_NUM_CTL_MODES_AT_2G_40; 5026 pCtlMode = ctlModesFor11g; 5027 if (IS_CHAN_HT40(chan)) 5028 /* All 2G CTL's */ 5029 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 5030 } else { 5031 /* Setup for CTL modes */ 5032 /* CTL_11A, CTL_5GHT20 */ 5033 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - 5034 SUB_NUM_CTL_MODES_AT_5G_40; 5035 pCtlMode = ctlModesFor11a; 5036 if (IS_CHAN_HT40(chan)) 5037 /* All 5G CTL's */ 5038 numCtlModes = ARRAY_SIZE(ctlModesFor11a); 5039 } 5040 5041 /* 5042 * For MIMO, need to apply regulatory caps individually across 5043 * dynamically running modes: CCK, OFDM, HT20, HT40 5044 * 5045 * The outer loop walks through each possible applicable runtime mode. 5046 * The inner loop walks through each ctlIndex entry in EEPROM. 5047 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 5048 */ 5049 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 5050 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 5051 (pCtlMode[ctlMode] == CTL_2GHT40); 5052 if (isHt40CtlMode) 5053 freq = centers.synth_center; 5054 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 5055 freq = centers.ext_center; 5056 else 5057 freq = centers.ctl_center; 5058 5059 ath_dbg(common, REGULATORY, 5060 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", 5061 ctlMode, numCtlModes, isHt40CtlMode, 5062 (pCtlMode[ctlMode] & EXT_ADDITIVE)); 5063 5064 /* walk through each CTL index stored in EEPROM */ 5065 if (is2ghz) { 5066 ctlIndex = pEepData->ctlIndex_2G; 5067 ctlNum = AR9300_NUM_CTLS_2G; 5068 } else { 5069 ctlIndex = pEepData->ctlIndex_5G; 5070 ctlNum = AR9300_NUM_CTLS_5G; 5071 } 5072 5073 twiceMaxEdgePower = MAX_RATE_POWER; 5074 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { 5075 ath_dbg(common, REGULATORY, 5076 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", 5077 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], 5078 chan->channel); 5079 5080 /* 5081 * compare test group from regulatory 5082 * channel list with test mode from pCtlMode 5083 * list 5084 */ 5085 if ((((cfgCtl & ~CTL_MODE_M) | 5086 (pCtlMode[ctlMode] & CTL_MODE_M)) == 5087 ctlIndex[i]) || 5088 (((cfgCtl & ~CTL_MODE_M) | 5089 (pCtlMode[ctlMode] & CTL_MODE_M)) == 5090 ((ctlIndex[i] & CTL_MODE_M) | 5091 SD_NO_CTL))) { 5092 twiceMinEdgePower = 5093 ar9003_hw_get_max_edge_power(pEepData, 5094 freq, i, 5095 is2ghz); 5096 5097 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) 5098 /* 5099 * Find the minimum of all CTL 5100 * edge powers that apply to 5101 * this channel 5102 */ 5103 twiceMaxEdgePower = 5104 min(twiceMaxEdgePower, 5105 twiceMinEdgePower); 5106 else { 5107 /* specific */ 5108 twiceMaxEdgePower = twiceMinEdgePower; 5109 break; 5110 } 5111 } 5112 } 5113 5114 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 5115 5116 ath_dbg(common, REGULATORY, 5117 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", 5118 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 5119 scaledPower, minCtlPower); 5120 5121 /* Apply ctl mode to correct target power set */ 5122 switch (pCtlMode[ctlMode]) { 5123 case CTL_11B: 5124 for (i = ALL_TARGET_LEGACY_1L_5L; 5125 i <= ALL_TARGET_LEGACY_11S; i++) 5126 pPwrArray[i] = (u8)min((u16)pPwrArray[i], 5127 minCtlPower); 5128 break; 5129 case CTL_11A: 5130 case CTL_11G: 5131 for (i = ALL_TARGET_LEGACY_6_24; 5132 i <= ALL_TARGET_LEGACY_54; i++) 5133 pPwrArray[i] = (u8)min((u16)pPwrArray[i], 5134 minCtlPower); 5135 break; 5136 case CTL_5GHT20: 5137 case CTL_2GHT20: 5138 for (i = ALL_TARGET_HT20_0_8_16; 5139 i <= ALL_TARGET_HT20_23; i++) { 5140 pPwrArray[i] = (u8)min((u16)pPwrArray[i], 5141 minCtlPower); 5142 if (ath9k_hw_mci_is_enabled(ah)) 5143 pPwrArray[i] = 5144 (u8)min((u16)pPwrArray[i], 5145 ar9003_mci_get_max_txpower(ah, 5146 pCtlMode[ctlMode])); 5147 } 5148 break; 5149 case CTL_5GHT40: 5150 case CTL_2GHT40: 5151 for (i = ALL_TARGET_HT40_0_8_16; 5152 i <= ALL_TARGET_HT40_23; i++) { 5153 pPwrArray[i] = (u8)min((u16)pPwrArray[i], 5154 minCtlPower); 5155 if (ath9k_hw_mci_is_enabled(ah)) 5156 pPwrArray[i] = 5157 (u8)min((u16)pPwrArray[i], 5158 ar9003_mci_get_max_txpower(ah, 5159 pCtlMode[ctlMode])); 5160 } 5161 break; 5162 default: 5163 break; 5164 } 5165 } /* end ctl mode checking */ 5166 } 5167 5168 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx) 5169 { 5170 u8 mod_idx = mcs_idx % 8; 5171 5172 if (mod_idx <= 3) 5173 return mod_idx ? (base_pwridx + 1) : base_pwridx; 5174 else 5175 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; 5176 } 5177 5178 static void ar9003_paprd_set_txpower(struct ath_hw *ah, 5179 struct ath9k_channel *chan, 5180 u8 *targetPowerValT2) 5181 { 5182 int i; 5183 5184 if (!ar9003_is_paprd_enabled(ah)) 5185 return; 5186 5187 if (IS_CHAN_HT40(chan)) 5188 i = ALL_TARGET_HT40_7; 5189 else 5190 i = ALL_TARGET_HT20_7; 5191 5192 if (IS_CHAN_2GHZ(chan)) { 5193 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && 5194 !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) { 5195 if (IS_CHAN_HT40(chan)) 5196 i = ALL_TARGET_HT40_0_8_16; 5197 else 5198 i = ALL_TARGET_HT20_0_8_16; 5199 } 5200 } 5201 5202 ah->paprd_target_power = targetPowerValT2[i]; 5203 } 5204 5205 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, 5206 struct ath9k_channel *chan, u16 cfgCtl, 5207 u8 twiceAntennaReduction, 5208 u8 powerLimit, bool test) 5209 { 5210 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 5211 struct ath_common *common = ath9k_hw_common(ah); 5212 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5213 struct ar9300_modal_eep_header *modal_hdr; 5214 u8 targetPowerValT2[ar9300RateSize]; 5215 u8 target_power_val_t2_eep[ar9300RateSize]; 5216 unsigned int i = 0, paprd_scale_factor = 0; 5217 u8 pwr_idx, min_pwridx = 0; 5218 5219 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2)); 5220 5221 /* 5222 * Get target powers from EEPROM - our baseline for TX Power 5223 */ 5224 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2); 5225 5226 if (ar9003_is_paprd_enabled(ah)) { 5227 if (IS_CHAN_2GHZ(chan)) 5228 modal_hdr = &eep->modalHeader2G; 5229 else 5230 modal_hdr = &eep->modalHeader5G; 5231 5232 ah->paprd_ratemask = 5233 le32_to_cpu(modal_hdr->papdRateMaskHt20) & 5234 AR9300_PAPRD_RATE_MASK; 5235 5236 ah->paprd_ratemask_ht40 = 5237 le32_to_cpu(modal_hdr->papdRateMaskHt40) & 5238 AR9300_PAPRD_RATE_MASK; 5239 5240 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); 5241 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 : 5242 ALL_TARGET_HT20_0_8_16; 5243 5244 if (!ah->paprd_table_write_done) { 5245 memcpy(target_power_val_t2_eep, targetPowerValT2, 5246 sizeof(targetPowerValT2)); 5247 for (i = 0; i < 24; i++) { 5248 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx); 5249 if (ah->paprd_ratemask & (1 << i)) { 5250 if (targetPowerValT2[pwr_idx] && 5251 targetPowerValT2[pwr_idx] == 5252 target_power_val_t2_eep[pwr_idx]) 5253 targetPowerValT2[pwr_idx] -= 5254 paprd_scale_factor; 5255 } 5256 } 5257 } 5258 memcpy(target_power_val_t2_eep, targetPowerValT2, 5259 sizeof(targetPowerValT2)); 5260 } 5261 5262 ar9003_hw_set_power_per_rate_table(ah, chan, 5263 targetPowerValT2, cfgCtl, 5264 twiceAntennaReduction, 5265 powerLimit); 5266 5267 if (ar9003_is_paprd_enabled(ah)) { 5268 for (i = 0; i < ar9300RateSize; i++) { 5269 if ((ah->paprd_ratemask & (1 << i)) && 5270 (abs(targetPowerValT2[i] - 5271 target_power_val_t2_eep[i]) > 5272 paprd_scale_factor)) { 5273 ah->paprd_ratemask &= ~(1 << i); 5274 ath_dbg(common, EEPROM, 5275 "paprd disabled for mcs %d\n", i); 5276 } 5277 } 5278 } 5279 5280 regulatory->max_power_level = 0; 5281 for (i = 0; i < ar9300RateSize; i++) { 5282 if (targetPowerValT2[i] > regulatory->max_power_level) 5283 regulatory->max_power_level = targetPowerValT2[i]; 5284 } 5285 5286 ath9k_hw_update_regulatory_maxpower(ah); 5287 5288 if (test) 5289 return; 5290 5291 for (i = 0; i < ar9300RateSize; i++) { 5292 ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n", 5293 i, targetPowerValT2[i]); 5294 } 5295 5296 /* Write target power array to registers */ 5297 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); 5298 ar9003_hw_calibration_apply(ah, chan->channel); 5299 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2); 5300 } 5301 5302 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, 5303 u16 i, bool is2GHz) 5304 { 5305 return AR_NO_SPUR; 5306 } 5307 5308 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) 5309 { 5310 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5311 5312 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ 5313 } 5314 5315 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) 5316 { 5317 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5318 5319 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ 5320 } 5321 5322 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) 5323 { 5324 return ar9003_modal_header(ah, is2ghz)->spurChans; 5325 } 5326 5327 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, 5328 struct ath9k_channel *chan) 5329 { 5330 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5331 5332 if (IS_CHAN_2GHZ(chan)) 5333 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20), 5334 AR9300_PAPRD_SCALE_1); 5335 else { 5336 if (chan->channel >= 5700) 5337 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20), 5338 AR9300_PAPRD_SCALE_1); 5339 else if (chan->channel >= 5400) 5340 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), 5341 AR9300_PAPRD_SCALE_2); 5342 else 5343 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), 5344 AR9300_PAPRD_SCALE_1); 5345 } 5346 } 5347 5348 const struct eeprom_ops eep_ar9300_ops = { 5349 .check_eeprom = ath9k_hw_ar9300_check_eeprom, 5350 .get_eeprom = ath9k_hw_ar9300_get_eeprom, 5351 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, 5352 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom, 5353 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, 5354 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, 5355 .set_board_values = ath9k_hw_ar9300_set_board_values, 5356 .set_addac = ath9k_hw_ar9300_set_addac, 5357 .set_txpower = ath9k_hw_ar9300_set_txpower, 5358 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel 5359 }; 5360