1 /* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef AR9002_PHY_H 17 #define AR9002_PHY_H 18 19 #define AR_PHY_TEST 0x9800 20 #define PHY_AGC_CLR 0x10000000 21 #define RFSILENT_BB 0x00002000 22 23 #define AR_PHY_TURBO 0x9804 24 #define AR_PHY_FC_TURBO_MODE 0x00000001 25 #define AR_PHY_FC_TURBO_SHORT 0x00000002 26 #define AR_PHY_FC_DYN2040_EN 0x00000004 27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 29 /* For 25 MHz channel spacing -- not used but supported by hw */ 30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 31 #define AR_PHY_FC_HT_EN 0x00000040 32 #define AR_PHY_FC_SHORT_GI_40 0x00000080 33 #define AR_PHY_FC_WALSH 0x00000100 34 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 35 #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 36 37 #define AR_PHY_TEST2 0x9808 38 39 #define AR_PHY_TIMING2 0x9810 40 #define AR_PHY_TIMING3 0x9814 41 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 42 #define AR_PHY_TIMING3_DSC_MAN_S 17 43 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 44 #define AR_PHY_TIMING3_DSC_EXP_S 13 45 46 #define AR_PHY_CHIP_ID_REV_0 0x80 47 #define AR_PHY_CHIP_ID_REV_1 0x81 48 #define AR_PHY_CHIP_ID_9160_REV_0 0xb0 49 50 #define AR_PHY_ACTIVE 0x981C 51 #define AR_PHY_ACTIVE_EN 0x00000001 52 #define AR_PHY_ACTIVE_DIS 0x00000000 53 54 #define AR_PHY_RF_CTL2 0x9824 55 #define AR_PHY_TX_END_DATA_START 0x000000FF 56 #define AR_PHY_TX_END_DATA_START_S 0 57 #define AR_PHY_TX_END_PA_ON 0x0000FF00 58 #define AR_PHY_TX_END_PA_ON_S 8 59 60 #define AR_PHY_RF_CTL3 0x9828 61 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 62 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 63 64 #define AR_PHY_ADC_CTL 0x982C 65 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 66 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 67 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 68 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 69 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 70 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 71 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 72 73 #define AR_PHY_ADC_SERIAL_CTL 0x9830 74 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 75 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 76 77 #define AR_PHY_RF_CTL4 0x9834 78 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 79 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 80 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 81 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 82 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 83 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 84 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 85 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 86 87 #define AR_PHY_TSTDAC_CONST 0x983c 88 89 #define AR_PHY_SETTLING 0x9844 90 #define AR_PHY_SETTLING_SWITCH 0x00003F80 91 #define AR_PHY_SETTLING_SWITCH_S 7 92 93 #define AR_PHY_RXGAIN 0x9848 94 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 95 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 96 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 97 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 98 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 99 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 100 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 101 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 102 103 #define AR_PHY_DESIRED_SZ 0x9850 104 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 105 #define AR_PHY_DESIRED_SZ_ADC_S 0 106 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 107 #define AR_PHY_DESIRED_SZ_PGA_S 8 108 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 109 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 110 111 #define AR_PHY_FIND_SIG 0x9858 112 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 113 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 114 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 115 #define AR_PHY_FIND_SIG_FIRPWR_S 18 116 117 #define AR_PHY_AGC_CTL1 0x985C 118 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 119 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 120 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 121 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 122 123 #define AR_PHY_CCA 0x9864 124 #define AR_PHY_MINCCA_PWR 0x0FF80000 125 #define AR_PHY_MINCCA_PWR_S 19 126 #define AR_PHY_CCA_THRESH62 0x0007F000 127 #define AR_PHY_CCA_THRESH62_S 12 128 #define AR9280_PHY_MINCCA_PWR 0x1FF00000 129 #define AR9280_PHY_MINCCA_PWR_S 20 130 #define AR9280_PHY_CCA_THRESH62 0x000FF000 131 #define AR9280_PHY_CCA_THRESH62_S 12 132 133 #define AR_PHY_SFCORR_LOW 0x986C 134 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 135 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 136 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 137 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 138 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 139 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 140 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 141 142 #define AR_PHY_SFCORR 0x9868 143 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 144 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 145 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 146 #define AR_PHY_SFCORR_M1_THRESH_S 17 147 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 148 #define AR_PHY_SFCORR_M2_THRESH_S 24 149 150 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 151 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 152 #define AR_PHY_SYNTH_CONTROL 0x9874 153 #define AR_PHY_SLEEP_SCAL 0x9878 154 155 #define AR_PHY_PLL_CTL 0x987c 156 #define AR_PHY_PLL_CTL_40 0xaa 157 #define AR_PHY_PLL_CTL_40_5413 0x04 158 #define AR_PHY_PLL_CTL_44 0xab 159 #define AR_PHY_PLL_CTL_44_2133 0xeb 160 #define AR_PHY_PLL_CTL_40_2133 0xea 161 162 #define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */ 163 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 164 #define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */ 165 #define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */ 166 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/ 167 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/ 168 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/ 169 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 170 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/ 171 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 172 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/ 173 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 174 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/ 175 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/ 176 177 #define AR_PHY_RX_DELAY 0x9914 178 #define AR_PHY_SEARCH_START_DELAY 0x9918 179 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF 180 181 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) 182 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F 183 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 184 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 185 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 186 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 187 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 188 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 189 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 190 191 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 192 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 193 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 194 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 195 196 #define AR_PHY_TIMING5 0x9924 197 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 198 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 199 200 #define AR_PHY_POWER_TX_RATE1 0x9934 201 #define AR_PHY_POWER_TX_RATE2 0x9938 202 #define AR_PHY_POWER_TX_RATE_MAX 0x993c 203 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 204 205 #define AR_PHY_FRAME_CTL 0x9944 206 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 207 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 208 209 #define AR_PHY_TXPWRADJ 0x994C 210 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 211 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 212 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 213 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 214 215 #define AR_PHY_RADAR_EXT 0x9940 216 #define AR_PHY_RADAR_EXT_ENA 0x00004000 217 218 #define AR_PHY_RADAR_0 0x9954 219 #define AR_PHY_RADAR_0_ENA 0x00000001 220 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 221 #define AR_PHY_RADAR_0_INBAND 0x0000003e 222 #define AR_PHY_RADAR_0_INBAND_S 1 223 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 224 #define AR_PHY_RADAR_0_PRSSI_S 6 225 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 226 #define AR_PHY_RADAR_0_HEIGHT_S 12 227 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 228 #define AR_PHY_RADAR_0_RRSSI_S 18 229 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 230 #define AR_PHY_RADAR_0_FIRPWR_S 24 231 232 #define AR_PHY_RADAR_1 0x9958 233 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 234 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 235 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 236 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 237 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 238 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 239 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 240 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 241 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 242 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF 243 #define AR_PHY_RADAR_1_MAXLEN_S 0 244 245 #define AR_PHY_SWITCH_CHAIN_0 0x9960 246 #define AR_PHY_SWITCH_COM 0x9964 247 248 #define AR_PHY_SIGMA_DELTA 0x996C 249 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 250 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 251 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 252 #define AR_PHY_SIGMA_DELTA_FILT2_S 3 253 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 254 #define AR_PHY_SIGMA_DELTA_FILT1_S 8 255 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 256 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 257 258 #define AR_PHY_RESTART 0x9970 259 #define AR_PHY_RESTART_DIV_GC 0x001C0000 260 #define AR_PHY_RESTART_DIV_GC_S 18 261 262 #define AR_PHY_RFBUS_REQ 0x997C 263 #define AR_PHY_RFBUS_REQ_EN 0x00000001 264 265 #define AR_PHY_TIMING7 0x9980 266 #define AR_PHY_TIMING8 0x9984 267 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 268 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 269 270 #define AR_PHY_BIN_MASK2_1 0x9988 271 #define AR_PHY_BIN_MASK2_2 0x998c 272 #define AR_PHY_BIN_MASK2_3 0x9990 273 #define AR_PHY_BIN_MASK2_4 0x9994 274 275 #define AR_PHY_BIN_MASK_1 0x9900 276 #define AR_PHY_BIN_MASK_2 0x9904 277 #define AR_PHY_BIN_MASK_3 0x9908 278 279 #define AR_PHY_MASK_CTL 0x990c 280 281 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 282 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 283 284 #define AR_PHY_TIMING9 0x9998 285 #define AR_PHY_TIMING10 0x999c 286 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 287 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 288 289 #define AR_PHY_TIMING11 0x99a0 290 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 291 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 292 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 293 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 294 295 #define AR_PHY_RX_CHAINMASK 0x99a4 296 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 297 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 298 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 299 300 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 301 #define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 302 #define AR_PHY_9285_ANT_DIV_CTL 0x01000000 303 #define AR_PHY_9285_ANT_DIV_CTL_S 24 304 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 305 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 306 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 307 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 308 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 309 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 310 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 311 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 312 #define AR_PHY_9285_ANT_DIV_LNA1 2 313 #define AR_PHY_9285_ANT_DIV_LNA2 1 314 #define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 315 #define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 316 #define AR_PHY_9285_ANT_DIV_GAINTB_0 0 317 #define AR_PHY_9285_ANT_DIV_GAINTB_1 1 318 319 #define AR_PHY_EXT_CCA0 0x99b8 320 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 321 #define AR_PHY_EXT_CCA0_THRESH62_S 0 322 323 #define AR_PHY_EXT_CCA 0x99bc 324 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 325 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 326 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 327 #define AR_PHY_EXT_CCA_THRESH62_S 16 328 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000 329 #define AR_PHY_EXT_MINCCA_PWR_S 23 330 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 331 #define AR9280_PHY_EXT_MINCCA_PWR_S 16 332 333 #define AR_PHY_SFCORR_EXT 0x99c0 334 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 335 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 336 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 337 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 338 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 339 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 340 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 341 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 342 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 343 344 #define AR_PHY_HALFGI 0x99D0 345 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 346 #define AR_PHY_HALFGI_DSC_MAN_S 4 347 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F 348 #define AR_PHY_HALFGI_DSC_EXP_S 0 349 350 #define AR_PHY_CHAN_INFO_MEMORY 0x99DC 351 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 352 353 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 354 355 #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC 356 #define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 357 358 #define AR_PHY_M_SLEEP 0x99f0 359 #define AR_PHY_REFCLKDLY 0x99f4 360 #define AR_PHY_REFCLKPD 0x99f8 361 362 #define AR_PHY_CALMODE 0x99f0 363 364 #define AR_PHY_CALMODE_IQ 0x00000000 365 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 366 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 367 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 368 369 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 370 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 371 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 372 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 373 374 #define AR_PHY_CURRENT_RSSI 0x9c1c 375 #define AR9280_PHY_CURRENT_RSSI 0x9c3c 376 377 #define AR_PHY_RFBUS_GRANT 0x9C20 378 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 379 380 #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 381 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 382 383 #define AR_PHY_CHAN_INFO_GAIN 0x9CFC 384 385 #define AR_PHY_MODE 0xA200 386 #define AR_PHY_MODE_ASYNCFIFO 0x80 387 #define AR_PHY_MODE_AR2133 0x08 388 #define AR_PHY_MODE_AR5111 0x00 389 #define AR_PHY_MODE_AR5112 0x08 390 #define AR_PHY_MODE_DYNAMIC 0x04 391 #define AR_PHY_MODE_RF2GHZ 0x02 392 #define AR_PHY_MODE_RF5GHZ 0x00 393 #define AR_PHY_MODE_CCK 0x01 394 #define AR_PHY_MODE_OFDM 0x00 395 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 396 397 #define AR_PHY_CCK_TX_CTRL 0xA204 398 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 399 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 400 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 401 402 #define AR_PHY_CCK_DETECT 0xA208 403 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 404 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 405 /* [12:6] settling time for antenna switch */ 406 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 407 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 408 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 409 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 410 411 #define AR_PHY_GAIN_2GHZ 0xA20C 412 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 413 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 414 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 415 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 416 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 417 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 418 419 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 420 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 421 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 422 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 423 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 424 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 425 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 426 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 427 428 #define AR_PHY_CCK_RXCTRL4 0xA21C 429 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 430 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 431 432 #define AR_PHY_DAG_CTRLCCK 0xA228 433 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 434 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 435 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 436 437 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C 438 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 439 440 #define AR_PHY_POWER_TX_RATE3 0xA234 441 #define AR_PHY_POWER_TX_RATE4 0xA238 442 443 #define AR_PHY_SCRM_SEQ_XR 0xA23C 444 #define AR_PHY_HEADER_DETECT_XR 0xA240 445 #define AR_PHY_CHIRP_DETECTED_XR 0xA244 446 #define AR_PHY_BLUETOOTH 0xA254 447 448 #define AR_PHY_TPCRG1 0xA258 449 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 450 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 451 452 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 453 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 454 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 455 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 456 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 457 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 458 459 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 460 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 461 462 #define AR_PHY_TX_PWRCTRL4 0xa264 463 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 464 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 465 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE 466 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 467 468 #define AR_PHY_TX_PWRCTRL6_0 0xa270 469 #define AR_PHY_TX_PWRCTRL6_1 0xb270 470 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 471 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 472 473 #define AR_PHY_TX_PWRCTRL7 0xa274 474 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 475 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 476 477 #define AR_PHY_TX_PWRCTRL9 0xa27C 478 #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 479 #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 480 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 481 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 482 483 #define AR_PHY_TX_GAIN_TBL1 0xa300 484 #define AR_PHY_TX_GAIN 0x0007F000 485 #define AR_PHY_TX_GAIN_S 12 486 487 #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 488 #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 489 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 490 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 491 492 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 493 #define AR_PHY_MASK2_M_31_45 0xa3a4 494 #define AR_PHY_MASK2_M_16_30 0xa3a8 495 #define AR_PHY_MASK2_M_00_15 0xa3ac 496 #define AR_PHY_MASK2_P_15_01 0xa3b8 497 #define AR_PHY_MASK2_P_30_16 0xa3bc 498 #define AR_PHY_MASK2_P_45_31 0xa3c0 499 #define AR_PHY_MASK2_P_61_45 0xa3c4 500 #define AR_PHY_SPUR_REG 0x994c 501 502 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 503 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 504 505 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 506 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) 507 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 508 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 509 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 510 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 511 512 #define AR_PHY_PILOT_MASK_01_30 0xa3b0 513 #define AR_PHY_PILOT_MASK_31_60 0xa3b4 514 515 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4 516 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 517 518 #define AR_PHY_ANALOG_SWAP 0xa268 519 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 520 521 #define AR_PHY_TPCRG5 0xA26C 522 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 523 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 524 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 525 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 526 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 527 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 528 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 529 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 530 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 531 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 532 533 /* Carrier leak calibration control, do it after AGC calibration */ 534 #define AR_PHY_CL_CAL_CTL 0xA358 535 #define AR_PHY_CL_CAL_ENABLE 0x00000002 536 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 537 538 #define AR_PHY_POWER_TX_RATE5 0xA38C 539 #define AR_PHY_POWER_TX_RATE6 0xA390 540 541 #define AR_PHY_CAL_CHAINMASK 0xA39C 542 543 #define AR_PHY_POWER_TX_SUB 0xA3C8 544 #define AR_PHY_POWER_TX_RATE7 0xA3CC 545 #define AR_PHY_POWER_TX_RATE8 0xA3D0 546 #define AR_PHY_POWER_TX_RATE9 0xA3D4 547 548 #define AR_PHY_XPA_CFG 0xA3D8 549 #define AR_PHY_FORCE_XPA_CFG 0x000000001 550 #define AR_PHY_FORCE_XPA_CFG_S 0 551 552 #define AR_PHY_CH1_CCA 0xa864 553 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 554 #define AR_PHY_CH1_MINCCA_PWR_S 19 555 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 556 #define AR9280_PHY_CH1_MINCCA_PWR_S 20 557 558 #define AR_PHY_CH2_CCA 0xb864 559 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 560 #define AR_PHY_CH2_MINCCA_PWR_S 19 561 562 #define AR_PHY_CH1_EXT_CCA 0xa9bc 563 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 564 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 565 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 566 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 567 568 #define AR_PHY_CH2_EXT_CCA 0xb9bc 569 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 570 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 571 572 #endif 573