1b622a720SLuis R. Rodriguez /* 25b68138eSSujith Manoharan * Copyright (c) 2008-2011 Atheros Communications Inc. 3b622a720SLuis R. Rodriguez * 4b622a720SLuis R. Rodriguez * Permission to use, copy, modify, and/or distribute this software for any 5b622a720SLuis R. Rodriguez * purpose with or without fee is hereby granted, provided that the above 6b622a720SLuis R. Rodriguez * copyright notice and this permission notice appear in all copies. 7b622a720SLuis R. Rodriguez * 8b622a720SLuis R. Rodriguez * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9b622a720SLuis R. Rodriguez * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10b622a720SLuis R. Rodriguez * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11b622a720SLuis R. Rodriguez * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12b622a720SLuis R. Rodriguez * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13b622a720SLuis R. Rodriguez * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14b622a720SLuis R. Rodriguez * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15b622a720SLuis R. Rodriguez */ 16b622a720SLuis R. Rodriguez 17b622a720SLuis R. Rodriguez #include "hw.h" 18b622a720SLuis R. Rodriguez 19b622a720SLuis R. Rodriguez #define AR_BufLen 0x00000fff 20b622a720SLuis R. Rodriguez 21b622a720SLuis R. Rodriguez static void ar9002_hw_rx_enable(struct ath_hw *ah) 22b622a720SLuis R. Rodriguez { 23b622a720SLuis R. Rodriguez REG_WRITE(ah, AR_CR, AR_CR_RXE); 24b622a720SLuis R. Rodriguez } 25b622a720SLuis R. Rodriguez 26b622a720SLuis R. Rodriguez static void ar9002_hw_set_desc_link(void *ds, u32 ds_link) 27b622a720SLuis R. Rodriguez { 28b622a720SLuis R. Rodriguez ((struct ath_desc*) ds)->ds_link = ds_link; 29b622a720SLuis R. Rodriguez } 30b622a720SLuis R. Rodriguez 31b622a720SLuis R. Rodriguez static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 32b622a720SLuis R. Rodriguez { 33b622a720SLuis R. Rodriguez u32 isr = 0; 34b622a720SLuis R. Rodriguez u32 mask2 = 0; 35b622a720SLuis R. Rodriguez struct ath9k_hw_capabilities *pCap = &ah->caps; 36b622a720SLuis R. Rodriguez u32 sync_cause = 0; 37b622a720SLuis R. Rodriguez bool fatal_int = false; 38b622a720SLuis R. Rodriguez struct ath_common *common = ath9k_hw_common(ah); 39b622a720SLuis R. Rodriguez 40b622a720SLuis R. Rodriguez if (!AR_SREV_9100(ah)) { 41b622a720SLuis R. Rodriguez if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 42b622a720SLuis R. Rodriguez if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 43b622a720SLuis R. Rodriguez == AR_RTC_STATUS_ON) { 44b622a720SLuis R. Rodriguez isr = REG_READ(ah, AR_ISR); 45b622a720SLuis R. Rodriguez } 46b622a720SLuis R. Rodriguez } 47b622a720SLuis R. Rodriguez 48b622a720SLuis R. Rodriguez sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & 49b622a720SLuis R. Rodriguez AR_INTR_SYNC_DEFAULT; 50b622a720SLuis R. Rodriguez 51b622a720SLuis R. Rodriguez *masked = 0; 52b622a720SLuis R. Rodriguez 53b622a720SLuis R. Rodriguez if (!isr && !sync_cause) 54b622a720SLuis R. Rodriguez return false; 55b622a720SLuis R. Rodriguez } else { 56b622a720SLuis R. Rodriguez *masked = 0; 57b622a720SLuis R. Rodriguez isr = REG_READ(ah, AR_ISR); 58b622a720SLuis R. Rodriguez } 59b622a720SLuis R. Rodriguez 60b622a720SLuis R. Rodriguez if (isr) { 61b622a720SLuis R. Rodriguez if (isr & AR_ISR_BCNMISC) { 62b622a720SLuis R. Rodriguez u32 isr2; 63b622a720SLuis R. Rodriguez isr2 = REG_READ(ah, AR_ISR_S2); 64b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_TIM) 65b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_TIM; 66b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_DTIM) 67b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_DTIM; 68b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_DTIMSYNC) 69b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_DTIMSYNC; 70b622a720SLuis R. Rodriguez if (isr2 & (AR_ISR_S2_CABEND)) 71b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_CABEND; 72b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_GTT) 73b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_GTT; 74b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_CST) 75b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_CST; 76b622a720SLuis R. Rodriguez if (isr2 & AR_ISR_S2_TSFOOR) 77b622a720SLuis R. Rodriguez mask2 |= ATH9K_INT_TSFOOR; 78b622a720SLuis R. Rodriguez } 79b622a720SLuis R. Rodriguez 80b622a720SLuis R. Rodriguez isr = REG_READ(ah, AR_ISR_RAC); 81b622a720SLuis R. Rodriguez if (isr == 0xffffffff) { 82b622a720SLuis R. Rodriguez *masked = 0; 83b622a720SLuis R. Rodriguez return false; 84b622a720SLuis R. Rodriguez } 85b622a720SLuis R. Rodriguez 86b622a720SLuis R. Rodriguez *masked = isr & ATH9K_INT_COMMON; 87b622a720SLuis R. Rodriguez 8845684c75SFelix Fietkau if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM | 8945684c75SFelix Fietkau AR_ISR_RXOK | AR_ISR_RXERR)) 90b622a720SLuis R. Rodriguez *masked |= ATH9K_INT_RX; 91b622a720SLuis R. Rodriguez 92b622a720SLuis R. Rodriguez if (isr & 93b622a720SLuis R. Rodriguez (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 94b622a720SLuis R. Rodriguez AR_ISR_TXEOL)) { 95b622a720SLuis R. Rodriguez u32 s0_s, s1_s; 96b622a720SLuis R. Rodriguez 97b622a720SLuis R. Rodriguez *masked |= ATH9K_INT_TX; 98b622a720SLuis R. Rodriguez 99b622a720SLuis R. Rodriguez s0_s = REG_READ(ah, AR_ISR_S0_S); 100b622a720SLuis R. Rodriguez ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 101b622a720SLuis R. Rodriguez ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 102b622a720SLuis R. Rodriguez 103b622a720SLuis R. Rodriguez s1_s = REG_READ(ah, AR_ISR_S1_S); 104b622a720SLuis R. Rodriguez ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 105b622a720SLuis R. Rodriguez ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 106b622a720SLuis R. Rodriguez } 107b622a720SLuis R. Rodriguez 108b622a720SLuis R. Rodriguez if (isr & AR_ISR_RXORN) { 109226afe68SJoe Perches ath_dbg(common, ATH_DBG_INTERRUPT, 110b622a720SLuis R. Rodriguez "receive FIFO overrun interrupt\n"); 111b622a720SLuis R. Rodriguez } 112b622a720SLuis R. Rodriguez 113b622a720SLuis R. Rodriguez *masked |= mask2; 114b622a720SLuis R. Rodriguez } 115b622a720SLuis R. Rodriguez 116b622a720SLuis R. Rodriguez if (AR_SREV_9100(ah)) 117b622a720SLuis R. Rodriguez return true; 118b622a720SLuis R. Rodriguez 119b622a720SLuis R. Rodriguez if (isr & AR_ISR_GENTMR) { 120b622a720SLuis R. Rodriguez u32 s5_s; 121b622a720SLuis R. Rodriguez 122b622a720SLuis R. Rodriguez s5_s = REG_READ(ah, AR_ISR_S5_S); 123b622a720SLuis R. Rodriguez ah->intr_gen_timer_trigger = 124b622a720SLuis R. Rodriguez MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); 125b622a720SLuis R. Rodriguez 126b622a720SLuis R. Rodriguez ah->intr_gen_timer_thresh = 127b622a720SLuis R. Rodriguez MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); 128b622a720SLuis R. Rodriguez 129b622a720SLuis R. Rodriguez if (ah->intr_gen_timer_trigger) 130b622a720SLuis R. Rodriguez *masked |= ATH9K_INT_GENTIMER; 131b622a720SLuis R. Rodriguez 13245684c75SFelix Fietkau if ((s5_s & AR_ISR_S5_TIM_TIMER) && 13345684c75SFelix Fietkau !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 13445684c75SFelix Fietkau *masked |= ATH9K_INT_TIM_TIMER; 135b622a720SLuis R. Rodriguez } 136b622a720SLuis R. Rodriguez 137b622a720SLuis R. Rodriguez if (sync_cause) { 138b622a720SLuis R. Rodriguez fatal_int = 139b622a720SLuis R. Rodriguez (sync_cause & 140b622a720SLuis R. Rodriguez (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) 141b622a720SLuis R. Rodriguez ? true : false; 142b622a720SLuis R. Rodriguez 143b622a720SLuis R. Rodriguez if (fatal_int) { 144b622a720SLuis R. Rodriguez if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 145226afe68SJoe Perches ath_dbg(common, ATH_DBG_ANY, 146b622a720SLuis R. Rodriguez "received PCI FATAL interrupt\n"); 147b622a720SLuis R. Rodriguez } 148b622a720SLuis R. Rodriguez if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 149226afe68SJoe Perches ath_dbg(common, ATH_DBG_ANY, 150b622a720SLuis R. Rodriguez "received PCI PERR interrupt\n"); 151b622a720SLuis R. Rodriguez } 152b622a720SLuis R. Rodriguez *masked |= ATH9K_INT_FATAL; 153b622a720SLuis R. Rodriguez } 154b622a720SLuis R. Rodriguez if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 155226afe68SJoe Perches ath_dbg(common, ATH_DBG_INTERRUPT, 156b622a720SLuis R. Rodriguez "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 157b622a720SLuis R. Rodriguez REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 158b622a720SLuis R. Rodriguez REG_WRITE(ah, AR_RC, 0); 159b622a720SLuis R. Rodriguez *masked |= ATH9K_INT_FATAL; 160b622a720SLuis R. Rodriguez } 161b622a720SLuis R. Rodriguez if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 162226afe68SJoe Perches ath_dbg(common, ATH_DBG_INTERRUPT, 163b622a720SLuis R. Rodriguez "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 164b622a720SLuis R. Rodriguez } 165b622a720SLuis R. Rodriguez 166b622a720SLuis R. Rodriguez REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 167b622a720SLuis R. Rodriguez (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 168b622a720SLuis R. Rodriguez } 169b622a720SLuis R. Rodriguez 170b622a720SLuis R. Rodriguez return true; 171b622a720SLuis R. Rodriguez } 172b622a720SLuis R. Rodriguez 1732b63a41dSFelix Fietkau static void 1742b63a41dSFelix Fietkau ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) 1752b63a41dSFelix Fietkau { 1762b63a41dSFelix Fietkau struct ar5416_desc *ads = AR5416DESC(ds); 1772b63a41dSFelix Fietkau u32 ctl1, ctl6; 1782b63a41dSFelix Fietkau 1792b63a41dSFelix Fietkau ads->ds_txstatus0 = ads->ds_txstatus1 = 0; 1802b63a41dSFelix Fietkau ads->ds_txstatus2 = ads->ds_txstatus3 = 0; 1812b63a41dSFelix Fietkau ads->ds_txstatus4 = ads->ds_txstatus5 = 0; 1822b63a41dSFelix Fietkau ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 1832b63a41dSFelix Fietkau ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 1842b63a41dSFelix Fietkau 1852b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_link) = i->link; 1862b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_data) = i->buf_addr[0]; 1872b63a41dSFelix Fietkau 1882b63a41dSFelix Fietkau ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore); 1892b63a41dSFelix Fietkau ctl6 = SM(i->keytype, AR_EncrType); 1902b63a41dSFelix Fietkau 1912b63a41dSFelix Fietkau if (AR_SREV_9285(ah)) { 1922b63a41dSFelix Fietkau ads->ds_ctl8 = 0; 1932b63a41dSFelix Fietkau ads->ds_ctl9 = 0; 1942b63a41dSFelix Fietkau ads->ds_ctl10 = 0; 1952b63a41dSFelix Fietkau ads->ds_ctl11 = 0; 1962b63a41dSFelix Fietkau } 1972b63a41dSFelix Fietkau 1982b63a41dSFelix Fietkau if ((i->is_first || i->is_last) && 1992b63a41dSFelix Fietkau i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) { 2002b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0) 2012b63a41dSFelix Fietkau | set11nTries(i->rates, 1) 2022b63a41dSFelix Fietkau | set11nTries(i->rates, 2) 2032b63a41dSFelix Fietkau | set11nTries(i->rates, 3) 2042b63a41dSFelix Fietkau | (i->dur_update ? AR_DurUpdateEna : 0) 2052b63a41dSFelix Fietkau | SM(0, AR_BurstDur); 2062b63a41dSFelix Fietkau 2072b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0) 2082b63a41dSFelix Fietkau | set11nRate(i->rates, 1) 2092b63a41dSFelix Fietkau | set11nRate(i->rates, 2) 2102b63a41dSFelix Fietkau | set11nRate(i->rates, 3); 2112b63a41dSFelix Fietkau } else { 2122b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl2) = 0; 2132b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl3) = 0; 2142b63a41dSFelix Fietkau } 2152b63a41dSFelix Fietkau 2162b63a41dSFelix Fietkau if (!i->is_first) { 2172b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl0) = 0; 2182b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl1) = ctl1; 2192b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl6) = ctl6; 2202b63a41dSFelix Fietkau return; 2212b63a41dSFelix Fietkau } 2222b63a41dSFelix Fietkau 2232b63a41dSFelix Fietkau ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) 2242b63a41dSFelix Fietkau | SM(i->type, AR_FrameType) 2252b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 2262b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 2272b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 2282b63a41dSFelix Fietkau 2292b63a41dSFelix Fietkau switch (i->aggr) { 2302b63a41dSFelix Fietkau case AGGR_BUF_FIRST: 2312b63a41dSFelix Fietkau ctl6 |= SM(i->aggr_len, AR_AggrLen); 2322b63a41dSFelix Fietkau /* fall through */ 2332b63a41dSFelix Fietkau case AGGR_BUF_MIDDLE: 2342b63a41dSFelix Fietkau ctl1 |= AR_IsAggr | AR_MoreAggr; 2352b63a41dSFelix Fietkau ctl6 |= SM(i->ndelim, AR_PadDelim); 2362b63a41dSFelix Fietkau break; 2372b63a41dSFelix Fietkau case AGGR_BUF_LAST: 2382b63a41dSFelix Fietkau ctl1 |= AR_IsAggr; 2392b63a41dSFelix Fietkau break; 2402b63a41dSFelix Fietkau case AGGR_BUF_NONE: 2412b63a41dSFelix Fietkau break; 2422b63a41dSFelix Fietkau } 2432b63a41dSFelix Fietkau 2442b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen) 2452b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 2462b63a41dSFelix Fietkau | SM(i->txpower, AR_XmitPower) 2472b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 2482b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) 2492b63a41dSFelix Fietkau | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 2502b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 2512b63a41dSFelix Fietkau | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : 2522b63a41dSFelix Fietkau (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); 2532b63a41dSFelix Fietkau 2542b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl1) = ctl1; 2552b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl6) = ctl6; 2562b63a41dSFelix Fietkau 2572b63a41dSFelix Fietkau if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST) 2582b63a41dSFelix Fietkau return; 2592b63a41dSFelix Fietkau 2602b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0) 2612b63a41dSFelix Fietkau | set11nPktDurRTSCTS(i->rates, 1); 2622b63a41dSFelix Fietkau 2632b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2) 2642b63a41dSFelix Fietkau | set11nPktDurRTSCTS(i->rates, 3); 2652b63a41dSFelix Fietkau 2662b63a41dSFelix Fietkau ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0) 2672b63a41dSFelix Fietkau | set11nRateFlags(i->rates, 1) 2682b63a41dSFelix Fietkau | set11nRateFlags(i->rates, 2) 2692b63a41dSFelix Fietkau | set11nRateFlags(i->rates, 3) 2702b63a41dSFelix Fietkau | SM(i->rtscts_rate, AR_RTSCTSRate); 2712b63a41dSFelix Fietkau } 2722b63a41dSFelix Fietkau 273b622a720SLuis R. Rodriguez static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, 274b622a720SLuis R. Rodriguez bool is_firstseg, bool is_lastseg, 275b622a720SLuis R. Rodriguez const void *ds0, dma_addr_t buf_addr, 276b622a720SLuis R. Rodriguez unsigned int qcu) 277b622a720SLuis R. Rodriguez { 278b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 279b622a720SLuis R. Rodriguez 280b622a720SLuis R. Rodriguez ads->ds_data = buf_addr; 281b622a720SLuis R. Rodriguez 282b622a720SLuis R. Rodriguez if (is_firstseg) { 283b622a720SLuis R. Rodriguez ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore); 284b622a720SLuis R. Rodriguez } else if (is_lastseg) { 285b622a720SLuis R. Rodriguez ads->ds_ctl0 = 0; 286b622a720SLuis R. Rodriguez ads->ds_ctl1 = seglen; 287b622a720SLuis R. Rodriguez ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; 288b622a720SLuis R. Rodriguez ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; 289b622a720SLuis R. Rodriguez } else { 290b622a720SLuis R. Rodriguez ads->ds_ctl0 = 0; 291b622a720SLuis R. Rodriguez ads->ds_ctl1 = seglen | AR_TxMore; 292b622a720SLuis R. Rodriguez ads->ds_ctl2 = 0; 293b622a720SLuis R. Rodriguez ads->ds_ctl3 = 0; 294b622a720SLuis R. Rodriguez } 295b622a720SLuis R. Rodriguez ads->ds_txstatus0 = ads->ds_txstatus1 = 0; 296b622a720SLuis R. Rodriguez ads->ds_txstatus2 = ads->ds_txstatus3 = 0; 297b622a720SLuis R. Rodriguez ads->ds_txstatus4 = ads->ds_txstatus5 = 0; 298b622a720SLuis R. Rodriguez ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 299b622a720SLuis R. Rodriguez ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 300b622a720SLuis R. Rodriguez } 301b622a720SLuis R. Rodriguez 302b622a720SLuis R. Rodriguez static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, 303b622a720SLuis R. Rodriguez struct ath_tx_status *ts) 304b622a720SLuis R. Rodriguez { 305b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 306e0e9bc82SFelix Fietkau u32 status; 307b622a720SLuis R. Rodriguez 308e0e9bc82SFelix Fietkau status = ACCESS_ONCE(ads->ds_txstatus9); 309e0e9bc82SFelix Fietkau if ((status & AR_TxDone) == 0) 310b622a720SLuis R. Rodriguez return -EINPROGRESS; 311b622a720SLuis R. Rodriguez 312b622a720SLuis R. Rodriguez ts->ts_tstamp = ads->AR_SendTimestamp; 313b622a720SLuis R. Rodriguez ts->ts_status = 0; 314b622a720SLuis R. Rodriguez ts->ts_flags = 0; 315b622a720SLuis R. Rodriguez 316e0e9bc82SFelix Fietkau if (status & AR_TxOpExceeded) 317b622a720SLuis R. Rodriguez ts->ts_status |= ATH9K_TXERR_XTXOP; 318e0e9bc82SFelix Fietkau ts->tid = MS(status, AR_TxTid); 319e0e9bc82SFelix Fietkau ts->ts_rateindex = MS(status, AR_FinalTxIdx); 320e0e9bc82SFelix Fietkau ts->ts_seqnum = MS(status, AR_SeqNum); 321b622a720SLuis R. Rodriguez 322e0e9bc82SFelix Fietkau status = ACCESS_ONCE(ads->ds_txstatus0); 323e0e9bc82SFelix Fietkau ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); 324e0e9bc82SFelix Fietkau ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); 325e0e9bc82SFelix Fietkau ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); 326e0e9bc82SFelix Fietkau if (status & AR_TxBaStatus) { 327b622a720SLuis R. Rodriguez ts->ts_flags |= ATH9K_TX_BA; 328b622a720SLuis R. Rodriguez ts->ba_low = ads->AR_BaBitmapLow; 329b622a720SLuis R. Rodriguez ts->ba_high = ads->AR_BaBitmapHigh; 330b622a720SLuis R. Rodriguez } 331b622a720SLuis R. Rodriguez 332e0e9bc82SFelix Fietkau status = ACCESS_ONCE(ads->ds_txstatus1); 333e0e9bc82SFelix Fietkau if (status & AR_FrmXmitOK) 334e0e9bc82SFelix Fietkau ts->ts_status |= ATH9K_TX_ACKED; 335ff32d9cdSFelix Fietkau else { 336e0e9bc82SFelix Fietkau if (status & AR_ExcessiveRetries) 337e0e9bc82SFelix Fietkau ts->ts_status |= ATH9K_TXERR_XRETRY; 338e0e9bc82SFelix Fietkau if (status & AR_Filtered) 339e0e9bc82SFelix Fietkau ts->ts_status |= ATH9K_TXERR_FILT; 340e0e9bc82SFelix Fietkau if (status & AR_FIFOUnderrun) { 341e0e9bc82SFelix Fietkau ts->ts_status |= ATH9K_TXERR_FIFO; 342e0e9bc82SFelix Fietkau ath9k_hw_updatetxtriglevel(ah, true); 343b622a720SLuis R. Rodriguez } 344ff32d9cdSFelix Fietkau } 345e0e9bc82SFelix Fietkau if (status & AR_TxTimerExpired) 346e0e9bc82SFelix Fietkau ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 347e0e9bc82SFelix Fietkau if (status & AR_DescCfgErr) 348e0e9bc82SFelix Fietkau ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 349e0e9bc82SFelix Fietkau if (status & AR_TxDataUnderrun) { 350e0e9bc82SFelix Fietkau ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 351e0e9bc82SFelix Fietkau ath9k_hw_updatetxtriglevel(ah, true); 352e0e9bc82SFelix Fietkau } 353e0e9bc82SFelix Fietkau if (status & AR_TxDelimUnderrun) { 354e0e9bc82SFelix Fietkau ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 355e0e9bc82SFelix Fietkau ath9k_hw_updatetxtriglevel(ah, true); 356e0e9bc82SFelix Fietkau } 357e0e9bc82SFelix Fietkau ts->ts_shortretry = MS(status, AR_RTSFailCnt); 358e0e9bc82SFelix Fietkau ts->ts_longretry = MS(status, AR_DataFailCnt); 359e0e9bc82SFelix Fietkau ts->ts_virtcol = MS(status, AR_VirtRetryCnt); 360b622a720SLuis R. Rodriguez 361e0e9bc82SFelix Fietkau status = ACCESS_ONCE(ads->ds_txstatus5); 362e0e9bc82SFelix Fietkau ts->ts_rssi = MS(status, AR_TxRSSICombined); 363e0e9bc82SFelix Fietkau ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); 364e0e9bc82SFelix Fietkau ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); 365e0e9bc82SFelix Fietkau ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); 366e0e9bc82SFelix Fietkau 367b622a720SLuis R. Rodriguez ts->evm0 = ads->AR_TxEVM0; 368b622a720SLuis R. Rodriguez ts->evm1 = ads->AR_TxEVM1; 369b622a720SLuis R. Rodriguez ts->evm2 = ads->AR_TxEVM2; 370b622a720SLuis R. Rodriguez 371b622a720SLuis R. Rodriguez return 0; 372b622a720SLuis R. Rodriguez } 373b622a720SLuis R. Rodriguez 374b622a720SLuis R. Rodriguez static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds, 375b622a720SLuis R. Rodriguez u32 pktLen, enum ath9k_pkt_type type, 376a75c0629SFelix Fietkau u32 txPower, u8 keyIx, 377b622a720SLuis R. Rodriguez enum ath9k_key_type keyType, u32 flags) 378b622a720SLuis R. Rodriguez { 379b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 380b622a720SLuis R. Rodriguez 381b622a720SLuis R. Rodriguez if (txPower > 63) 382b622a720SLuis R. Rodriguez txPower = 63; 383b622a720SLuis R. Rodriguez 384b622a720SLuis R. Rodriguez ads->ds_ctl0 = (pktLen & AR_FrameLen) 385b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 386b622a720SLuis R. Rodriguez | SM(txPower, AR_XmitPower) 387b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 388b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) 389b622a720SLuis R. Rodriguez | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0); 390b622a720SLuis R. Rodriguez 391b622a720SLuis R. Rodriguez ads->ds_ctl1 = 392b622a720SLuis R. Rodriguez (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) 393b622a720SLuis R. Rodriguez | SM(type, AR_FrameType) 394b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 395b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 396b622a720SLuis R. Rodriguez | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 397b622a720SLuis R. Rodriguez 398b622a720SLuis R. Rodriguez ads->ds_ctl6 = SM(keyType, AR_EncrType); 399b622a720SLuis R. Rodriguez 400b622a720SLuis R. Rodriguez if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) { 401b622a720SLuis R. Rodriguez ads->ds_ctl8 = 0; 402b622a720SLuis R. Rodriguez ads->ds_ctl9 = 0; 403b622a720SLuis R. Rodriguez ads->ds_ctl10 = 0; 404b622a720SLuis R. Rodriguez ads->ds_ctl11 = 0; 405b622a720SLuis R. Rodriguez } 406b622a720SLuis R. Rodriguez } 407b622a720SLuis R. Rodriguez 4085519541dSFelix Fietkau static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) 4095519541dSFelix Fietkau { 4105519541dSFelix Fietkau struct ar5416_desc *ads = AR5416DESC(ds); 4115519541dSFelix Fietkau 4125519541dSFelix Fietkau if (val) 4135519541dSFelix Fietkau ads->ds_ctl0 |= AR_ClrDestMask; 4145519541dSFelix Fietkau else 4155519541dSFelix Fietkau ads->ds_ctl0 &= ~AR_ClrDestMask; 4165519541dSFelix Fietkau } 4175519541dSFelix Fietkau 418b622a720SLuis R. Rodriguez static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, 419b622a720SLuis R. Rodriguez void *lastds, 420b622a720SLuis R. Rodriguez u32 durUpdateEn, u32 rtsctsRate, 421b622a720SLuis R. Rodriguez u32 rtsctsDuration, 422b622a720SLuis R. Rodriguez struct ath9k_11n_rate_series series[], 423b622a720SLuis R. Rodriguez u32 nseries, u32 flags) 424b622a720SLuis R. Rodriguez { 425b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 426b622a720SLuis R. Rodriguez struct ar5416_desc *last_ads = AR5416DESC(lastds); 427b622a720SLuis R. Rodriguez u32 ds_ctl0; 428b622a720SLuis R. Rodriguez 429b622a720SLuis R. Rodriguez if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { 430b622a720SLuis R. Rodriguez ds_ctl0 = ads->ds_ctl0; 431b622a720SLuis R. Rodriguez 432b622a720SLuis R. Rodriguez if (flags & ATH9K_TXDESC_RTSENA) { 433b622a720SLuis R. Rodriguez ds_ctl0 &= ~AR_CTSEnable; 434b622a720SLuis R. Rodriguez ds_ctl0 |= AR_RTSEnable; 435b622a720SLuis R. Rodriguez } else { 436b622a720SLuis R. Rodriguez ds_ctl0 &= ~AR_RTSEnable; 437b622a720SLuis R. Rodriguez ds_ctl0 |= AR_CTSEnable; 438b622a720SLuis R. Rodriguez } 439b622a720SLuis R. Rodriguez 440b622a720SLuis R. Rodriguez ads->ds_ctl0 = ds_ctl0; 441b622a720SLuis R. Rodriguez } else { 442b622a720SLuis R. Rodriguez ads->ds_ctl0 = 443b622a720SLuis R. Rodriguez (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); 444b622a720SLuis R. Rodriguez } 445b622a720SLuis R. Rodriguez 446b622a720SLuis R. Rodriguez ads->ds_ctl2 = set11nTries(series, 0) 447b622a720SLuis R. Rodriguez | set11nTries(series, 1) 448b622a720SLuis R. Rodriguez | set11nTries(series, 2) 449b622a720SLuis R. Rodriguez | set11nTries(series, 3) 450b622a720SLuis R. Rodriguez | (durUpdateEn ? AR_DurUpdateEna : 0) 451b622a720SLuis R. Rodriguez | SM(0, AR_BurstDur); 452b622a720SLuis R. Rodriguez 453b622a720SLuis R. Rodriguez ads->ds_ctl3 = set11nRate(series, 0) 454b622a720SLuis R. Rodriguez | set11nRate(series, 1) 455b622a720SLuis R. Rodriguez | set11nRate(series, 2) 456b622a720SLuis R. Rodriguez | set11nRate(series, 3); 457b622a720SLuis R. Rodriguez 458b622a720SLuis R. Rodriguez ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) 459b622a720SLuis R. Rodriguez | set11nPktDurRTSCTS(series, 1); 460b622a720SLuis R. Rodriguez 461b622a720SLuis R. Rodriguez ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) 462b622a720SLuis R. Rodriguez | set11nPktDurRTSCTS(series, 3); 463b622a720SLuis R. Rodriguez 464b622a720SLuis R. Rodriguez ads->ds_ctl7 = set11nRateFlags(series, 0) 465b622a720SLuis R. Rodriguez | set11nRateFlags(series, 1) 466b622a720SLuis R. Rodriguez | set11nRateFlags(series, 2) 467b622a720SLuis R. Rodriguez | set11nRateFlags(series, 3) 468b622a720SLuis R. Rodriguez | SM(rtsctsRate, AR_RTSCTSRate); 469b622a720SLuis R. Rodriguez last_ads->ds_ctl2 = ads->ds_ctl2; 470b622a720SLuis R. Rodriguez last_ads->ds_ctl3 = ads->ds_ctl3; 471b622a720SLuis R. Rodriguez } 472b622a720SLuis R. Rodriguez 473b622a720SLuis R. Rodriguez static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, 474b622a720SLuis R. Rodriguez u32 aggrLen) 475b622a720SLuis R. Rodriguez { 476b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 477b622a720SLuis R. Rodriguez 478b622a720SLuis R. Rodriguez ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 479b622a720SLuis R. Rodriguez ads->ds_ctl6 &= ~AR_AggrLen; 480b622a720SLuis R. Rodriguez ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 481b622a720SLuis R. Rodriguez } 482b622a720SLuis R. Rodriguez 483b622a720SLuis R. Rodriguez static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, 484b622a720SLuis R. Rodriguez u32 numDelims) 485b622a720SLuis R. Rodriguez { 486b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 487b622a720SLuis R. Rodriguez unsigned int ctl6; 488b622a720SLuis R. Rodriguez 489b622a720SLuis R. Rodriguez ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 490b622a720SLuis R. Rodriguez 491b622a720SLuis R. Rodriguez ctl6 = ads->ds_ctl6; 492b622a720SLuis R. Rodriguez ctl6 &= ~AR_PadDelim; 493b622a720SLuis R. Rodriguez ctl6 |= SM(numDelims, AR_PadDelim); 494b622a720SLuis R. Rodriguez ads->ds_ctl6 = ctl6; 495b622a720SLuis R. Rodriguez } 496b622a720SLuis R. Rodriguez 497b622a720SLuis R. Rodriguez static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) 498b622a720SLuis R. Rodriguez { 499b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 500b622a720SLuis R. Rodriguez 501b622a720SLuis R. Rodriguez ads->ds_ctl1 |= AR_IsAggr; 502b622a720SLuis R. Rodriguez ads->ds_ctl1 &= ~AR_MoreAggr; 503b622a720SLuis R. Rodriguez ads->ds_ctl6 &= ~AR_PadDelim; 504b622a720SLuis R. Rodriguez } 505b622a720SLuis R. Rodriguez 506b622a720SLuis R. Rodriguez static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds) 507b622a720SLuis R. Rodriguez { 508b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 509b622a720SLuis R. Rodriguez 510b622a720SLuis R. Rodriguez ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 511b622a720SLuis R. Rodriguez } 512b622a720SLuis R. Rodriguez 513b622a720SLuis R. Rodriguez void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 514b622a720SLuis R. Rodriguez u32 size, u32 flags) 515b622a720SLuis R. Rodriguez { 516b622a720SLuis R. Rodriguez struct ar5416_desc *ads = AR5416DESC(ds); 517b622a720SLuis R. Rodriguez struct ath9k_hw_capabilities *pCap = &ah->caps; 518b622a720SLuis R. Rodriguez 519b622a720SLuis R. Rodriguez ads->ds_ctl1 = size & AR_BufLen; 520b622a720SLuis R. Rodriguez if (flags & ATH9K_RXDESC_INTREQ) 521b622a720SLuis R. Rodriguez ads->ds_ctl1 |= AR_RxIntrReq; 522b622a720SLuis R. Rodriguez 523b622a720SLuis R. Rodriguez ads->ds_rxstatus8 &= ~AR_RxDone; 524b622a720SLuis R. Rodriguez if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 525b622a720SLuis R. Rodriguez memset(&(ads->u), 0, sizeof(ads->u)); 526b622a720SLuis R. Rodriguez } 527b622a720SLuis R. Rodriguez EXPORT_SYMBOL(ath9k_hw_setuprxdesc); 528b622a720SLuis R. Rodriguez 529b622a720SLuis R. Rodriguez void ar9002_hw_attach_mac_ops(struct ath_hw *ah) 530b622a720SLuis R. Rodriguez { 531b622a720SLuis R. Rodriguez struct ath_hw_ops *ops = ath9k_hw_ops(ah); 532b622a720SLuis R. Rodriguez 533b622a720SLuis R. Rodriguez ops->rx_enable = ar9002_hw_rx_enable; 534b622a720SLuis R. Rodriguez ops->set_desc_link = ar9002_hw_set_desc_link; 535b622a720SLuis R. Rodriguez ops->get_isr = ar9002_hw_get_isr; 5362b63a41dSFelix Fietkau ops->set_txdesc = ar9002_set_txdesc; 537b622a720SLuis R. Rodriguez ops->fill_txdesc = ar9002_hw_fill_txdesc; 538b622a720SLuis R. Rodriguez ops->proc_txdesc = ar9002_hw_proc_txdesc; 539b622a720SLuis R. Rodriguez ops->set11n_txdesc = ar9002_hw_set11n_txdesc; 540b622a720SLuis R. Rodriguez ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario; 541b622a720SLuis R. Rodriguez ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first; 542b622a720SLuis R. Rodriguez ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle; 543b622a720SLuis R. Rodriguez ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last; 544b622a720SLuis R. Rodriguez ops->clr11n_aggr = ar9002_hw_clr11n_aggr; 5455519541dSFelix Fietkau ops->set_clrdmask = ar9002_hw_set_clrdmask; 546b622a720SLuis R. Rodriguez } 547