1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar5008_initvals.h" 19 #include "ar9001_initvals.h" 20 #include "ar9002_initvals.h" 21 #include "ar9002_phy.h" 22 23 int modparam_force_new_ani; 24 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444); 25 MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002"); 26 27 /* General hardware code for the A5008/AR9001/AR9002 hadware families */ 28 29 static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 30 { 31 if (AR_SREV_9271(ah)) { 32 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, 33 ARRAY_SIZE(ar9271Modes_9271), 6); 34 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, 35 ARRAY_SIZE(ar9271Common_9271), 2); 36 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, 37 ar9271Common_normal_cck_fir_coeff_9271, 38 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); 39 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, 40 ar9271Common_japan_2484_cck_fir_coeff_9271, 41 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); 42 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, 43 ar9271Modes_9271_1_0_only, 44 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); 45 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, 46 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); 47 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 48 ar9271Modes_high_power_tx_gain_9271, 49 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); 50 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 51 ar9271Modes_normal_power_tx_gain_9271, 52 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); 53 return; 54 } 55 56 if (AR_SREV_9287_11_OR_LATER(ah)) { 57 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, 58 ARRAY_SIZE(ar9287Modes_9287_1_1), 6); 59 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, 60 ARRAY_SIZE(ar9287Common_9287_1_1), 2); 61 if (ah->config.pcie_clock_req) 62 INIT_INI_ARRAY(&ah->iniPcieSerdes, 63 ar9287PciePhy_clkreq_off_L1_9287_1_1, 64 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); 65 else 66 INIT_INI_ARRAY(&ah->iniPcieSerdes, 67 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 68 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), 69 2); 70 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 71 72 73 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 74 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 75 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, 76 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 77 78 if (ah->config.pcie_clock_req) { 79 INIT_INI_ARRAY(&ah->iniPcieSerdes, 80 ar9285PciePhy_clkreq_off_L1_9285_1_2, 81 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 82 } else { 83 INIT_INI_ARRAY(&ah->iniPcieSerdes, 84 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 85 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 86 2); 87 } 88 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 89 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 90 ARRAY_SIZE(ar9280Modes_9280_2), 6); 91 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, 92 ARRAY_SIZE(ar9280Common_9280_2), 2); 93 94 if (ah->config.pcie_clock_req) { 95 INIT_INI_ARRAY(&ah->iniPcieSerdes, 96 ar9280PciePhy_clkreq_off_L1_9280, 97 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); 98 } else { 99 INIT_INI_ARRAY(&ah->iniPcieSerdes, 100 ar9280PciePhy_clkreq_always_on_L1_9280, 101 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 102 } 103 INIT_INI_ARRAY(&ah->iniModesAdditional, 104 ar9280Modes_fast_clock_9280_2, 105 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 106 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 107 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 108 ARRAY_SIZE(ar5416Modes_9160), 6); 109 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, 110 ARRAY_SIZE(ar5416Common_9160), 2); 111 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, 112 ARRAY_SIZE(ar5416Bank0_9160), 2); 113 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, 114 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 115 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, 116 ARRAY_SIZE(ar5416Bank1_9160), 2); 117 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, 118 ARRAY_SIZE(ar5416Bank2_9160), 2); 119 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, 120 ARRAY_SIZE(ar5416Bank3_9160), 3); 121 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, 122 ARRAY_SIZE(ar5416Bank6_9160), 3); 123 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, 124 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 125 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, 126 ARRAY_SIZE(ar5416Bank7_9160), 2); 127 if (AR_SREV_9160_11(ah)) { 128 INIT_INI_ARRAY(&ah->iniAddac, 129 ar5416Addac_9160_1_1, 130 ARRAY_SIZE(ar5416Addac_9160_1_1), 2); 131 } else { 132 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 133 ARRAY_SIZE(ar5416Addac_9160), 2); 134 } 135 } else if (AR_SREV_9100_OR_LATER(ah)) { 136 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 137 ARRAY_SIZE(ar5416Modes_9100), 6); 138 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 139 ARRAY_SIZE(ar5416Common_9100), 2); 140 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, 141 ARRAY_SIZE(ar5416Bank0_9100), 2); 142 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, 143 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 144 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, 145 ARRAY_SIZE(ar5416Bank1_9100), 2); 146 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, 147 ARRAY_SIZE(ar5416Bank2_9100), 2); 148 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, 149 ARRAY_SIZE(ar5416Bank3_9100), 3); 150 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, 151 ARRAY_SIZE(ar5416Bank6_9100), 3); 152 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 153 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 154 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, 155 ARRAY_SIZE(ar5416Bank7_9100), 2); 156 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, 157 ARRAY_SIZE(ar5416Addac_9100), 2); 158 } else { 159 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 160 ARRAY_SIZE(ar5416Modes), 6); 161 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 162 ARRAY_SIZE(ar5416Common), 2); 163 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 164 ARRAY_SIZE(ar5416Bank0), 2); 165 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 166 ARRAY_SIZE(ar5416BB_RfGain), 3); 167 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 168 ARRAY_SIZE(ar5416Bank1), 2); 169 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, 170 ARRAY_SIZE(ar5416Bank2), 2); 171 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, 172 ARRAY_SIZE(ar5416Bank3), 3); 173 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 174 ARRAY_SIZE(ar5416Bank6), 3); 175 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, 176 ARRAY_SIZE(ar5416Bank6TPC), 3); 177 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, 178 ARRAY_SIZE(ar5416Bank7), 2); 179 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, 180 ARRAY_SIZE(ar5416Addac), 2); 181 } 182 } 183 184 /* Support for Japan ch.14 (2484) spread */ 185 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah) 186 { 187 if (AR_SREV_9287_11_OR_LATER(ah)) { 188 INIT_INI_ARRAY(&ah->iniCckfirNormal, 189 ar9287Common_normal_cck_fir_coeff_9287_1_1, 190 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1), 191 2); 192 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 193 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 194 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1), 195 2); 196 } 197 } 198 199 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) 200 { 201 u32 rxgain_type; 202 203 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= 204 AR5416_EEP_MINOR_VER_17) { 205 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 206 207 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 208 INIT_INI_ARRAY(&ah->iniModesRxGain, 209 ar9280Modes_backoff_13db_rxgain_9280_2, 210 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 211 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 212 INIT_INI_ARRAY(&ah->iniModesRxGain, 213 ar9280Modes_backoff_23db_rxgain_9280_2, 214 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 215 else 216 INIT_INI_ARRAY(&ah->iniModesRxGain, 217 ar9280Modes_original_rxgain_9280_2, 218 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 219 } else { 220 INIT_INI_ARRAY(&ah->iniModesRxGain, 221 ar9280Modes_original_rxgain_9280_2, 222 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 223 } 224 } 225 226 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah) 227 { 228 u32 txgain_type; 229 230 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= 231 AR5416_EEP_MINOR_VER_19) { 232 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 233 234 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 235 INIT_INI_ARRAY(&ah->iniModesTxGain, 236 ar9280Modes_high_power_tx_gain_9280_2, 237 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 238 else 239 INIT_INI_ARRAY(&ah->iniModesTxGain, 240 ar9280Modes_original_tx_gain_9280_2, 241 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 242 } else { 243 INIT_INI_ARRAY(&ah->iniModesTxGain, 244 ar9280Modes_original_tx_gain_9280_2, 245 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 246 } 247 } 248 249 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) 250 { 251 if (AR_SREV_9287_11_OR_LATER(ah)) 252 INIT_INI_ARRAY(&ah->iniModesRxGain, 253 ar9287Modes_rx_gain_9287_1_1, 254 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); 255 else if (AR_SREV_9280_20(ah)) 256 ar9280_20_hw_init_rxgain_ini(ah); 257 258 if (AR_SREV_9287_11_OR_LATER(ah)) { 259 INIT_INI_ARRAY(&ah->iniModesTxGain, 260 ar9287Modes_tx_gain_9287_1_1, 261 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); 262 } else if (AR_SREV_9280_20(ah)) { 263 ar9280_20_hw_init_txgain_ini(ah); 264 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 265 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 266 267 /* txgain table */ 268 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 269 if (AR_SREV_9285E_20(ah)) { 270 INIT_INI_ARRAY(&ah->iniModesTxGain, 271 ar9285Modes_XE2_0_high_power, 272 ARRAY_SIZE( 273 ar9285Modes_XE2_0_high_power), 6); 274 } else { 275 INIT_INI_ARRAY(&ah->iniModesTxGain, 276 ar9285Modes_high_power_tx_gain_9285_1_2, 277 ARRAY_SIZE( 278 ar9285Modes_high_power_tx_gain_9285_1_2), 6); 279 } 280 } else { 281 if (AR_SREV_9285E_20(ah)) { 282 INIT_INI_ARRAY(&ah->iniModesTxGain, 283 ar9285Modes_XE2_0_normal_power, 284 ARRAY_SIZE( 285 ar9285Modes_XE2_0_normal_power), 6); 286 } else { 287 INIT_INI_ARRAY(&ah->iniModesTxGain, 288 ar9285Modes_original_tx_gain_9285_1_2, 289 ARRAY_SIZE( 290 ar9285Modes_original_tx_gain_9285_1_2), 6); 291 } 292 } 293 } 294 } 295 296 /* 297 * Helper for ASPM support. 298 * 299 * Disable PLL when in L0s as well as receiver clock when in L1. 300 * This power saving option must be enabled through the SerDes. 301 * 302 * Programming the SerDes must go through the same 288 bit serial shift 303 * register as the other analog registers. Hence the 9 writes. 304 */ 305 static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 306 int restore, 307 int power_off) 308 { 309 u8 i; 310 u32 val; 311 312 if (ah->is_pciexpress != true || ah->aspm_enabled != true) 313 return; 314 315 /* Nothing to do on restore for 11N */ 316 if (!restore) { 317 if (AR_SREV_9280_20_OR_LATER(ah)) { 318 /* 319 * AR9280 2.0 or later chips use SerDes values from the 320 * initvals.h initialized depending on chipset during 321 * __ath9k_hw_init() 322 */ 323 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { 324 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 325 INI_RA(&ah->iniPcieSerdes, i, 1)); 326 } 327 } else { 328 ENABLE_REGWRITE_BUFFER(ah); 329 330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 332 333 /* RX shut off when elecidle is asserted */ 334 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 335 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 336 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 337 338 /* 339 * Ignore ah->ah_config.pcie_clock_req setting for 340 * pre-AR9280 11n 341 */ 342 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 343 344 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 345 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 346 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 347 348 /* Load the new settings */ 349 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 350 351 REGWRITE_BUFFER_FLUSH(ah); 352 } 353 354 udelay(1000); 355 } 356 357 if (power_off) { 358 /* clear bit 19 to disable L1 */ 359 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 360 361 val = REG_READ(ah, AR_WA); 362 363 /* 364 * Set PCIe workaround bits 365 * In AR9280 and AR9285, bit 14 in WA register (disable L1) 366 * should only be set when device enters D3 and be 367 * cleared when device comes back to D0. 368 */ 369 if (ah->config.pcie_waen) { 370 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) 371 val |= AR_WA_D3_L1_DISABLE; 372 } else { 373 if (((AR_SREV_9285(ah) || 374 AR_SREV_9271(ah) || 375 AR_SREV_9287(ah)) && 376 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || 377 (AR_SREV_9280(ah) && 378 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { 379 val |= AR_WA_D3_L1_DISABLE; 380 } 381 } 382 383 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { 384 /* 385 * Disable bit 6 and 7 before entering D3 to 386 * prevent system hang. 387 */ 388 val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 389 } 390 391 if (AR_SREV_9280(ah)) 392 val |= AR_WA_BIT22; 393 394 if (AR_SREV_9285E_20(ah)) 395 val |= AR_WA_BIT23; 396 397 REG_WRITE(ah, AR_WA, val); 398 } else { 399 if (ah->config.pcie_waen) { 400 val = ah->config.pcie_waen; 401 if (!power_off) 402 val &= (~AR_WA_D3_L1_DISABLE); 403 } else { 404 if (AR_SREV_9285(ah) || 405 AR_SREV_9271(ah) || 406 AR_SREV_9287(ah)) { 407 val = AR9285_WA_DEFAULT; 408 if (!power_off) 409 val &= (~AR_WA_D3_L1_DISABLE); 410 } 411 else if (AR_SREV_9280(ah)) { 412 /* 413 * For AR9280 chips, bit 22 of 0x4004 414 * needs to be set. 415 */ 416 val = AR9280_WA_DEFAULT; 417 if (!power_off) 418 val &= (~AR_WA_D3_L1_DISABLE); 419 } else { 420 val = AR_WA_DEFAULT; 421 } 422 } 423 424 /* WAR for ASPM system hang */ 425 if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) 426 val |= (AR_WA_BIT6 | AR_WA_BIT7); 427 428 if (AR_SREV_9285E_20(ah)) 429 val |= AR_WA_BIT23; 430 431 REG_WRITE(ah, AR_WA, val); 432 433 /* set bit 19 to allow forcing of pcie core into L1 state */ 434 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 435 } 436 } 437 438 static int ar9002_hw_get_radiorev(struct ath_hw *ah) 439 { 440 u32 val; 441 int i; 442 443 ENABLE_REGWRITE_BUFFER(ah); 444 445 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 446 for (i = 0; i < 8; i++) 447 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 448 449 REGWRITE_BUFFER_FLUSH(ah); 450 451 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 452 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 453 454 return ath9k_hw_reverse_bits(val, 8); 455 } 456 457 int ar9002_hw_rf_claim(struct ath_hw *ah) 458 { 459 u32 val; 460 461 REG_WRITE(ah, AR_PHY(0), 0x00000007); 462 463 val = ar9002_hw_get_radiorev(ah); 464 switch (val & AR_RADIO_SREV_MAJOR) { 465 case 0: 466 val = AR_RAD5133_SREV_MAJOR; 467 break; 468 case AR_RAD5133_SREV_MAJOR: 469 case AR_RAD5122_SREV_MAJOR: 470 case AR_RAD2133_SREV_MAJOR: 471 case AR_RAD2122_SREV_MAJOR: 472 break; 473 default: 474 ath_err(ath9k_hw_common(ah), 475 "Radio Chip Rev 0x%02X not supported\n", 476 val & AR_RADIO_SREV_MAJOR); 477 return -EOPNOTSUPP; 478 } 479 480 ah->hw_version.analog5GhzRev = val; 481 482 return 0; 483 } 484 485 void ar9002_hw_enable_async_fifo(struct ath_hw *ah) 486 { 487 if (AR_SREV_9287_13_OR_LATER(ah)) { 488 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 489 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 490 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 491 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 492 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 493 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 494 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 495 } 496 } 497 498 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ 499 void ar9002_hw_attach_ops(struct ath_hw *ah) 500 { 501 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 502 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 503 504 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; 505 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; 506 507 ops->config_pci_powersave = ar9002_hw_configpcipowersave; 508 509 ar5008_hw_attach_phy_ops(ah); 510 if (AR_SREV_9280_20_OR_LATER(ah)) 511 ar9002_hw_attach_phy_ops(ah); 512 513 ar9002_hw_attach_calib_ops(ah); 514 ar9002_hw_attach_mac_ops(ah); 515 } 516 517 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) 518 { 519 u32 modesIndex; 520 int i; 521 522 switch (chan->chanmode) { 523 case CHANNEL_A: 524 case CHANNEL_A_HT20: 525 modesIndex = 1; 526 break; 527 case CHANNEL_A_HT40PLUS: 528 case CHANNEL_A_HT40MINUS: 529 modesIndex = 2; 530 break; 531 case CHANNEL_G: 532 case CHANNEL_G_HT20: 533 case CHANNEL_B: 534 modesIndex = 4; 535 break; 536 case CHANNEL_G_HT40PLUS: 537 case CHANNEL_G_HT40MINUS: 538 modesIndex = 3; 539 break; 540 541 default: 542 return; 543 } 544 545 ENABLE_REGWRITE_BUFFER(ah); 546 547 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { 548 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); 549 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); 550 u32 val_orig; 551 552 if (reg == AR_PHY_CCK_DETECT) { 553 val_orig = REG_READ(ah, reg); 554 val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; 555 val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; 556 557 REG_WRITE(ah, reg, val|val_orig); 558 } else 559 REG_WRITE(ah, reg, val); 560 } 561 562 REGWRITE_BUFFER_FLUSH(ah); 563 } 564