1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/moduleparam.h> 18 #include "hw.h" 19 #include "ar5008_initvals.h" 20 #include "ar9001_initvals.h" 21 #include "ar9002_initvals.h" 22 #include "ar9002_phy.h" 23 24 /* General hardware code for the A5008/AR9001/AR9002 hadware families */ 25 26 static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 27 { 28 if (AR_SREV_9271(ah)) { 29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); 30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); 31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); 32 return; 33 } 34 35 if (ah->config.pcie_clock_req) 36 INIT_INI_ARRAY(&ah->iniPcieSerdes, 37 ar9280PciePhy_clkreq_off_L1_9280); 38 else 39 INIT_INI_ARRAY(&ah->iniPcieSerdes, 40 ar9280PciePhy_clkreq_always_on_L1_9280); 41 #ifdef CONFIG_PM_SLEEP 42 INIT_INI_ARRAY(&ah->iniPcieSerdesWow, 43 ar9280PciePhy_awow); 44 #endif 45 46 if (AR_SREV_9287_11_OR_LATER(ah)) { 47 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); 48 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); 49 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 50 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); 51 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); 52 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 53 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2); 54 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2); 55 56 INIT_INI_ARRAY(&ah->iniModesFastClock, 57 ar9280Modes_fast_clock_9280_2); 58 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 59 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160); 60 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160); 61 if (AR_SREV_9160_11(ah)) { 62 INIT_INI_ARRAY(&ah->iniAddac, 63 ar5416Addac_9160_1_1); 64 } else { 65 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160); 66 } 67 } else if (AR_SREV_9100_OR_LATER(ah)) { 68 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100); 69 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100); 70 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100); 71 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100); 72 } else { 73 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes); 74 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common); 75 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC); 76 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac); 77 } 78 79 if (!AR_SREV_9280_20_OR_LATER(ah)) { 80 /* Common for AR5416, AR913x, AR9160 */ 81 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain); 82 83 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0); 84 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1); 85 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2); 86 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3); 87 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7); 88 89 /* Common for AR5416, AR9160 */ 90 if (!AR_SREV_9100(ah)) 91 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6); 92 93 /* Common for AR913x, AR9160 */ 94 if (!AR_SREV_5416(ah)) 95 INIT_INI_ARRAY(&ah->iniBank6TPC, 96 ar5416Bank6TPC_9100); 97 } 98 99 /* iniAddac needs to be modified for these chips */ 100 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { 101 struct ar5416IniArray *addac = &ah->iniAddac; 102 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns; 103 u32 *data; 104 105 data = kmalloc(size, GFP_KERNEL); 106 if (!data) 107 return; 108 109 memcpy(data, addac->ia_array, size); 110 addac->ia_array = data; 111 112 if (!AR_SREV_5416_22_OR_LATER(ah)) { 113 /* override CLKDRV value */ 114 INI_RA(addac, 31,1) = 0; 115 } 116 } 117 if (AR_SREV_9287_11_OR_LATER(ah)) { 118 INIT_INI_ARRAY(&ah->iniCckfirNormal, 119 ar9287Common_normal_cck_fir_coeff_9287_1_1); 120 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 121 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1); 122 } 123 } 124 125 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) 126 { 127 u32 rxgain_type; 128 129 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= 130 AR5416_EEP_MINOR_VER_17) { 131 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); 132 133 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 134 INIT_INI_ARRAY(&ah->iniModesRxGain, 135 ar9280Modes_backoff_13db_rxgain_9280_2); 136 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 137 INIT_INI_ARRAY(&ah->iniModesRxGain, 138 ar9280Modes_backoff_23db_rxgain_9280_2); 139 else 140 INIT_INI_ARRAY(&ah->iniModesRxGain, 141 ar9280Modes_original_rxgain_9280_2); 142 } else { 143 INIT_INI_ARRAY(&ah->iniModesRxGain, 144 ar9280Modes_original_rxgain_9280_2); 145 } 146 } 147 148 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) 149 { 150 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= 151 AR5416_EEP_MINOR_VER_19) { 152 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 153 INIT_INI_ARRAY(&ah->iniModesTxGain, 154 ar9280Modes_high_power_tx_gain_9280_2); 155 else 156 INIT_INI_ARRAY(&ah->iniModesTxGain, 157 ar9280Modes_original_tx_gain_9280_2); 158 } else { 159 INIT_INI_ARRAY(&ah->iniModesTxGain, 160 ar9280Modes_original_tx_gain_9280_2); 161 } 162 } 163 164 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) 165 { 166 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 167 INIT_INI_ARRAY(&ah->iniModesTxGain, 168 ar9271Modes_high_power_tx_gain_9271); 169 else 170 INIT_INI_ARRAY(&ah->iniModesTxGain, 171 ar9271Modes_normal_power_tx_gain_9271); 172 } 173 174 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) 175 { 176 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); 177 178 if (AR_SREV_9287_11_OR_LATER(ah)) 179 INIT_INI_ARRAY(&ah->iniModesRxGain, 180 ar9287Modes_rx_gain_9287_1_1); 181 else if (AR_SREV_9280_20(ah)) 182 ar9280_20_hw_init_rxgain_ini(ah); 183 184 if (AR_SREV_9271(ah)) { 185 ar9271_hw_init_txgain_ini(ah, txgain_type); 186 } else if (AR_SREV_9287_11_OR_LATER(ah)) { 187 INIT_INI_ARRAY(&ah->iniModesTxGain, 188 ar9287Modes_tx_gain_9287_1_1); 189 } else if (AR_SREV_9280_20(ah)) { 190 ar9280_20_hw_init_txgain_ini(ah, txgain_type); 191 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 192 /* txgain table */ 193 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 194 if (AR_SREV_9285E_20(ah)) { 195 INIT_INI_ARRAY(&ah->iniModesTxGain, 196 ar9285Modes_XE2_0_high_power); 197 } else { 198 INIT_INI_ARRAY(&ah->iniModesTxGain, 199 ar9285Modes_high_power_tx_gain_9285_1_2); 200 } 201 } else { 202 if (AR_SREV_9285E_20(ah)) { 203 INIT_INI_ARRAY(&ah->iniModesTxGain, 204 ar9285Modes_XE2_0_normal_power); 205 } else { 206 INIT_INI_ARRAY(&ah->iniModesTxGain, 207 ar9285Modes_original_tx_gain_9285_1_2); 208 } 209 } 210 } 211 } 212 213 /* 214 * Helper for ASPM support. 215 * 216 * Disable PLL when in L0s as well as receiver clock when in L1. 217 * This power saving option must be enabled through the SerDes. 218 * 219 * Programming the SerDes must go through the same 288 bit serial shift 220 * register as the other analog registers. Hence the 9 writes. 221 */ 222 static void ar9002_hw_configpcipowersave(struct ath_hw *ah, 223 bool power_off) 224 { 225 u8 i; 226 u32 val; 227 228 /* Nothing to do on restore for 11N */ 229 if (!power_off /* !restore */) { 230 if (AR_SREV_9280_20_OR_LATER(ah)) { 231 /* 232 * AR9280 2.0 or later chips use SerDes values from the 233 * initvals.h initialized depending on chipset during 234 * __ath9k_hw_init() 235 */ 236 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { 237 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 238 INI_RA(&ah->iniPcieSerdes, i, 1)); 239 } 240 } else { 241 ENABLE_REGWRITE_BUFFER(ah); 242 243 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 244 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 245 246 /* RX shut off when elecidle is asserted */ 247 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 248 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 249 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 250 251 /* 252 * Ignore ah->ah_config.pcie_clock_req setting for 253 * pre-AR9280 11n 254 */ 255 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 256 257 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 258 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 259 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 260 261 /* Load the new settings */ 262 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 263 264 REGWRITE_BUFFER_FLUSH(ah); 265 } 266 267 udelay(1000); 268 } 269 270 if (power_off) { 271 /* clear bit 19 to disable L1 */ 272 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 273 274 val = REG_READ(ah, AR_WA); 275 276 /* 277 * Set PCIe workaround bits 278 * In AR9280 and AR9285, bit 14 in WA register (disable L1) 279 * should only be set when device enters D3 and be 280 * cleared when device comes back to D0. 281 */ 282 if (ah->config.pcie_waen) { 283 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) 284 val |= AR_WA_D3_L1_DISABLE; 285 } else { 286 if (((AR_SREV_9285(ah) || 287 AR_SREV_9271(ah) || 288 AR_SREV_9287(ah)) && 289 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || 290 (AR_SREV_9280(ah) && 291 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { 292 val |= AR_WA_D3_L1_DISABLE; 293 } 294 } 295 296 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { 297 /* 298 * Disable bit 6 and 7 before entering D3 to 299 * prevent system hang. 300 */ 301 val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 302 } 303 304 if (AR_SREV_9280(ah)) 305 val |= AR_WA_BIT22; 306 307 if (AR_SREV_9285E_20(ah)) 308 val |= AR_WA_BIT23; 309 310 REG_WRITE(ah, AR_WA, val); 311 } else { 312 if (ah->config.pcie_waen) { 313 val = ah->config.pcie_waen; 314 if (!power_off) 315 val &= (~AR_WA_D3_L1_DISABLE); 316 } else { 317 if (AR_SREV_9285(ah) || 318 AR_SREV_9271(ah) || 319 AR_SREV_9287(ah)) { 320 val = AR9285_WA_DEFAULT; 321 if (!power_off) 322 val &= (~AR_WA_D3_L1_DISABLE); 323 } 324 else if (AR_SREV_9280(ah)) { 325 /* 326 * For AR9280 chips, bit 22 of 0x4004 327 * needs to be set. 328 */ 329 val = AR9280_WA_DEFAULT; 330 if (!power_off) 331 val &= (~AR_WA_D3_L1_DISABLE); 332 } else { 333 val = AR_WA_DEFAULT; 334 } 335 } 336 337 /* WAR for ASPM system hang */ 338 if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) 339 val |= (AR_WA_BIT6 | AR_WA_BIT7); 340 341 if (AR_SREV_9285E_20(ah)) 342 val |= AR_WA_BIT23; 343 344 REG_WRITE(ah, AR_WA, val); 345 346 /* set bit 19 to allow forcing of pcie core into L1 state */ 347 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 348 } 349 } 350 351 static int ar9002_hw_get_radiorev(struct ath_hw *ah) 352 { 353 u32 val; 354 int i; 355 356 ENABLE_REGWRITE_BUFFER(ah); 357 358 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 359 for (i = 0; i < 8; i++) 360 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 361 362 REGWRITE_BUFFER_FLUSH(ah); 363 364 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 365 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 366 367 return ath9k_hw_reverse_bits(val, 8); 368 } 369 370 int ar9002_hw_rf_claim(struct ath_hw *ah) 371 { 372 u32 val; 373 374 REG_WRITE(ah, AR_PHY(0), 0x00000007); 375 376 val = ar9002_hw_get_radiorev(ah); 377 switch (val & AR_RADIO_SREV_MAJOR) { 378 case 0: 379 val = AR_RAD5133_SREV_MAJOR; 380 break; 381 case AR_RAD5133_SREV_MAJOR: 382 case AR_RAD5122_SREV_MAJOR: 383 case AR_RAD2133_SREV_MAJOR: 384 case AR_RAD2122_SREV_MAJOR: 385 break; 386 default: 387 ath_err(ath9k_hw_common(ah), 388 "Radio Chip Rev 0x%02X not supported\n", 389 val & AR_RADIO_SREV_MAJOR); 390 return -EOPNOTSUPP; 391 } 392 393 ah->hw_version.analog5GhzRev = val; 394 395 return 0; 396 } 397 398 void ar9002_hw_enable_async_fifo(struct ath_hw *ah) 399 { 400 if (AR_SREV_9287_13_OR_LATER(ah)) { 401 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 402 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 403 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 404 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 405 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 406 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 407 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 408 } 409 } 410 411 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ 412 void ar9002_hw_attach_ops(struct ath_hw *ah) 413 { 414 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 415 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 416 417 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; 418 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; 419 420 ops->config_pci_powersave = ar9002_hw_configpcipowersave; 421 422 ar5008_hw_attach_phy_ops(ah); 423 if (AR_SREV_9280_20_OR_LATER(ah)) 424 ar9002_hw_attach_phy_ops(ah); 425 426 ar9002_hw_attach_calib_ops(ah); 427 ar9002_hw_attach_mac_ops(ah); 428 } 429 430 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) 431 { 432 u32 modesIndex; 433 int i; 434 435 switch (chan->chanmode) { 436 case CHANNEL_A: 437 case CHANNEL_A_HT20: 438 modesIndex = 1; 439 break; 440 case CHANNEL_A_HT40PLUS: 441 case CHANNEL_A_HT40MINUS: 442 modesIndex = 2; 443 break; 444 case CHANNEL_G: 445 case CHANNEL_G_HT20: 446 case CHANNEL_B: 447 modesIndex = 4; 448 break; 449 case CHANNEL_G_HT40PLUS: 450 case CHANNEL_G_HT40MINUS: 451 modesIndex = 3; 452 break; 453 454 default: 455 return; 456 } 457 458 ENABLE_REGWRITE_BUFFER(ah); 459 460 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { 461 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); 462 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); 463 u32 val_orig; 464 465 if (reg == AR_PHY_CCK_DETECT) { 466 val_orig = REG_READ(ah, reg); 467 val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; 468 val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; 469 470 REG_WRITE(ah, reg, val|val_orig); 471 } else 472 REG_WRITE(ah, reg, val); 473 } 474 475 REGWRITE_BUFFER_FLUSH(ah); 476 } 477