1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 #include "ar5008_initvals.h" 22 23 /* All code below is for AR5008, AR9001, AR9002 */ 24 25 #define AR5008_OFDM_RATES 8 26 #define AR5008_HT_SS_RATES 8 27 #define AR5008_HT_DS_RATES 8 28 29 #define AR5008_HT20_SHIFT 16 30 #define AR5008_HT40_SHIFT 24 31 32 #define AR5008_11NA_OFDM_SHIFT 0 33 #define AR5008_11NA_HT_SS_SHIFT 8 34 #define AR5008_11NA_HT_DS_SHIFT 16 35 36 #define AR5008_11NG_OFDM_SHIFT 4 37 #define AR5008_11NG_HT_SS_SHIFT 12 38 #define AR5008_11NG_HT_DS_SHIFT 20 39 40 static const int firstep_table[] = 41 /* level: 0 1 2 3 4 5 6 7 8 */ 42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 43 44 /* 45 * register values to turn OFDM weak signal detection OFF 46 */ 47 static const int m1ThreshLow_off = 127; 48 static const int m2ThreshLow_off = 127; 49 static const int m1Thresh_off = 127; 50 static const int m2Thresh_off = 127; 51 static const int m2CountThr_off = 31; 52 static const int m2CountThrLow_off = 63; 53 static const int m1ThreshLowExt_off = 127; 54 static const int m2ThreshLowExt_off = 127; 55 static const int m1ThreshExt_off = 127; 56 static const int m2ThreshExt_off = 127; 57 58 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 59 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 60 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 61 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 62 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 63 64 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 65 { 66 struct ar5416IniArray *array = &ah->iniBank6; 67 u32 *data = ah->analogBank6Data; 68 int r; 69 70 ENABLE_REGWRITE_BUFFER(ah); 71 72 for (r = 0; r < array->ia_rows; r++) { 73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 74 DO_DELAY(*writecnt); 75 } 76 77 REGWRITE_BUFFER_FLUSH(ah); 78 } 79 80 /** 81 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 82 * @rfbuf: 83 * @reg32: 84 * @numBits: 85 * @firstBit: 86 * @column: 87 * 88 * Performs analog "swizzling" of parameters into their location. 89 * Used on external AR2133/AR5133 radios. 90 */ 91 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 92 u32 numBits, u32 firstBit, 93 u32 column) 94 { 95 u32 tmp32, mask, arrayEntry, lastBit; 96 int32_t bitPosition, bitsLeft; 97 98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 99 arrayEntry = (firstBit - 1) / 8; 100 bitPosition = (firstBit - 1) % 8; 101 bitsLeft = numBits; 102 while (bitsLeft > 0) { 103 lastBit = (bitPosition + bitsLeft > 8) ? 104 8 : bitPosition + bitsLeft; 105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 106 (column * 8); 107 rfBuf[arrayEntry] &= ~mask; 108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 109 (column * 8)) & mask; 110 bitsLeft -= 8 - bitPosition; 111 tmp32 = tmp32 >> (8 - bitPosition); 112 bitPosition = 0; 113 arrayEntry++; 114 } 115 } 116 117 /* 118 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 119 * rf_pwd_icsyndiv. 120 * 121 * Theoretical Rules: 122 * if 2 GHz band 123 * if forceBiasAuto 124 * if synth_freq < 2412 125 * bias = 0 126 * else if 2412 <= synth_freq <= 2422 127 * bias = 1 128 * else // synth_freq > 2422 129 * bias = 2 130 * else if forceBias > 0 131 * bias = forceBias & 7 132 * else 133 * no change, use value from ini file 134 * else 135 * no change, invalid band 136 * 137 * 1st Mod: 138 * 2422 also uses value of 2 139 * <approved> 140 * 141 * 2nd Mod: 142 * Less than 2412 uses value of 0, 2412 and above uses value of 2 143 */ 144 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 145 { 146 struct ath_common *common = ath9k_hw_common(ah); 147 u32 tmp_reg; 148 int reg_writes = 0; 149 u32 new_bias = 0; 150 151 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 152 return; 153 154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 155 156 if (synth_freq < 2412) 157 new_bias = 0; 158 else if (synth_freq < 2422) 159 new_bias = 1; 160 else 161 new_bias = 2; 162 163 /* pre-reverse this field */ 164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 165 166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 167 new_bias, synth_freq); 168 169 /* swizzle rf_pwd_icsyndiv */ 170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 171 172 /* write Bank 6 with new params */ 173 ar5008_write_bank6(ah, ®_writes); 174 } 175 176 /** 177 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 178 * @ah: atheros hardware structure 179 * @chan: 180 * 181 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 182 * the channel value. Assumes writes enabled to analog bus and bank6 register 183 * cache in ah->analogBank6Data. 184 */ 185 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 186 { 187 struct ath_common *common = ath9k_hw_common(ah); 188 u32 channelSel = 0; 189 u32 bModeSynth = 0; 190 u32 aModeRefSel = 0; 191 u32 reg32 = 0; 192 u16 freq; 193 struct chan_centers centers; 194 195 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 196 freq = centers.synth_center; 197 198 if (freq < 4800) { 199 u32 txctl; 200 201 if (((freq - 2192) % 5) == 0) { 202 channelSel = ((freq - 672) * 2 - 3040) / 10; 203 bModeSynth = 0; 204 } else if (((freq - 2224) % 5) == 0) { 205 channelSel = ((freq - 704) * 2 - 3040) / 10; 206 bModeSynth = 1; 207 } else { 208 ath_err(common, "Invalid channel %u MHz\n", freq); 209 return -EINVAL; 210 } 211 212 channelSel = (channelSel << 2) & 0xff; 213 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 214 215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 216 if (freq == 2484) { 217 218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 220 } else { 221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 223 } 224 225 } else if ((freq % 20) == 0 && freq >= 5120) { 226 channelSel = 227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 228 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 229 } else if ((freq % 10) == 0) { 230 channelSel = 231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 233 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 234 else 235 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 236 } else if ((freq % 5) == 0) { 237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 238 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 239 } else { 240 ath_err(common, "Invalid channel %u MHz\n", freq); 241 return -EINVAL; 242 } 243 244 ar5008_hw_force_bias(ah, freq); 245 246 reg32 = 247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 248 (1 << 5) | 0x1; 249 250 REG_WRITE(ah, AR_PHY(0x37), reg32); 251 252 ah->curchan = chan; 253 254 return 0; 255 } 256 257 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, 258 struct ath9k_channel *chan, int bin) 259 { 260 int cur_bin; 261 int upper, lower, cur_vit_mask; 262 int i; 263 int8_t mask_m[123] = {0}; 264 int8_t mask_p[123] = {0}; 265 int8_t mask_amt; 266 int tmp_mask; 267 static const int pilot_mask_reg[4] = { 268 AR_PHY_TIMING7, AR_PHY_TIMING8, 269 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 270 }; 271 static const int chan_mask_reg[4] = { 272 AR_PHY_TIMING9, AR_PHY_TIMING10, 273 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 274 }; 275 static const int inc[4] = { 0, 100, 0, 0 }; 276 277 cur_bin = -6000; 278 upper = bin + 100; 279 lower = bin - 100; 280 281 for (i = 0; i < 4; i++) { 282 int pilot_mask = 0; 283 int chan_mask = 0; 284 int bp = 0; 285 286 for (bp = 0; bp < 30; bp++) { 287 if ((cur_bin > lower) && (cur_bin < upper)) { 288 pilot_mask = pilot_mask | 0x1 << bp; 289 chan_mask = chan_mask | 0x1 << bp; 290 } 291 cur_bin += 100; 292 } 293 cur_bin += inc[i]; 294 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 295 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 296 } 297 298 cur_vit_mask = 6100; 299 upper = bin + 120; 300 lower = bin - 120; 301 302 for (i = 0; i < ARRAY_SIZE(mask_m); i++) { 303 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 304 /* workaround for gcc bug #37014 */ 305 volatile int tmp_v = abs(cur_vit_mask - bin); 306 307 if (tmp_v < 75) 308 mask_amt = 1; 309 else 310 mask_amt = 0; 311 if (cur_vit_mask < 0) 312 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 313 else 314 mask_p[cur_vit_mask / 100] = mask_amt; 315 } 316 cur_vit_mask -= 100; 317 } 318 319 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 320 | (mask_m[48] << 26) | (mask_m[49] << 24) 321 | (mask_m[50] << 22) | (mask_m[51] << 20) 322 | (mask_m[52] << 18) | (mask_m[53] << 16) 323 | (mask_m[54] << 14) | (mask_m[55] << 12) 324 | (mask_m[56] << 10) | (mask_m[57] << 8) 325 | (mask_m[58] << 6) | (mask_m[59] << 4) 326 | (mask_m[60] << 2) | (mask_m[61] << 0); 327 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 328 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 329 330 tmp_mask = (mask_m[31] << 28) 331 | (mask_m[32] << 26) | (mask_m[33] << 24) 332 | (mask_m[34] << 22) | (mask_m[35] << 20) 333 | (mask_m[36] << 18) | (mask_m[37] << 16) 334 | (mask_m[48] << 14) | (mask_m[39] << 12) 335 | (mask_m[40] << 10) | (mask_m[41] << 8) 336 | (mask_m[42] << 6) | (mask_m[43] << 4) 337 | (mask_m[44] << 2) | (mask_m[45] << 0); 338 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 339 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 340 341 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 342 | (mask_m[18] << 26) | (mask_m[18] << 24) 343 | (mask_m[20] << 22) | (mask_m[20] << 20) 344 | (mask_m[22] << 18) | (mask_m[22] << 16) 345 | (mask_m[24] << 14) | (mask_m[24] << 12) 346 | (mask_m[25] << 10) | (mask_m[26] << 8) 347 | (mask_m[27] << 6) | (mask_m[28] << 4) 348 | (mask_m[29] << 2) | (mask_m[30] << 0); 349 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 350 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 351 352 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 353 | (mask_m[2] << 26) | (mask_m[3] << 24) 354 | (mask_m[4] << 22) | (mask_m[5] << 20) 355 | (mask_m[6] << 18) | (mask_m[7] << 16) 356 | (mask_m[8] << 14) | (mask_m[9] << 12) 357 | (mask_m[10] << 10) | (mask_m[11] << 8) 358 | (mask_m[12] << 6) | (mask_m[13] << 4) 359 | (mask_m[14] << 2) | (mask_m[15] << 0); 360 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 361 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 362 363 tmp_mask = (mask_p[15] << 28) 364 | (mask_p[14] << 26) | (mask_p[13] << 24) 365 | (mask_p[12] << 22) | (mask_p[11] << 20) 366 | (mask_p[10] << 18) | (mask_p[9] << 16) 367 | (mask_p[8] << 14) | (mask_p[7] << 12) 368 | (mask_p[6] << 10) | (mask_p[5] << 8) 369 | (mask_p[4] << 6) | (mask_p[3] << 4) 370 | (mask_p[2] << 2) | (mask_p[1] << 0); 371 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 372 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 373 374 tmp_mask = (mask_p[30] << 28) 375 | (mask_p[29] << 26) | (mask_p[28] << 24) 376 | (mask_p[27] << 22) | (mask_p[26] << 20) 377 | (mask_p[25] << 18) | (mask_p[24] << 16) 378 | (mask_p[23] << 14) | (mask_p[22] << 12) 379 | (mask_p[21] << 10) | (mask_p[20] << 8) 380 | (mask_p[19] << 6) | (mask_p[18] << 4) 381 | (mask_p[17] << 2) | (mask_p[16] << 0); 382 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 383 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 384 385 tmp_mask = (mask_p[45] << 28) 386 | (mask_p[44] << 26) | (mask_p[43] << 24) 387 | (mask_p[42] << 22) | (mask_p[41] << 20) 388 | (mask_p[40] << 18) | (mask_p[39] << 16) 389 | (mask_p[38] << 14) | (mask_p[37] << 12) 390 | (mask_p[36] << 10) | (mask_p[35] << 8) 391 | (mask_p[34] << 6) | (mask_p[33] << 4) 392 | (mask_p[32] << 2) | (mask_p[31] << 0); 393 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 394 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 395 396 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 397 | (mask_p[59] << 26) | (mask_p[58] << 24) 398 | (mask_p[57] << 22) | (mask_p[56] << 20) 399 | (mask_p[55] << 18) | (mask_p[54] << 16) 400 | (mask_p[53] << 14) | (mask_p[52] << 12) 401 | (mask_p[51] << 10) | (mask_p[50] << 8) 402 | (mask_p[49] << 6) | (mask_p[48] << 4) 403 | (mask_p[47] << 2) | (mask_p[46] << 0); 404 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 405 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 406 } 407 408 /** 409 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 410 * @ah: atheros hardware structure 411 * @chan: 412 * 413 * For non single-chip solutions. Converts to baseband spur frequency given the 414 * input channel frequency and compute register settings below. 415 */ 416 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 417 struct ath9k_channel *chan) 418 { 419 int bb_spur = AR_NO_SPUR; 420 int bin; 421 int spur_freq_sd; 422 int spur_delta_phase; 423 int denominator; 424 int tmp, new; 425 int i; 426 427 int cur_bb_spur; 428 bool is2GHz = IS_CHAN_2GHZ(chan); 429 430 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 431 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 432 if (AR_NO_SPUR == cur_bb_spur) 433 break; 434 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 435 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 436 bb_spur = cur_bb_spur; 437 break; 438 } 439 } 440 441 if (AR_NO_SPUR == bb_spur) 442 return; 443 444 bin = bb_spur * 32; 445 446 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 447 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 448 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 449 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 450 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 451 452 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 453 454 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 455 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 456 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 457 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 458 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 459 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 460 461 spur_delta_phase = ((bb_spur * 524288) / 100) & 462 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 463 464 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 465 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 466 467 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 468 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 469 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 470 REG_WRITE(ah, AR_PHY_TIMING11, new); 471 472 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); 473 } 474 475 /** 476 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 477 * @ah: atheros hardware structure 478 * 479 * Only required for older devices with external AR2133/AR5133 radios. 480 */ 481 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 482 { 483 int size = ah->iniBank6.ia_rows * sizeof(u32); 484 485 if (AR_SREV_9280_20_OR_LATER(ah)) 486 return 0; 487 488 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 489 if (!ah->analogBank6Data) 490 return -ENOMEM; 491 492 return 0; 493 } 494 495 496 /* * 497 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 498 * @ah: atheros hardware structure 499 * @chan: 500 * @modesIndex: 501 * 502 * Used for the external AR2133/AR5133 radios. 503 * 504 * Reads the EEPROM header info from the device structure and programs 505 * all rf registers. This routine requires access to the analog 506 * rf device. This is not required for single-chip devices. 507 */ 508 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 509 struct ath9k_channel *chan, 510 u16 modesIndex) 511 { 512 u32 eepMinorRev; 513 u32 ob5GHz = 0, db5GHz = 0; 514 u32 ob2GHz = 0, db2GHz = 0; 515 int regWrites = 0; 516 int i; 517 518 /* 519 * Software does not need to program bank data 520 * for single chip devices, that is AR9280 or anything 521 * after that. 522 */ 523 if (AR_SREV_9280_20_OR_LATER(ah)) 524 return true; 525 526 /* Setup rf parameters */ 527 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah); 528 529 for (i = 0; i < ah->iniBank6.ia_rows; i++) 530 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 531 532 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 533 if (eepMinorRev >= 2) { 534 if (IS_CHAN_2GHZ(chan)) { 535 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 536 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 537 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 538 ob2GHz, 3, 197, 0); 539 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 540 db2GHz, 3, 194, 0); 541 } else { 542 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 543 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 544 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 545 ob5GHz, 3, 203, 0); 546 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 547 db5GHz, 3, 200, 0); 548 } 549 } 550 551 /* Write Analog registers */ 552 REG_WRITE_ARRAY(&bank0, 1, regWrites); 553 REG_WRITE_ARRAY(&bank1, 1, regWrites); 554 REG_WRITE_ARRAY(&bank2, 1, regWrites); 555 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 556 ar5008_write_bank6(ah, ®Writes); 557 REG_WRITE_ARRAY(&bank7, 1, regWrites); 558 559 return true; 560 } 561 562 static void ar5008_hw_init_bb(struct ath_hw *ah, 563 struct ath9k_channel *chan) 564 { 565 u32 synthDelay; 566 567 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 568 569 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 570 571 ath9k_hw_synth_delay(ah, chan, synthDelay); 572 } 573 574 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 575 { 576 int rx_chainmask, tx_chainmask; 577 578 rx_chainmask = ah->rxchainmask; 579 tx_chainmask = ah->txchainmask; 580 581 582 switch (rx_chainmask) { 583 case 0x5: 584 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 585 AR_PHY_SWAP_ALT_CHAIN); 586 case 0x3: 587 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 588 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 589 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 590 break; 591 } 592 case 0x1: 593 case 0x2: 594 case 0x7: 595 ENABLE_REGWRITE_BUFFER(ah); 596 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 597 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 598 break; 599 default: 600 ENABLE_REGWRITE_BUFFER(ah); 601 break; 602 } 603 604 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 605 606 REGWRITE_BUFFER_FLUSH(ah); 607 608 if (tx_chainmask == 0x5) { 609 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 610 AR_PHY_SWAP_ALT_CHAIN); 611 } 612 if (AR_SREV_9100(ah)) 613 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 614 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 615 } 616 617 static void ar5008_hw_override_ini(struct ath_hw *ah, 618 struct ath9k_channel *chan) 619 { 620 u32 val; 621 622 /* 623 * Set the RX_ABORT and RX_DIS and clear if off only after 624 * RXE is set for MAC. This prevents frames with corrupted 625 * descriptor status. 626 */ 627 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 628 629 if (AR_SREV_9280_20_OR_LATER(ah)) { 630 /* 631 * For AR9280 and above, there is a new feature that allows 632 * Multicast search based on both MAC Address and Key ID. 633 * By default, this feature is enabled. But since the driver 634 * is not using this feature, we switch it off; otherwise 635 * multicast search based on MAC addr only will fail. 636 */ 637 val = REG_READ(ah, AR_PCU_MISC_MODE2) & 638 (~AR_ADHOC_MCAST_KEYID_ENABLE); 639 640 if (!AR_SREV_9271(ah)) 641 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 642 643 if (AR_SREV_9287_11_OR_LATER(ah)) 644 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 645 646 val |= AR_PCU_MISC_MODE2_CFP_IGNORE; 647 648 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 649 } 650 651 if (AR_SREV_9280_20_OR_LATER(ah)) 652 return; 653 /* 654 * Disable BB clock gating 655 * Necessary to avoid issues on AR5416 2.0 656 */ 657 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 658 659 /* 660 * Disable RIFS search on some chips to avoid baseband 661 * hang issues. 662 */ 663 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 664 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 665 val &= ~AR_PHY_RIFS_INIT_DELAY; 666 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 667 } 668 } 669 670 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 671 struct ath9k_channel *chan) 672 { 673 u32 phymode; 674 u32 enableDacFifo = 0; 675 676 if (AR_SREV_9285_12_OR_LATER(ah)) 677 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 678 AR_PHY_FC_ENABLE_DAC_FIFO); 679 680 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 681 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 682 683 if (IS_CHAN_HT40(chan)) { 684 phymode |= AR_PHY_FC_DYN2040_EN; 685 686 if (IS_CHAN_HT40PLUS(chan)) 687 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 688 689 } 690 ENABLE_REGWRITE_BUFFER(ah); 691 REG_WRITE(ah, AR_PHY_TURBO, phymode); 692 693 /* This function do only REG_WRITE, so 694 * we can include it to REGWRITE_BUFFER. */ 695 ath9k_hw_set11nmac2040(ah, chan); 696 697 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 698 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 699 700 REGWRITE_BUFFER_FLUSH(ah); 701 } 702 703 704 static int ar5008_hw_process_ini(struct ath_hw *ah, 705 struct ath9k_channel *chan) 706 { 707 struct ath_common *common = ath9k_hw_common(ah); 708 int i, regWrites = 0; 709 u32 modesIndex, freqIndex; 710 711 if (IS_CHAN_5GHZ(chan)) { 712 freqIndex = 1; 713 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 714 } else { 715 freqIndex = 2; 716 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 717 } 718 719 /* 720 * Set correct baseband to analog shift setting to 721 * access analog chips. 722 */ 723 REG_WRITE(ah, AR_PHY(0), 0x00000007); 724 725 /* Write ADDAC shifts */ 726 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 727 if (ah->eep_ops->set_addac) 728 ah->eep_ops->set_addac(ah, chan); 729 730 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 731 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 732 733 ENABLE_REGWRITE_BUFFER(ah); 734 735 for (i = 0; i < ah->iniModes.ia_rows; i++) { 736 u32 reg = INI_RA(&ah->iniModes, i, 0); 737 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 738 739 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 740 val &= ~AR_AN_TOP2_PWDCLKIND; 741 742 REG_WRITE(ah, reg, val); 743 744 if (reg >= 0x7800 && reg < 0x78a0 745 && ah->config.analog_shiftreg 746 && (common->bus_ops->ath_bus_type != ATH_USB)) { 747 udelay(100); 748 } 749 750 DO_DELAY(regWrites); 751 } 752 753 REGWRITE_BUFFER_FLUSH(ah); 754 755 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 756 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 757 758 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 759 AR_SREV_9287_11_OR_LATER(ah)) 760 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 761 762 if (AR_SREV_9271_10(ah)) { 763 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 764 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 765 } 766 767 ENABLE_REGWRITE_BUFFER(ah); 768 769 /* Write common array parameters */ 770 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 771 u32 reg = INI_RA(&ah->iniCommon, i, 0); 772 u32 val = INI_RA(&ah->iniCommon, i, 1); 773 774 REG_WRITE(ah, reg, val); 775 776 if (reg >= 0x7800 && reg < 0x78a0 777 && ah->config.analog_shiftreg 778 && (common->bus_ops->ath_bus_type != ATH_USB)) { 779 udelay(100); 780 } 781 782 DO_DELAY(regWrites); 783 } 784 785 REGWRITE_BUFFER_FLUSH(ah); 786 787 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 788 789 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 790 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 791 regWrites); 792 793 ar5008_hw_override_ini(ah, chan); 794 ar5008_hw_set_channel_regs(ah, chan); 795 ar5008_hw_init_chain_masks(ah); 796 ath9k_olc_init(ah); 797 ath9k_hw_apply_txpower(ah, chan, false); 798 799 /* Write analog registers */ 800 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 801 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 802 return -EIO; 803 } 804 805 return 0; 806 } 807 808 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 809 { 810 u32 rfMode = 0; 811 812 if (chan == NULL) 813 return; 814 815 if (IS_CHAN_2GHZ(chan)) 816 rfMode |= AR_PHY_MODE_DYNAMIC; 817 else 818 rfMode |= AR_PHY_MODE_OFDM; 819 820 if (!AR_SREV_9280_20_OR_LATER(ah)) 821 rfMode |= (IS_CHAN_5GHZ(chan)) ? 822 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 823 824 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 825 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 826 827 REG_WRITE(ah, AR_PHY_MODE, rfMode); 828 } 829 830 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 831 { 832 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 833 } 834 835 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 836 struct ath9k_channel *chan) 837 { 838 u32 coef_scaled, ds_coef_exp, ds_coef_man; 839 u32 clockMhzScaled = 0x64000000; 840 struct chan_centers centers; 841 842 if (IS_CHAN_HALF_RATE(chan)) 843 clockMhzScaled = clockMhzScaled >> 1; 844 else if (IS_CHAN_QUARTER_RATE(chan)) 845 clockMhzScaled = clockMhzScaled >> 2; 846 847 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 848 coef_scaled = clockMhzScaled / centers.synth_center; 849 850 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 851 &ds_coef_exp); 852 853 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 854 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 855 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 856 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 857 858 coef_scaled = (9 * coef_scaled) / 10; 859 860 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 861 &ds_coef_exp); 862 863 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 864 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 865 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 866 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 867 } 868 869 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 870 { 871 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 872 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 873 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 874 } 875 876 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 877 { 878 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 879 880 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 881 882 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 883 } 884 885 static void ar5008_restore_chainmask(struct ath_hw *ah) 886 { 887 int rx_chainmask = ah->rxchainmask; 888 889 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 890 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 891 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 892 } 893 } 894 895 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 896 struct ath9k_channel *chan) 897 { 898 u32 pll; 899 900 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 901 902 if (chan && IS_CHAN_HALF_RATE(chan)) 903 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 904 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 905 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 906 907 if (chan && IS_CHAN_5GHZ(chan)) 908 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 909 else 910 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 911 912 return pll; 913 } 914 915 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 916 struct ath9k_channel *chan) 917 { 918 u32 pll; 919 920 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 921 922 if (chan && IS_CHAN_HALF_RATE(chan)) 923 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 924 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 925 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 926 927 if (chan && IS_CHAN_5GHZ(chan)) 928 pll |= SM(0xa, AR_RTC_PLL_DIV); 929 else 930 pll |= SM(0xb, AR_RTC_PLL_DIV); 931 932 return pll; 933 } 934 935 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 936 enum ath9k_ani_cmd cmd, 937 int param) 938 { 939 struct ath_common *common = ath9k_hw_common(ah); 940 struct ath9k_channel *chan = ah->curchan; 941 struct ar5416AniState *aniState = &ah->ani; 942 s32 value; 943 944 switch (cmd & ah->ani_function) { 945 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 946 /* 947 * on == 1 means ofdm weak signal detection is ON 948 * on == 1 is the default, for less noise immunity 949 * 950 * on == 0 means ofdm weak signal detection is OFF 951 * on == 0 means more noise imm 952 */ 953 u32 on = param ? 1 : 0; 954 /* 955 * make register setting for default 956 * (weak sig detect ON) come from INI file 957 */ 958 int m1ThreshLow = on ? 959 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 960 int m2ThreshLow = on ? 961 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 962 int m1Thresh = on ? 963 aniState->iniDef.m1Thresh : m1Thresh_off; 964 int m2Thresh = on ? 965 aniState->iniDef.m2Thresh : m2Thresh_off; 966 int m2CountThr = on ? 967 aniState->iniDef.m2CountThr : m2CountThr_off; 968 int m2CountThrLow = on ? 969 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 970 int m1ThreshLowExt = on ? 971 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 972 int m2ThreshLowExt = on ? 973 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 974 int m1ThreshExt = on ? 975 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 976 int m2ThreshExt = on ? 977 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 978 979 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 980 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 981 m1ThreshLow); 982 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 983 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 984 m2ThreshLow); 985 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 986 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 987 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 988 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 989 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 990 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 991 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 992 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 993 m2CountThrLow); 994 995 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 996 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 997 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 998 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 999 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1000 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1001 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1002 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1003 1004 if (on) 1005 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1006 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1007 else 1008 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1009 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1010 1011 if (on != aniState->ofdmWeakSigDetect) { 1012 ath_dbg(common, ANI, 1013 "** ch %d: ofdm weak signal: %s=>%s\n", 1014 chan->channel, 1015 aniState->ofdmWeakSigDetect ? 1016 "on" : "off", 1017 on ? "on" : "off"); 1018 if (on) 1019 ah->stats.ast_ani_ofdmon++; 1020 else 1021 ah->stats.ast_ani_ofdmoff++; 1022 aniState->ofdmWeakSigDetect = on; 1023 } 1024 break; 1025 } 1026 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1027 u32 level = param; 1028 1029 value = level * 2; 1030 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1031 AR_PHY_FIND_SIG_FIRSTEP, value); 1032 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1033 AR_PHY_FIND_SIG_FIRSTEP_LOW, value); 1034 1035 if (level != aniState->firstepLevel) { 1036 ath_dbg(common, ANI, 1037 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1038 chan->channel, 1039 aniState->firstepLevel, 1040 level, 1041 ATH9K_ANI_FIRSTEP_LVL, 1042 value, 1043 aniState->iniDef.firstep); 1044 ath_dbg(common, ANI, 1045 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1046 chan->channel, 1047 aniState->firstepLevel, 1048 level, 1049 ATH9K_ANI_FIRSTEP_LVL, 1050 value, 1051 aniState->iniDef.firstepLow); 1052 if (level > aniState->firstepLevel) 1053 ah->stats.ast_ani_stepup++; 1054 else if (level < aniState->firstepLevel) 1055 ah->stats.ast_ani_stepdown++; 1056 aniState->firstepLevel = level; 1057 } 1058 break; 1059 } 1060 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1061 u32 level = param; 1062 1063 value = (level + 1) * 2; 1064 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1065 AR_PHY_TIMING5_CYCPWR_THR1, value); 1066 1067 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1068 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); 1069 1070 if (level != aniState->spurImmunityLevel) { 1071 ath_dbg(common, ANI, 1072 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1073 chan->channel, 1074 aniState->spurImmunityLevel, 1075 level, 1076 ATH9K_ANI_SPUR_IMMUNE_LVL, 1077 value, 1078 aniState->iniDef.cycpwrThr1); 1079 ath_dbg(common, ANI, 1080 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1081 chan->channel, 1082 aniState->spurImmunityLevel, 1083 level, 1084 ATH9K_ANI_SPUR_IMMUNE_LVL, 1085 value, 1086 aniState->iniDef.cycpwrThr1Ext); 1087 if (level > aniState->spurImmunityLevel) 1088 ah->stats.ast_ani_spurup++; 1089 else if (level < aniState->spurImmunityLevel) 1090 ah->stats.ast_ani_spurdown++; 1091 aniState->spurImmunityLevel = level; 1092 } 1093 break; 1094 } 1095 case ATH9K_ANI_MRC_CCK: 1096 /* 1097 * You should not see this as AR5008, AR9001, AR9002 1098 * does not have hardware support for MRC CCK. 1099 */ 1100 WARN_ON(1); 1101 break; 1102 default: 1103 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1104 return false; 1105 } 1106 1107 ath_dbg(common, ANI, 1108 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1109 aniState->spurImmunityLevel, 1110 aniState->ofdmWeakSigDetect ? "on" : "off", 1111 aniState->firstepLevel, 1112 aniState->mrcCCK ? "on" : "off", 1113 aniState->listenTime, 1114 aniState->ofdmPhyErrCount, 1115 aniState->cckPhyErrCount); 1116 return true; 1117 } 1118 1119 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1120 int16_t nfarray[NUM_NF_READINGS]) 1121 { 1122 int16_t nf; 1123 1124 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1125 nfarray[0] = sign_extend32(nf, 8); 1126 1127 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1128 nfarray[1] = sign_extend32(nf, 8); 1129 1130 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1131 nfarray[2] = sign_extend32(nf, 8); 1132 1133 if (!IS_CHAN_HT40(ah->curchan)) 1134 return; 1135 1136 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1137 nfarray[3] = sign_extend32(nf, 8); 1138 1139 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1140 nfarray[4] = sign_extend32(nf, 8); 1141 1142 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1143 nfarray[5] = sign_extend32(nf, 8); 1144 } 1145 1146 /* 1147 * Initialize the ANI register values with default (ini) values. 1148 * This routine is called during a (full) hardware reset after 1149 * all the registers are initialised from the INI. 1150 */ 1151 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1152 { 1153 struct ath_common *common = ath9k_hw_common(ah); 1154 struct ath9k_channel *chan = ah->curchan; 1155 struct ar5416AniState *aniState = &ah->ani; 1156 struct ath9k_ani_default *iniDef; 1157 u32 val; 1158 1159 iniDef = &aniState->iniDef; 1160 1161 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1162 ah->hw_version.macVersion, 1163 ah->hw_version.macRev, 1164 ah->opmode, 1165 chan->channel); 1166 1167 val = REG_READ(ah, AR_PHY_SFCORR); 1168 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1169 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1170 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1171 1172 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1173 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1174 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1175 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1176 1177 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1178 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1179 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1180 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1181 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1182 iniDef->firstep = REG_READ_FIELD(ah, 1183 AR_PHY_FIND_SIG, 1184 AR_PHY_FIND_SIG_FIRSTEP); 1185 iniDef->firstepLow = REG_READ_FIELD(ah, 1186 AR_PHY_FIND_SIG_LOW, 1187 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1188 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1189 AR_PHY_TIMING5, 1190 AR_PHY_TIMING5_CYCPWR_THR1); 1191 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1192 AR_PHY_EXT_CCA, 1193 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1194 1195 /* these levels just got reset to defaults by the INI */ 1196 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1197 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1198 aniState->ofdmWeakSigDetect = true; 1199 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1200 } 1201 1202 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1203 { 1204 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1205 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1206 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1207 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1208 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1209 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1210 } 1211 1212 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1213 struct ath_hw_radar_conf *conf) 1214 { 1215 u32 radar_0 = 0, radar_1; 1216 1217 if (!conf) { 1218 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1219 return; 1220 } 1221 1222 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1223 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1224 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1225 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1226 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1227 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1228 1229 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1230 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1231 AR_PHY_RADAR_1_RELPWR_THRESH); 1232 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1233 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1234 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1235 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1236 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1237 1238 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1239 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1240 if (conf->ext_channel) 1241 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1242 else 1243 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1244 } 1245 1246 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1247 { 1248 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1249 1250 conf->fir_power = -33; 1251 conf->radar_rssi = 20; 1252 conf->pulse_height = 10; 1253 conf->pulse_rssi = 15; 1254 conf->pulse_inband = 15; 1255 conf->pulse_maxlen = 255; 1256 conf->pulse_inband_step = 12; 1257 conf->radar_inband = 8; 1258 } 1259 1260 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) 1261 { 1262 #define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x)) 1263 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); 1264 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], 1265 rate_array[rate2s])); 1266 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], 1267 rate_array[rate5_5s])); 1268 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], 1269 rate_array[rate11s])); 1270 #undef CCK_DELTA 1271 } 1272 1273 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, 1274 int offset) 1275 { 1276 int i, idx = 0; 1277 1278 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) { 1279 ah->tx_power[i] = rate_array[idx]; 1280 idx++; 1281 } 1282 } 1283 1284 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, 1285 int ss_offset, int ds_offset, 1286 bool is_40, int ht40_delta) 1287 { 1288 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT; 1289 1290 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) { 1291 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; 1292 mcs_idx++; 1293 } 1294 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], 1295 AR5008_HT_SS_RATES); 1296 } 1297 1298 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1299 struct ath9k_channel *chan, int ht40_delta) 1300 { 1301 if (IS_CHAN_5GHZ(chan)) { 1302 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1303 AR5008_11NA_OFDM_SHIFT); 1304 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1305 ar5008_hw_init_txpower_ht(ah, rate_array, 1306 AR5008_11NA_HT_SS_SHIFT, 1307 AR5008_11NA_HT_DS_SHIFT, 1308 IS_CHAN_HT40(chan), 1309 ht40_delta); 1310 } 1311 } else { 1312 ar5008_hw_init_txpower_cck(ah, rate_array); 1313 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1314 AR5008_11NG_OFDM_SHIFT); 1315 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1316 ar5008_hw_init_txpower_ht(ah, rate_array, 1317 AR5008_11NG_HT_SS_SHIFT, 1318 AR5008_11NG_HT_DS_SHIFT, 1319 IS_CHAN_HT40(chan), 1320 ht40_delta); 1321 } 1322 } 1323 } 1324 1325 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1326 { 1327 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1328 static const u32 ar5416_cca_regs[6] = { 1329 AR_PHY_CCA, 1330 AR_PHY_CH1_CCA, 1331 AR_PHY_CH2_CCA, 1332 AR_PHY_EXT_CCA, 1333 AR_PHY_CH1_EXT_CCA, 1334 AR_PHY_CH2_EXT_CCA 1335 }; 1336 int ret; 1337 1338 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1339 if (ret) 1340 return ret; 1341 1342 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1343 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1344 1345 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1346 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1347 priv_ops->init_bb = ar5008_hw_init_bb; 1348 priv_ops->process_ini = ar5008_hw_process_ini; 1349 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1350 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1351 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1352 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1353 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1354 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1355 priv_ops->do_getnf = ar5008_hw_do_getnf; 1356 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1357 1358 priv_ops->ani_control = ar5008_hw_ani_control_new; 1359 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1360 1361 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1362 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1363 else 1364 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1365 1366 ar5008_hw_set_nf_limits(ah); 1367 ar5008_hw_set_radar_conf(ah); 1368 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1369 return 0; 1370 } 1371