1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 #include "ar5008_initvals.h" 22 23 /* All code below is for AR5008, AR9001, AR9002 */ 24 25 static const int firstep_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 28 29 static const int cycpwrThr1_table[] = 30 /* level: 0 1 2 3 4 5 6 7 8 */ 31 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 32 33 /* 34 * register values to turn OFDM weak signal detection OFF 35 */ 36 static const int m1ThreshLow_off = 127; 37 static const int m2ThreshLow_off = 127; 38 static const int m1Thresh_off = 127; 39 static const int m2Thresh_off = 127; 40 static const int m2CountThr_off = 31; 41 static const int m2CountThrLow_off = 63; 42 static const int m1ThreshLowExt_off = 127; 43 static const int m2ThreshLowExt_off = 127; 44 static const int m1ThreshExt_off = 127; 45 static const int m2ThreshExt_off = 127; 46 47 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 48 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 49 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 50 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 51 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 52 53 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 54 { 55 struct ar5416IniArray *array = &ah->iniBank6; 56 u32 *data = ah->analogBank6Data; 57 int r; 58 59 ENABLE_REGWRITE_BUFFER(ah); 60 61 for (r = 0; r < array->ia_rows; r++) { 62 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 63 DO_DELAY(*writecnt); 64 } 65 66 REGWRITE_BUFFER_FLUSH(ah); 67 } 68 69 /** 70 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 71 * @rfbuf: 72 * @reg32: 73 * @numBits: 74 * @firstBit: 75 * @column: 76 * 77 * Performs analog "swizzling" of parameters into their location. 78 * Used on external AR2133/AR5133 radios. 79 */ 80 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 81 u32 numBits, u32 firstBit, 82 u32 column) 83 { 84 u32 tmp32, mask, arrayEntry, lastBit; 85 int32_t bitPosition, bitsLeft; 86 87 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 88 arrayEntry = (firstBit - 1) / 8; 89 bitPosition = (firstBit - 1) % 8; 90 bitsLeft = numBits; 91 while (bitsLeft > 0) { 92 lastBit = (bitPosition + bitsLeft > 8) ? 93 8 : bitPosition + bitsLeft; 94 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 95 (column * 8); 96 rfBuf[arrayEntry] &= ~mask; 97 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 98 (column * 8)) & mask; 99 bitsLeft -= 8 - bitPosition; 100 tmp32 = tmp32 >> (8 - bitPosition); 101 bitPosition = 0; 102 arrayEntry++; 103 } 104 } 105 106 /* 107 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 108 * rf_pwd_icsyndiv. 109 * 110 * Theoretical Rules: 111 * if 2 GHz band 112 * if forceBiasAuto 113 * if synth_freq < 2412 114 * bias = 0 115 * else if 2412 <= synth_freq <= 2422 116 * bias = 1 117 * else // synth_freq > 2422 118 * bias = 2 119 * else if forceBias > 0 120 * bias = forceBias & 7 121 * else 122 * no change, use value from ini file 123 * else 124 * no change, invalid band 125 * 126 * 1st Mod: 127 * 2422 also uses value of 2 128 * <approved> 129 * 130 * 2nd Mod: 131 * Less than 2412 uses value of 0, 2412 and above uses value of 2 132 */ 133 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 134 { 135 struct ath_common *common = ath9k_hw_common(ah); 136 u32 tmp_reg; 137 int reg_writes = 0; 138 u32 new_bias = 0; 139 140 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 141 return; 142 143 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 144 145 if (synth_freq < 2412) 146 new_bias = 0; 147 else if (synth_freq < 2422) 148 new_bias = 1; 149 else 150 new_bias = 2; 151 152 /* pre-reverse this field */ 153 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 154 155 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 156 new_bias, synth_freq); 157 158 /* swizzle rf_pwd_icsyndiv */ 159 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 160 161 /* write Bank 6 with new params */ 162 ar5008_write_bank6(ah, ®_writes); 163 } 164 165 /** 166 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 167 * @ah: atheros hardware structure 168 * @chan: 169 * 170 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 171 * the channel value. Assumes writes enabled to analog bus and bank6 register 172 * cache in ah->analogBank6Data. 173 */ 174 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 175 { 176 struct ath_common *common = ath9k_hw_common(ah); 177 u32 channelSel = 0; 178 u32 bModeSynth = 0; 179 u32 aModeRefSel = 0; 180 u32 reg32 = 0; 181 u16 freq; 182 struct chan_centers centers; 183 184 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 185 freq = centers.synth_center; 186 187 if (freq < 4800) { 188 u32 txctl; 189 190 if (((freq - 2192) % 5) == 0) { 191 channelSel = ((freq - 672) * 2 - 3040) / 10; 192 bModeSynth = 0; 193 } else if (((freq - 2224) % 5) == 0) { 194 channelSel = ((freq - 704) * 2 - 3040) / 10; 195 bModeSynth = 1; 196 } else { 197 ath_err(common, "Invalid channel %u MHz\n", freq); 198 return -EINVAL; 199 } 200 201 channelSel = (channelSel << 2) & 0xff; 202 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 203 204 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 205 if (freq == 2484) { 206 207 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 208 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 209 } else { 210 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 211 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 212 } 213 214 } else if ((freq % 20) == 0 && freq >= 5120) { 215 channelSel = 216 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 217 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 218 } else if ((freq % 10) == 0) { 219 channelSel = 220 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 221 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 222 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 223 else 224 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 225 } else if ((freq % 5) == 0) { 226 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 227 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 228 } else { 229 ath_err(common, "Invalid channel %u MHz\n", freq); 230 return -EINVAL; 231 } 232 233 ar5008_hw_force_bias(ah, freq); 234 235 reg32 = 236 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 237 (1 << 5) | 0x1; 238 239 REG_WRITE(ah, AR_PHY(0x37), reg32); 240 241 ah->curchan = chan; 242 243 return 0; 244 } 245 246 /** 247 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 248 * @ah: atheros hardware structure 249 * @chan: 250 * 251 * For non single-chip solutions. Converts to baseband spur frequency given the 252 * input channel frequency and compute register settings below. 253 */ 254 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 255 struct ath9k_channel *chan) 256 { 257 int bb_spur = AR_NO_SPUR; 258 int bin, cur_bin; 259 int spur_freq_sd; 260 int spur_delta_phase; 261 int denominator; 262 int upper, lower, cur_vit_mask; 263 int tmp, new; 264 int i; 265 static int pilot_mask_reg[4] = { 266 AR_PHY_TIMING7, AR_PHY_TIMING8, 267 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 268 }; 269 static int chan_mask_reg[4] = { 270 AR_PHY_TIMING9, AR_PHY_TIMING10, 271 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 272 }; 273 static int inc[4] = { 0, 100, 0, 0 }; 274 275 int8_t mask_m[123]; 276 int8_t mask_p[123]; 277 int8_t mask_amt; 278 int tmp_mask; 279 int cur_bb_spur; 280 bool is2GHz = IS_CHAN_2GHZ(chan); 281 282 memset(&mask_m, 0, sizeof(int8_t) * 123); 283 memset(&mask_p, 0, sizeof(int8_t) * 123); 284 285 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 286 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 287 if (AR_NO_SPUR == cur_bb_spur) 288 break; 289 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 290 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 291 bb_spur = cur_bb_spur; 292 break; 293 } 294 } 295 296 if (AR_NO_SPUR == bb_spur) 297 return; 298 299 bin = bb_spur * 32; 300 301 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 302 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 303 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 304 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 305 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 306 307 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 308 309 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 310 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 311 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 312 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 313 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 314 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 315 316 spur_delta_phase = ((bb_spur * 524288) / 100) & 317 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 318 319 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 320 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 321 322 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 323 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 324 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 325 REG_WRITE(ah, AR_PHY_TIMING11, new); 326 327 cur_bin = -6000; 328 upper = bin + 100; 329 lower = bin - 100; 330 331 for (i = 0; i < 4; i++) { 332 int pilot_mask = 0; 333 int chan_mask = 0; 334 int bp = 0; 335 for (bp = 0; bp < 30; bp++) { 336 if ((cur_bin > lower) && (cur_bin < upper)) { 337 pilot_mask = pilot_mask | 0x1 << bp; 338 chan_mask = chan_mask | 0x1 << bp; 339 } 340 cur_bin += 100; 341 } 342 cur_bin += inc[i]; 343 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 344 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 345 } 346 347 cur_vit_mask = 6100; 348 upper = bin + 120; 349 lower = bin - 120; 350 351 for (i = 0; i < 123; i++) { 352 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 353 354 /* workaround for gcc bug #37014 */ 355 volatile int tmp_v = abs(cur_vit_mask - bin); 356 357 if (tmp_v < 75) 358 mask_amt = 1; 359 else 360 mask_amt = 0; 361 if (cur_vit_mask < 0) 362 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 363 else 364 mask_p[cur_vit_mask / 100] = mask_amt; 365 } 366 cur_vit_mask -= 100; 367 } 368 369 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 370 | (mask_m[48] << 26) | (mask_m[49] << 24) 371 | (mask_m[50] << 22) | (mask_m[51] << 20) 372 | (mask_m[52] << 18) | (mask_m[53] << 16) 373 | (mask_m[54] << 14) | (mask_m[55] << 12) 374 | (mask_m[56] << 10) | (mask_m[57] << 8) 375 | (mask_m[58] << 6) | (mask_m[59] << 4) 376 | (mask_m[60] << 2) | (mask_m[61] << 0); 377 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 378 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 379 380 tmp_mask = (mask_m[31] << 28) 381 | (mask_m[32] << 26) | (mask_m[33] << 24) 382 | (mask_m[34] << 22) | (mask_m[35] << 20) 383 | (mask_m[36] << 18) | (mask_m[37] << 16) 384 | (mask_m[48] << 14) | (mask_m[39] << 12) 385 | (mask_m[40] << 10) | (mask_m[41] << 8) 386 | (mask_m[42] << 6) | (mask_m[43] << 4) 387 | (mask_m[44] << 2) | (mask_m[45] << 0); 388 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 389 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 390 391 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 392 | (mask_m[18] << 26) | (mask_m[18] << 24) 393 | (mask_m[20] << 22) | (mask_m[20] << 20) 394 | (mask_m[22] << 18) | (mask_m[22] << 16) 395 | (mask_m[24] << 14) | (mask_m[24] << 12) 396 | (mask_m[25] << 10) | (mask_m[26] << 8) 397 | (mask_m[27] << 6) | (mask_m[28] << 4) 398 | (mask_m[29] << 2) | (mask_m[30] << 0); 399 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 400 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 401 402 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 403 | (mask_m[2] << 26) | (mask_m[3] << 24) 404 | (mask_m[4] << 22) | (mask_m[5] << 20) 405 | (mask_m[6] << 18) | (mask_m[7] << 16) 406 | (mask_m[8] << 14) | (mask_m[9] << 12) 407 | (mask_m[10] << 10) | (mask_m[11] << 8) 408 | (mask_m[12] << 6) | (mask_m[13] << 4) 409 | (mask_m[14] << 2) | (mask_m[15] << 0); 410 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 411 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 412 413 tmp_mask = (mask_p[15] << 28) 414 | (mask_p[14] << 26) | (mask_p[13] << 24) 415 | (mask_p[12] << 22) | (mask_p[11] << 20) 416 | (mask_p[10] << 18) | (mask_p[9] << 16) 417 | (mask_p[8] << 14) | (mask_p[7] << 12) 418 | (mask_p[6] << 10) | (mask_p[5] << 8) 419 | (mask_p[4] << 6) | (mask_p[3] << 4) 420 | (mask_p[2] << 2) | (mask_p[1] << 0); 421 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 422 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 423 424 tmp_mask = (mask_p[30] << 28) 425 | (mask_p[29] << 26) | (mask_p[28] << 24) 426 | (mask_p[27] << 22) | (mask_p[26] << 20) 427 | (mask_p[25] << 18) | (mask_p[24] << 16) 428 | (mask_p[23] << 14) | (mask_p[22] << 12) 429 | (mask_p[21] << 10) | (mask_p[20] << 8) 430 | (mask_p[19] << 6) | (mask_p[18] << 4) 431 | (mask_p[17] << 2) | (mask_p[16] << 0); 432 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 433 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 434 435 tmp_mask = (mask_p[45] << 28) 436 | (mask_p[44] << 26) | (mask_p[43] << 24) 437 | (mask_p[42] << 22) | (mask_p[41] << 20) 438 | (mask_p[40] << 18) | (mask_p[39] << 16) 439 | (mask_p[38] << 14) | (mask_p[37] << 12) 440 | (mask_p[36] << 10) | (mask_p[35] << 8) 441 | (mask_p[34] << 6) | (mask_p[33] << 4) 442 | (mask_p[32] << 2) | (mask_p[31] << 0); 443 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 444 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 445 446 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 447 | (mask_p[59] << 26) | (mask_p[58] << 24) 448 | (mask_p[57] << 22) | (mask_p[56] << 20) 449 | (mask_p[55] << 18) | (mask_p[54] << 16) 450 | (mask_p[53] << 14) | (mask_p[52] << 12) 451 | (mask_p[51] << 10) | (mask_p[50] << 8) 452 | (mask_p[49] << 6) | (mask_p[48] << 4) 453 | (mask_p[47] << 2) | (mask_p[46] << 0); 454 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 455 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 456 } 457 458 /** 459 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 460 * @ah: atheros hardware structure 461 * 462 * Only required for older devices with external AR2133/AR5133 radios. 463 */ 464 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 465 { 466 int size = ah->iniBank6.ia_rows * sizeof(u32); 467 468 if (AR_SREV_9280_20_OR_LATER(ah)) 469 return 0; 470 471 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 472 if (!ah->analogBank6Data) 473 return -ENOMEM; 474 475 return 0; 476 } 477 478 479 /* * 480 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 481 * @ah: atheros hardware structure 482 * @chan: 483 * @modesIndex: 484 * 485 * Used for the external AR2133/AR5133 radios. 486 * 487 * Reads the EEPROM header info from the device structure and programs 488 * all rf registers. This routine requires access to the analog 489 * rf device. This is not required for single-chip devices. 490 */ 491 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 492 struct ath9k_channel *chan, 493 u16 modesIndex) 494 { 495 u32 eepMinorRev; 496 u32 ob5GHz = 0, db5GHz = 0; 497 u32 ob2GHz = 0, db2GHz = 0; 498 int regWrites = 0; 499 int i; 500 501 /* 502 * Software does not need to program bank data 503 * for single chip devices, that is AR9280 or anything 504 * after that. 505 */ 506 if (AR_SREV_9280_20_OR_LATER(ah)) 507 return true; 508 509 /* Setup rf parameters */ 510 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 511 512 for (i = 0; i < ah->iniBank6.ia_rows; i++) 513 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 514 515 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 516 if (eepMinorRev >= 2) { 517 if (IS_CHAN_2GHZ(chan)) { 518 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 519 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 520 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 521 ob2GHz, 3, 197, 0); 522 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 523 db2GHz, 3, 194, 0); 524 } else { 525 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 526 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 527 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 528 ob5GHz, 3, 203, 0); 529 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 530 db5GHz, 3, 200, 0); 531 } 532 } 533 534 /* Write Analog registers */ 535 REG_WRITE_ARRAY(&bank0, 1, regWrites); 536 REG_WRITE_ARRAY(&bank1, 1, regWrites); 537 REG_WRITE_ARRAY(&bank2, 1, regWrites); 538 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 539 ar5008_write_bank6(ah, ®Writes); 540 REG_WRITE_ARRAY(&bank7, 1, regWrites); 541 542 return true; 543 } 544 545 static void ar5008_hw_init_bb(struct ath_hw *ah, 546 struct ath9k_channel *chan) 547 { 548 u32 synthDelay; 549 550 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 551 552 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 553 554 ath9k_hw_synth_delay(ah, chan, synthDelay); 555 } 556 557 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 558 { 559 int rx_chainmask, tx_chainmask; 560 561 rx_chainmask = ah->rxchainmask; 562 tx_chainmask = ah->txchainmask; 563 564 565 switch (rx_chainmask) { 566 case 0x5: 567 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 568 AR_PHY_SWAP_ALT_CHAIN); 569 case 0x3: 570 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 571 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 572 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 573 break; 574 } 575 case 0x1: 576 case 0x2: 577 case 0x7: 578 ENABLE_REGWRITE_BUFFER(ah); 579 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 580 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 581 break; 582 default: 583 ENABLE_REGWRITE_BUFFER(ah); 584 break; 585 } 586 587 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 588 589 REGWRITE_BUFFER_FLUSH(ah); 590 591 if (tx_chainmask == 0x5) { 592 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 593 AR_PHY_SWAP_ALT_CHAIN); 594 } 595 if (AR_SREV_9100(ah)) 596 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 597 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 598 } 599 600 static void ar5008_hw_override_ini(struct ath_hw *ah, 601 struct ath9k_channel *chan) 602 { 603 u32 val; 604 605 /* 606 * Set the RX_ABORT and RX_DIS and clear if off only after 607 * RXE is set for MAC. This prevents frames with corrupted 608 * descriptor status. 609 */ 610 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 611 612 if (AR_SREV_9280_20_OR_LATER(ah)) { 613 val = REG_READ(ah, AR_PCU_MISC_MODE2); 614 615 if (!AR_SREV_9271(ah)) 616 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 617 618 if (AR_SREV_9287_11_OR_LATER(ah)) 619 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 620 621 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 622 } 623 624 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 625 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 626 627 if (AR_SREV_9280_20_OR_LATER(ah)) 628 return; 629 /* 630 * Disable BB clock gating 631 * Necessary to avoid issues on AR5416 2.0 632 */ 633 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 634 635 /* 636 * Disable RIFS search on some chips to avoid baseband 637 * hang issues. 638 */ 639 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 640 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 641 val &= ~AR_PHY_RIFS_INIT_DELAY; 642 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 643 } 644 } 645 646 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 647 struct ath9k_channel *chan) 648 { 649 u32 phymode; 650 u32 enableDacFifo = 0; 651 652 if (AR_SREV_9285_12_OR_LATER(ah)) 653 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 654 AR_PHY_FC_ENABLE_DAC_FIFO); 655 656 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 657 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 658 659 if (IS_CHAN_HT40(chan)) { 660 phymode |= AR_PHY_FC_DYN2040_EN; 661 662 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 663 (chan->chanmode == CHANNEL_G_HT40PLUS)) 664 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 665 666 } 667 REG_WRITE(ah, AR_PHY_TURBO, phymode); 668 669 ath9k_hw_set11nmac2040(ah); 670 671 ENABLE_REGWRITE_BUFFER(ah); 672 673 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 674 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 675 676 REGWRITE_BUFFER_FLUSH(ah); 677 } 678 679 680 static int ar5008_hw_process_ini(struct ath_hw *ah, 681 struct ath9k_channel *chan) 682 { 683 struct ath_common *common = ath9k_hw_common(ah); 684 int i, regWrites = 0; 685 u32 modesIndex, freqIndex; 686 687 switch (chan->chanmode) { 688 case CHANNEL_A: 689 case CHANNEL_A_HT20: 690 modesIndex = 1; 691 freqIndex = 1; 692 break; 693 case CHANNEL_A_HT40PLUS: 694 case CHANNEL_A_HT40MINUS: 695 modesIndex = 2; 696 freqIndex = 1; 697 break; 698 case CHANNEL_G: 699 case CHANNEL_G_HT20: 700 case CHANNEL_B: 701 modesIndex = 4; 702 freqIndex = 2; 703 break; 704 case CHANNEL_G_HT40PLUS: 705 case CHANNEL_G_HT40MINUS: 706 modesIndex = 3; 707 freqIndex = 2; 708 break; 709 710 default: 711 return -EINVAL; 712 } 713 714 /* 715 * Set correct baseband to analog shift setting to 716 * access analog chips. 717 */ 718 REG_WRITE(ah, AR_PHY(0), 0x00000007); 719 720 /* Write ADDAC shifts */ 721 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 722 if (ah->eep_ops->set_addac) 723 ah->eep_ops->set_addac(ah, chan); 724 725 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 726 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 727 728 ENABLE_REGWRITE_BUFFER(ah); 729 730 for (i = 0; i < ah->iniModes.ia_rows; i++) { 731 u32 reg = INI_RA(&ah->iniModes, i, 0); 732 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 733 734 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 735 val &= ~AR_AN_TOP2_PWDCLKIND; 736 737 REG_WRITE(ah, reg, val); 738 739 if (reg >= 0x7800 && reg < 0x78a0 740 && ah->config.analog_shiftreg 741 && (common->bus_ops->ath_bus_type != ATH_USB)) { 742 udelay(100); 743 } 744 745 DO_DELAY(regWrites); 746 } 747 748 REGWRITE_BUFFER_FLUSH(ah); 749 750 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 751 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 752 753 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 754 AR_SREV_9287_11_OR_LATER(ah)) 755 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 756 757 if (AR_SREV_9271_10(ah)) { 758 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 759 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 760 } 761 762 ENABLE_REGWRITE_BUFFER(ah); 763 764 /* Write common array parameters */ 765 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 766 u32 reg = INI_RA(&ah->iniCommon, i, 0); 767 u32 val = INI_RA(&ah->iniCommon, i, 1); 768 769 REG_WRITE(ah, reg, val); 770 771 if (reg >= 0x7800 && reg < 0x78a0 772 && ah->config.analog_shiftreg 773 && (common->bus_ops->ath_bus_type != ATH_USB)) { 774 udelay(100); 775 } 776 777 DO_DELAY(regWrites); 778 } 779 780 REGWRITE_BUFFER_FLUSH(ah); 781 782 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 783 784 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 785 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 786 regWrites); 787 788 ar5008_hw_override_ini(ah, chan); 789 ar5008_hw_set_channel_regs(ah, chan); 790 ar5008_hw_init_chain_masks(ah); 791 ath9k_olc_init(ah); 792 ath9k_hw_apply_txpower(ah, chan, false); 793 794 /* Write analog registers */ 795 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 796 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 797 return -EIO; 798 } 799 800 return 0; 801 } 802 803 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 804 { 805 u32 rfMode = 0; 806 807 if (chan == NULL) 808 return; 809 810 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 811 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 812 813 if (!AR_SREV_9280_20_OR_LATER(ah)) 814 rfMode |= (IS_CHAN_5GHZ(chan)) ? 815 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 816 817 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 818 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 819 820 REG_WRITE(ah, AR_PHY_MODE, rfMode); 821 } 822 823 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 824 { 825 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 826 } 827 828 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 829 struct ath9k_channel *chan) 830 { 831 u32 coef_scaled, ds_coef_exp, ds_coef_man; 832 u32 clockMhzScaled = 0x64000000; 833 struct chan_centers centers; 834 835 if (IS_CHAN_HALF_RATE(chan)) 836 clockMhzScaled = clockMhzScaled >> 1; 837 else if (IS_CHAN_QUARTER_RATE(chan)) 838 clockMhzScaled = clockMhzScaled >> 2; 839 840 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 841 coef_scaled = clockMhzScaled / centers.synth_center; 842 843 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 844 &ds_coef_exp); 845 846 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 847 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 848 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 849 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 850 851 coef_scaled = (9 * coef_scaled) / 10; 852 853 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 854 &ds_coef_exp); 855 856 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 857 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 858 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 859 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 860 } 861 862 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 863 { 864 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 865 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 866 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 867 } 868 869 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 870 { 871 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 872 873 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 874 875 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 876 } 877 878 static void ar5008_restore_chainmask(struct ath_hw *ah) 879 { 880 int rx_chainmask = ah->rxchainmask; 881 882 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 883 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 884 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 885 } 886 } 887 888 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 889 struct ath9k_channel *chan) 890 { 891 u32 pll; 892 893 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 894 895 if (chan && IS_CHAN_HALF_RATE(chan)) 896 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 897 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 898 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 899 900 if (chan && IS_CHAN_5GHZ(chan)) 901 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 902 else 903 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 904 905 return pll; 906 } 907 908 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 909 struct ath9k_channel *chan) 910 { 911 u32 pll; 912 913 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 914 915 if (chan && IS_CHAN_HALF_RATE(chan)) 916 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 917 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 918 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 919 920 if (chan && IS_CHAN_5GHZ(chan)) 921 pll |= SM(0xa, AR_RTC_PLL_DIV); 922 else 923 pll |= SM(0xb, AR_RTC_PLL_DIV); 924 925 return pll; 926 } 927 928 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 929 enum ath9k_ani_cmd cmd, 930 int param) 931 { 932 struct ath_common *common = ath9k_hw_common(ah); 933 struct ath9k_channel *chan = ah->curchan; 934 struct ar5416AniState *aniState = &chan->ani; 935 s32 value, value2; 936 937 switch (cmd & ah->ani_function) { 938 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 939 /* 940 * on == 1 means ofdm weak signal detection is ON 941 * on == 1 is the default, for less noise immunity 942 * 943 * on == 0 means ofdm weak signal detection is OFF 944 * on == 0 means more noise imm 945 */ 946 u32 on = param ? 1 : 0; 947 /* 948 * make register setting for default 949 * (weak sig detect ON) come from INI file 950 */ 951 int m1ThreshLow = on ? 952 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 953 int m2ThreshLow = on ? 954 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 955 int m1Thresh = on ? 956 aniState->iniDef.m1Thresh : m1Thresh_off; 957 int m2Thresh = on ? 958 aniState->iniDef.m2Thresh : m2Thresh_off; 959 int m2CountThr = on ? 960 aniState->iniDef.m2CountThr : m2CountThr_off; 961 int m2CountThrLow = on ? 962 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 963 int m1ThreshLowExt = on ? 964 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 965 int m2ThreshLowExt = on ? 966 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 967 int m1ThreshExt = on ? 968 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 969 int m2ThreshExt = on ? 970 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 971 972 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 973 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 974 m1ThreshLow); 975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 976 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 977 m2ThreshLow); 978 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 979 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 980 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 981 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 982 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 983 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 984 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 985 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 986 m2CountThrLow); 987 988 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 989 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 990 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 991 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 992 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 993 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 994 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 995 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 996 997 if (on) 998 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 999 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1000 else 1001 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1002 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1003 1004 if (on != aniState->ofdmWeakSigDetect) { 1005 ath_dbg(common, ANI, 1006 "** ch %d: ofdm weak signal: %s=>%s\n", 1007 chan->channel, 1008 aniState->ofdmWeakSigDetect ? 1009 "on" : "off", 1010 on ? "on" : "off"); 1011 if (on) 1012 ah->stats.ast_ani_ofdmon++; 1013 else 1014 ah->stats.ast_ani_ofdmoff++; 1015 aniState->ofdmWeakSigDetect = on; 1016 } 1017 break; 1018 } 1019 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1020 u32 level = param; 1021 1022 if (level >= ARRAY_SIZE(firstep_table)) { 1023 ath_dbg(common, ANI, 1024 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1025 level, ARRAY_SIZE(firstep_table)); 1026 return false; 1027 } 1028 1029 /* 1030 * make register setting relative to default 1031 * from INI file & cap value 1032 */ 1033 value = firstep_table[level] - 1034 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1035 aniState->iniDef.firstep; 1036 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1037 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1038 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1039 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1040 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1041 AR_PHY_FIND_SIG_FIRSTEP, 1042 value); 1043 /* 1044 * we need to set first step low register too 1045 * make register setting relative to default 1046 * from INI file & cap value 1047 */ 1048 value2 = firstep_table[level] - 1049 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1050 aniState->iniDef.firstepLow; 1051 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1052 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1053 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1054 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1055 1056 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1057 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); 1058 1059 if (level != aniState->firstepLevel) { 1060 ath_dbg(common, ANI, 1061 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1062 chan->channel, 1063 aniState->firstepLevel, 1064 level, 1065 ATH9K_ANI_FIRSTEP_LVL, 1066 value, 1067 aniState->iniDef.firstep); 1068 ath_dbg(common, ANI, 1069 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1070 chan->channel, 1071 aniState->firstepLevel, 1072 level, 1073 ATH9K_ANI_FIRSTEP_LVL, 1074 value2, 1075 aniState->iniDef.firstepLow); 1076 if (level > aniState->firstepLevel) 1077 ah->stats.ast_ani_stepup++; 1078 else if (level < aniState->firstepLevel) 1079 ah->stats.ast_ani_stepdown++; 1080 aniState->firstepLevel = level; 1081 } 1082 break; 1083 } 1084 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1085 u32 level = param; 1086 1087 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1088 ath_dbg(common, ANI, 1089 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1090 level, ARRAY_SIZE(cycpwrThr1_table)); 1091 return false; 1092 } 1093 /* 1094 * make register setting relative to default 1095 * from INI file & cap value 1096 */ 1097 value = cycpwrThr1_table[level] - 1098 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1099 aniState->iniDef.cycpwrThr1; 1100 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1101 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1102 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1103 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1104 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1105 AR_PHY_TIMING5_CYCPWR_THR1, 1106 value); 1107 1108 /* 1109 * set AR_PHY_EXT_CCA for extension channel 1110 * make register setting relative to default 1111 * from INI file & cap value 1112 */ 1113 value2 = cycpwrThr1_table[level] - 1114 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1115 aniState->iniDef.cycpwrThr1Ext; 1116 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1117 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1118 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1119 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1120 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1121 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); 1122 1123 if (level != aniState->spurImmunityLevel) { 1124 ath_dbg(common, ANI, 1125 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1126 chan->channel, 1127 aniState->spurImmunityLevel, 1128 level, 1129 ATH9K_ANI_SPUR_IMMUNE_LVL, 1130 value, 1131 aniState->iniDef.cycpwrThr1); 1132 ath_dbg(common, ANI, 1133 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1134 chan->channel, 1135 aniState->spurImmunityLevel, 1136 level, 1137 ATH9K_ANI_SPUR_IMMUNE_LVL, 1138 value2, 1139 aniState->iniDef.cycpwrThr1Ext); 1140 if (level > aniState->spurImmunityLevel) 1141 ah->stats.ast_ani_spurup++; 1142 else if (level < aniState->spurImmunityLevel) 1143 ah->stats.ast_ani_spurdown++; 1144 aniState->spurImmunityLevel = level; 1145 } 1146 break; 1147 } 1148 case ATH9K_ANI_MRC_CCK: 1149 /* 1150 * You should not see this as AR5008, AR9001, AR9002 1151 * does not have hardware support for MRC CCK. 1152 */ 1153 WARN_ON(1); 1154 break; 1155 case ATH9K_ANI_PRESENT: 1156 break; 1157 default: 1158 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1159 return false; 1160 } 1161 1162 ath_dbg(common, ANI, 1163 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1164 aniState->spurImmunityLevel, 1165 aniState->ofdmWeakSigDetect ? "on" : "off", 1166 aniState->firstepLevel, 1167 aniState->mrcCCK ? "on" : "off", 1168 aniState->listenTime, 1169 aniState->ofdmPhyErrCount, 1170 aniState->cckPhyErrCount); 1171 return true; 1172 } 1173 1174 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1175 int16_t nfarray[NUM_NF_READINGS]) 1176 { 1177 int16_t nf; 1178 1179 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1180 nfarray[0] = sign_extend32(nf, 8); 1181 1182 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1183 nfarray[1] = sign_extend32(nf, 8); 1184 1185 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1186 nfarray[2] = sign_extend32(nf, 8); 1187 1188 if (!IS_CHAN_HT40(ah->curchan)) 1189 return; 1190 1191 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1192 nfarray[3] = sign_extend32(nf, 8); 1193 1194 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1195 nfarray[4] = sign_extend32(nf, 8); 1196 1197 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1198 nfarray[5] = sign_extend32(nf, 8); 1199 } 1200 1201 /* 1202 * Initialize the ANI register values with default (ini) values. 1203 * This routine is called during a (full) hardware reset after 1204 * all the registers are initialised from the INI. 1205 */ 1206 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1207 { 1208 struct ath_common *common = ath9k_hw_common(ah); 1209 struct ath9k_channel *chan = ah->curchan; 1210 struct ar5416AniState *aniState = &chan->ani; 1211 struct ath9k_ani_default *iniDef; 1212 u32 val; 1213 1214 iniDef = &aniState->iniDef; 1215 1216 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1217 ah->hw_version.macVersion, 1218 ah->hw_version.macRev, 1219 ah->opmode, 1220 chan->channel, 1221 chan->channelFlags); 1222 1223 val = REG_READ(ah, AR_PHY_SFCORR); 1224 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1225 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1226 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1227 1228 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1229 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1230 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1231 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1232 1233 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1234 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1235 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1236 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1237 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1238 iniDef->firstep = REG_READ_FIELD(ah, 1239 AR_PHY_FIND_SIG, 1240 AR_PHY_FIND_SIG_FIRSTEP); 1241 iniDef->firstepLow = REG_READ_FIELD(ah, 1242 AR_PHY_FIND_SIG_LOW, 1243 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1244 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1245 AR_PHY_TIMING5, 1246 AR_PHY_TIMING5_CYCPWR_THR1); 1247 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1248 AR_PHY_EXT_CCA, 1249 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1250 1251 /* these levels just got reset to defaults by the INI */ 1252 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1253 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1254 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG; 1255 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1256 } 1257 1258 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1259 { 1260 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1261 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1262 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1263 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1264 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1265 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1266 } 1267 1268 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1269 struct ath_hw_radar_conf *conf) 1270 { 1271 u32 radar_0 = 0, radar_1 = 0; 1272 1273 if (!conf) { 1274 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1275 return; 1276 } 1277 1278 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1279 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1280 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1281 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1282 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1283 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1284 1285 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1286 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1287 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1288 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1289 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1290 1291 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1292 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1293 if (conf->ext_channel) 1294 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1295 else 1296 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1297 } 1298 1299 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1300 { 1301 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1302 1303 conf->fir_power = -33; 1304 conf->radar_rssi = 20; 1305 conf->pulse_height = 10; 1306 conf->pulse_rssi = 24; 1307 conf->pulse_inband = 15; 1308 conf->pulse_maxlen = 255; 1309 conf->pulse_inband_step = 12; 1310 conf->radar_inband = 8; 1311 } 1312 1313 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1314 { 1315 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1316 static const u32 ar5416_cca_regs[6] = { 1317 AR_PHY_CCA, 1318 AR_PHY_CH1_CCA, 1319 AR_PHY_CH2_CCA, 1320 AR_PHY_EXT_CCA, 1321 AR_PHY_CH1_EXT_CCA, 1322 AR_PHY_CH2_EXT_CCA 1323 }; 1324 int ret; 1325 1326 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1327 if (ret) 1328 return ret; 1329 1330 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1331 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1332 1333 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1334 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1335 priv_ops->init_bb = ar5008_hw_init_bb; 1336 priv_ops->process_ini = ar5008_hw_process_ini; 1337 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1338 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1339 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1340 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1341 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1342 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1343 priv_ops->do_getnf = ar5008_hw_do_getnf; 1344 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1345 1346 priv_ops->ani_control = ar5008_hw_ani_control_new; 1347 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1348 1349 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1350 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1351 else 1352 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1353 1354 ar5008_hw_set_nf_limits(ah); 1355 ar5008_hw_set_radar_conf(ah); 1356 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1357 return 0; 1358 } 1359