1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 22 /* All code below is for AR5008, AR9001, AR9002 */ 23 24 static const int firstep_table[] = 25 /* level: 0 1 2 3 4 5 6 7 8 */ 26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 27 28 static const int cycpwrThr1_table[] = 29 /* level: 0 1 2 3 4 5 6 7 8 */ 30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 31 32 /* 33 * register values to turn OFDM weak signal detection OFF 34 */ 35 static const int m1ThreshLow_off = 127; 36 static const int m2ThreshLow_off = 127; 37 static const int m1Thresh_off = 127; 38 static const int m2Thresh_off = 127; 39 static const int m2CountThr_off = 31; 40 static const int m2CountThrLow_off = 63; 41 static const int m1ThreshLowExt_off = 127; 42 static const int m2ThreshLowExt_off = 127; 43 static const int m1ThreshExt_off = 127; 44 static const int m2ThreshExt_off = 127; 45 46 47 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array, 48 int col) 49 { 50 int i; 51 52 for (i = 0; i < array->ia_rows; i++) 53 bank[i] = INI_RA(array, i, col); 54 } 55 56 57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \ 58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr)) 59 60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, 61 u32 *data, unsigned int *writecnt) 62 { 63 int r; 64 65 ENABLE_REGWRITE_BUFFER(ah); 66 67 for (r = 0; r < array->ia_rows; r++) { 68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 69 DO_DELAY(*writecnt); 70 } 71 72 REGWRITE_BUFFER_FLUSH(ah); 73 } 74 75 /** 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 77 * @rfbuf: 78 * @reg32: 79 * @numBits: 80 * @firstBit: 81 * @column: 82 * 83 * Performs analog "swizzling" of parameters into their location. 84 * Used on external AR2133/AR5133 radios. 85 */ 86 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 87 u32 numBits, u32 firstBit, 88 u32 column) 89 { 90 u32 tmp32, mask, arrayEntry, lastBit; 91 int32_t bitPosition, bitsLeft; 92 93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 94 arrayEntry = (firstBit - 1) / 8; 95 bitPosition = (firstBit - 1) % 8; 96 bitsLeft = numBits; 97 while (bitsLeft > 0) { 98 lastBit = (bitPosition + bitsLeft > 8) ? 99 8 : bitPosition + bitsLeft; 100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 101 (column * 8); 102 rfBuf[arrayEntry] &= ~mask; 103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 104 (column * 8)) & mask; 105 bitsLeft -= 8 - bitPosition; 106 tmp32 = tmp32 >> (8 - bitPosition); 107 bitPosition = 0; 108 arrayEntry++; 109 } 110 } 111 112 /* 113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 114 * rf_pwd_icsyndiv. 115 * 116 * Theoretical Rules: 117 * if 2 GHz band 118 * if forceBiasAuto 119 * if synth_freq < 2412 120 * bias = 0 121 * else if 2412 <= synth_freq <= 2422 122 * bias = 1 123 * else // synth_freq > 2422 124 * bias = 2 125 * else if forceBias > 0 126 * bias = forceBias & 7 127 * else 128 * no change, use value from ini file 129 * else 130 * no change, invalid band 131 * 132 * 1st Mod: 133 * 2422 also uses value of 2 134 * <approved> 135 * 136 * 2nd Mod: 137 * Less than 2412 uses value of 0, 2412 and above uses value of 2 138 */ 139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 140 { 141 struct ath_common *common = ath9k_hw_common(ah); 142 u32 tmp_reg; 143 int reg_writes = 0; 144 u32 new_bias = 0; 145 146 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 147 return; 148 149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 150 151 if (synth_freq < 2412) 152 new_bias = 0; 153 else if (synth_freq < 2422) 154 new_bias = 1; 155 else 156 new_bias = 2; 157 158 /* pre-reverse this field */ 159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 160 161 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 162 new_bias, synth_freq); 163 164 /* swizzle rf_pwd_icsyndiv */ 165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 166 167 /* write Bank 6 with new params */ 168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes); 169 } 170 171 /** 172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 173 * @ah: atheros hardware structure 174 * @chan: 175 * 176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 177 * the channel value. Assumes writes enabled to analog bus and bank6 register 178 * cache in ah->analogBank6Data. 179 */ 180 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 181 { 182 struct ath_common *common = ath9k_hw_common(ah); 183 u32 channelSel = 0; 184 u32 bModeSynth = 0; 185 u32 aModeRefSel = 0; 186 u32 reg32 = 0; 187 u16 freq; 188 struct chan_centers centers; 189 190 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 191 freq = centers.synth_center; 192 193 if (freq < 4800) { 194 u32 txctl; 195 196 if (((freq - 2192) % 5) == 0) { 197 channelSel = ((freq - 672) * 2 - 3040) / 10; 198 bModeSynth = 0; 199 } else if (((freq - 2224) % 5) == 0) { 200 channelSel = ((freq - 704) * 2 - 3040) / 10; 201 bModeSynth = 1; 202 } else { 203 ath_err(common, "Invalid channel %u MHz\n", freq); 204 return -EINVAL; 205 } 206 207 channelSel = (channelSel << 2) & 0xff; 208 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 209 210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 211 if (freq == 2484) { 212 213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 215 } else { 216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 218 } 219 220 } else if ((freq % 20) == 0 && freq >= 5120) { 221 channelSel = 222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 223 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 224 } else if ((freq % 10) == 0) { 225 channelSel = 226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 228 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 229 else 230 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 231 } else if ((freq % 5) == 0) { 232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 233 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 234 } else { 235 ath_err(common, "Invalid channel %u MHz\n", freq); 236 return -EINVAL; 237 } 238 239 ar5008_hw_force_bias(ah, freq); 240 241 reg32 = 242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 243 (1 << 5) | 0x1; 244 245 REG_WRITE(ah, AR_PHY(0x37), reg32); 246 247 ah->curchan = chan; 248 249 return 0; 250 } 251 252 /** 253 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 254 * @ah: atheros hardware structure 255 * @chan: 256 * 257 * For non single-chip solutions. Converts to baseband spur frequency given the 258 * input channel frequency and compute register settings below. 259 */ 260 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 261 struct ath9k_channel *chan) 262 { 263 int bb_spur = AR_NO_SPUR; 264 int bin, cur_bin; 265 int spur_freq_sd; 266 int spur_delta_phase; 267 int denominator; 268 int upper, lower, cur_vit_mask; 269 int tmp, new; 270 int i; 271 static int pilot_mask_reg[4] = { 272 AR_PHY_TIMING7, AR_PHY_TIMING8, 273 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 274 }; 275 static int chan_mask_reg[4] = { 276 AR_PHY_TIMING9, AR_PHY_TIMING10, 277 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 278 }; 279 static int inc[4] = { 0, 100, 0, 0 }; 280 281 int8_t mask_m[123]; 282 int8_t mask_p[123]; 283 int8_t mask_amt; 284 int tmp_mask; 285 int cur_bb_spur; 286 bool is2GHz = IS_CHAN_2GHZ(chan); 287 288 memset(&mask_m, 0, sizeof(int8_t) * 123); 289 memset(&mask_p, 0, sizeof(int8_t) * 123); 290 291 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 292 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 293 if (AR_NO_SPUR == cur_bb_spur) 294 break; 295 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 296 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 297 bb_spur = cur_bb_spur; 298 break; 299 } 300 } 301 302 if (AR_NO_SPUR == bb_spur) 303 return; 304 305 bin = bb_spur * 32; 306 307 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 308 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 309 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 310 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 311 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 312 313 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 314 315 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 316 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 317 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 318 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 319 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 320 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 321 322 spur_delta_phase = ((bb_spur * 524288) / 100) & 323 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 324 325 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 326 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 327 328 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 329 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 330 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 331 REG_WRITE(ah, AR_PHY_TIMING11, new); 332 333 cur_bin = -6000; 334 upper = bin + 100; 335 lower = bin - 100; 336 337 for (i = 0; i < 4; i++) { 338 int pilot_mask = 0; 339 int chan_mask = 0; 340 int bp = 0; 341 for (bp = 0; bp < 30; bp++) { 342 if ((cur_bin > lower) && (cur_bin < upper)) { 343 pilot_mask = pilot_mask | 0x1 << bp; 344 chan_mask = chan_mask | 0x1 << bp; 345 } 346 cur_bin += 100; 347 } 348 cur_bin += inc[i]; 349 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 350 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 351 } 352 353 cur_vit_mask = 6100; 354 upper = bin + 120; 355 lower = bin - 120; 356 357 for (i = 0; i < 123; i++) { 358 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 359 360 /* workaround for gcc bug #37014 */ 361 volatile int tmp_v = abs(cur_vit_mask - bin); 362 363 if (tmp_v < 75) 364 mask_amt = 1; 365 else 366 mask_amt = 0; 367 if (cur_vit_mask < 0) 368 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 369 else 370 mask_p[cur_vit_mask / 100] = mask_amt; 371 } 372 cur_vit_mask -= 100; 373 } 374 375 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 376 | (mask_m[48] << 26) | (mask_m[49] << 24) 377 | (mask_m[50] << 22) | (mask_m[51] << 20) 378 | (mask_m[52] << 18) | (mask_m[53] << 16) 379 | (mask_m[54] << 14) | (mask_m[55] << 12) 380 | (mask_m[56] << 10) | (mask_m[57] << 8) 381 | (mask_m[58] << 6) | (mask_m[59] << 4) 382 | (mask_m[60] << 2) | (mask_m[61] << 0); 383 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 384 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 385 386 tmp_mask = (mask_m[31] << 28) 387 | (mask_m[32] << 26) | (mask_m[33] << 24) 388 | (mask_m[34] << 22) | (mask_m[35] << 20) 389 | (mask_m[36] << 18) | (mask_m[37] << 16) 390 | (mask_m[48] << 14) | (mask_m[39] << 12) 391 | (mask_m[40] << 10) | (mask_m[41] << 8) 392 | (mask_m[42] << 6) | (mask_m[43] << 4) 393 | (mask_m[44] << 2) | (mask_m[45] << 0); 394 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 395 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 396 397 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 398 | (mask_m[18] << 26) | (mask_m[18] << 24) 399 | (mask_m[20] << 22) | (mask_m[20] << 20) 400 | (mask_m[22] << 18) | (mask_m[22] << 16) 401 | (mask_m[24] << 14) | (mask_m[24] << 12) 402 | (mask_m[25] << 10) | (mask_m[26] << 8) 403 | (mask_m[27] << 6) | (mask_m[28] << 4) 404 | (mask_m[29] << 2) | (mask_m[30] << 0); 405 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 406 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 407 408 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 409 | (mask_m[2] << 26) | (mask_m[3] << 24) 410 | (mask_m[4] << 22) | (mask_m[5] << 20) 411 | (mask_m[6] << 18) | (mask_m[7] << 16) 412 | (mask_m[8] << 14) | (mask_m[9] << 12) 413 | (mask_m[10] << 10) | (mask_m[11] << 8) 414 | (mask_m[12] << 6) | (mask_m[13] << 4) 415 | (mask_m[14] << 2) | (mask_m[15] << 0); 416 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 417 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 418 419 tmp_mask = (mask_p[15] << 28) 420 | (mask_p[14] << 26) | (mask_p[13] << 24) 421 | (mask_p[12] << 22) | (mask_p[11] << 20) 422 | (mask_p[10] << 18) | (mask_p[9] << 16) 423 | (mask_p[8] << 14) | (mask_p[7] << 12) 424 | (mask_p[6] << 10) | (mask_p[5] << 8) 425 | (mask_p[4] << 6) | (mask_p[3] << 4) 426 | (mask_p[2] << 2) | (mask_p[1] << 0); 427 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 428 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 429 430 tmp_mask = (mask_p[30] << 28) 431 | (mask_p[29] << 26) | (mask_p[28] << 24) 432 | (mask_p[27] << 22) | (mask_p[26] << 20) 433 | (mask_p[25] << 18) | (mask_p[24] << 16) 434 | (mask_p[23] << 14) | (mask_p[22] << 12) 435 | (mask_p[21] << 10) | (mask_p[20] << 8) 436 | (mask_p[19] << 6) | (mask_p[18] << 4) 437 | (mask_p[17] << 2) | (mask_p[16] << 0); 438 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 439 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 440 441 tmp_mask = (mask_p[45] << 28) 442 | (mask_p[44] << 26) | (mask_p[43] << 24) 443 | (mask_p[42] << 22) | (mask_p[41] << 20) 444 | (mask_p[40] << 18) | (mask_p[39] << 16) 445 | (mask_p[38] << 14) | (mask_p[37] << 12) 446 | (mask_p[36] << 10) | (mask_p[35] << 8) 447 | (mask_p[34] << 6) | (mask_p[33] << 4) 448 | (mask_p[32] << 2) | (mask_p[31] << 0); 449 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 450 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 451 452 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 453 | (mask_p[59] << 26) | (mask_p[58] << 24) 454 | (mask_p[57] << 22) | (mask_p[56] << 20) 455 | (mask_p[55] << 18) | (mask_p[54] << 16) 456 | (mask_p[53] << 14) | (mask_p[52] << 12) 457 | (mask_p[51] << 10) | (mask_p[50] << 8) 458 | (mask_p[49] << 6) | (mask_p[48] << 4) 459 | (mask_p[47] << 2) | (mask_p[46] << 0); 460 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 461 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 462 } 463 464 /** 465 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 466 * @ah: atheros hardware structure 467 * 468 * Only required for older devices with external AR2133/AR5133 radios. 469 */ 470 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 471 { 472 #define ATH_ALLOC_BANK(bank, size) do { \ 473 bank = devm_kzalloc(ah->dev, sizeof(u32) * size, GFP_KERNEL); \ 474 if (!bank) \ 475 goto error; \ 476 } while (0); 477 478 struct ath_common *common = ath9k_hw_common(ah); 479 480 if (AR_SREV_9280_20_OR_LATER(ah)) 481 return 0; 482 483 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows); 484 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows); 485 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows); 486 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows); 487 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows); 488 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows); 489 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows); 490 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows); 491 492 return 0; 493 #undef ATH_ALLOC_BANK 494 error: 495 ath_err(common, "Cannot allocate RF banks\n"); 496 return -ENOMEM; 497 } 498 499 500 /* * 501 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 502 * @ah: atheros hardware structure 503 * @chan: 504 * @modesIndex: 505 * 506 * Used for the external AR2133/AR5133 radios. 507 * 508 * Reads the EEPROM header info from the device structure and programs 509 * all rf registers. This routine requires access to the analog 510 * rf device. This is not required for single-chip devices. 511 */ 512 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 513 struct ath9k_channel *chan, 514 u16 modesIndex) 515 { 516 u32 eepMinorRev; 517 u32 ob5GHz = 0, db5GHz = 0; 518 u32 ob2GHz = 0, db2GHz = 0; 519 int regWrites = 0; 520 521 /* 522 * Software does not need to program bank data 523 * for single chip devices, that is AR9280 or anything 524 * after that. 525 */ 526 if (AR_SREV_9280_20_OR_LATER(ah)) 527 return true; 528 529 /* Setup rf parameters */ 530 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 531 532 /* Setup Bank 0 Write */ 533 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1); 534 535 /* Setup Bank 1 Write */ 536 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1); 537 538 /* Setup Bank 2 Write */ 539 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1); 540 541 /* Setup Bank 6 Write */ 542 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3, 543 modesIndex); 544 { 545 int i; 546 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { 547 ah->analogBank6Data[i] = 548 INI_RA(&ah->iniBank6TPC, i, modesIndex); 549 } 550 } 551 552 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 553 if (eepMinorRev >= 2) { 554 if (IS_CHAN_2GHZ(chan)) { 555 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 556 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 557 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 558 ob2GHz, 3, 197, 0); 559 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 560 db2GHz, 3, 194, 0); 561 } else { 562 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 563 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 564 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 565 ob5GHz, 3, 203, 0); 566 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 567 db5GHz, 3, 200, 0); 568 } 569 } 570 571 /* Setup Bank 7 Setup */ 572 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1); 573 574 /* Write Analog registers */ 575 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 576 regWrites); 577 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 578 regWrites); 579 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, 580 regWrites); 581 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, 582 regWrites); 583 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, 584 regWrites); 585 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, 586 regWrites); 587 588 return true; 589 } 590 591 static void ar5008_hw_init_bb(struct ath_hw *ah, 592 struct ath9k_channel *chan) 593 { 594 u32 synthDelay; 595 596 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 597 598 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 599 600 ath9k_hw_synth_delay(ah, chan, synthDelay); 601 } 602 603 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 604 { 605 int rx_chainmask, tx_chainmask; 606 607 rx_chainmask = ah->rxchainmask; 608 tx_chainmask = ah->txchainmask; 609 610 611 switch (rx_chainmask) { 612 case 0x5: 613 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 614 AR_PHY_SWAP_ALT_CHAIN); 615 case 0x3: 616 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 617 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 618 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 619 break; 620 } 621 case 0x1: 622 case 0x2: 623 case 0x7: 624 ENABLE_REGWRITE_BUFFER(ah); 625 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 626 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 627 break; 628 default: 629 ENABLE_REGWRITE_BUFFER(ah); 630 break; 631 } 632 633 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 634 635 REGWRITE_BUFFER_FLUSH(ah); 636 637 if (tx_chainmask == 0x5) { 638 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 639 AR_PHY_SWAP_ALT_CHAIN); 640 } 641 if (AR_SREV_9100(ah)) 642 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 643 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 644 } 645 646 static void ar5008_hw_override_ini(struct ath_hw *ah, 647 struct ath9k_channel *chan) 648 { 649 u32 val; 650 651 /* 652 * Set the RX_ABORT and RX_DIS and clear if off only after 653 * RXE is set for MAC. This prevents frames with corrupted 654 * descriptor status. 655 */ 656 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 657 658 if (AR_SREV_9280_20_OR_LATER(ah)) { 659 val = REG_READ(ah, AR_PCU_MISC_MODE2); 660 661 if (!AR_SREV_9271(ah)) 662 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 663 664 if (AR_SREV_9287_11_OR_LATER(ah)) 665 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 666 667 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 668 } 669 670 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 671 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 672 673 if (AR_SREV_9280_20_OR_LATER(ah)) 674 return; 675 /* 676 * Disable BB clock gating 677 * Necessary to avoid issues on AR5416 2.0 678 */ 679 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 680 681 /* 682 * Disable RIFS search on some chips to avoid baseband 683 * hang issues. 684 */ 685 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 686 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 687 val &= ~AR_PHY_RIFS_INIT_DELAY; 688 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 689 } 690 } 691 692 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 693 struct ath9k_channel *chan) 694 { 695 u32 phymode; 696 u32 enableDacFifo = 0; 697 698 if (AR_SREV_9285_12_OR_LATER(ah)) 699 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 700 AR_PHY_FC_ENABLE_DAC_FIFO); 701 702 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 703 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 704 705 if (IS_CHAN_HT40(chan)) { 706 phymode |= AR_PHY_FC_DYN2040_EN; 707 708 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 709 (chan->chanmode == CHANNEL_G_HT40PLUS)) 710 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 711 712 } 713 REG_WRITE(ah, AR_PHY_TURBO, phymode); 714 715 ath9k_hw_set11nmac2040(ah); 716 717 ENABLE_REGWRITE_BUFFER(ah); 718 719 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 720 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 721 722 REGWRITE_BUFFER_FLUSH(ah); 723 } 724 725 726 static int ar5008_hw_process_ini(struct ath_hw *ah, 727 struct ath9k_channel *chan) 728 { 729 struct ath_common *common = ath9k_hw_common(ah); 730 int i, regWrites = 0; 731 u32 modesIndex, freqIndex; 732 733 switch (chan->chanmode) { 734 case CHANNEL_A: 735 case CHANNEL_A_HT20: 736 modesIndex = 1; 737 freqIndex = 1; 738 break; 739 case CHANNEL_A_HT40PLUS: 740 case CHANNEL_A_HT40MINUS: 741 modesIndex = 2; 742 freqIndex = 1; 743 break; 744 case CHANNEL_G: 745 case CHANNEL_G_HT20: 746 case CHANNEL_B: 747 modesIndex = 4; 748 freqIndex = 2; 749 break; 750 case CHANNEL_G_HT40PLUS: 751 case CHANNEL_G_HT40MINUS: 752 modesIndex = 3; 753 freqIndex = 2; 754 break; 755 756 default: 757 return -EINVAL; 758 } 759 760 /* 761 * Set correct baseband to analog shift setting to 762 * access analog chips. 763 */ 764 REG_WRITE(ah, AR_PHY(0), 0x00000007); 765 766 /* Write ADDAC shifts */ 767 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 768 if (ah->eep_ops->set_addac) 769 ah->eep_ops->set_addac(ah, chan); 770 771 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 772 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 773 774 ENABLE_REGWRITE_BUFFER(ah); 775 776 for (i = 0; i < ah->iniModes.ia_rows; i++) { 777 u32 reg = INI_RA(&ah->iniModes, i, 0); 778 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 779 780 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 781 val &= ~AR_AN_TOP2_PWDCLKIND; 782 783 REG_WRITE(ah, reg, val); 784 785 if (reg >= 0x7800 && reg < 0x78a0 786 && ah->config.analog_shiftreg 787 && (common->bus_ops->ath_bus_type != ATH_USB)) { 788 udelay(100); 789 } 790 791 DO_DELAY(regWrites); 792 } 793 794 REGWRITE_BUFFER_FLUSH(ah); 795 796 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 797 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 798 799 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 800 AR_SREV_9287_11_OR_LATER(ah)) 801 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 802 803 if (AR_SREV_9271_10(ah)) { 804 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 805 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 806 } 807 808 ENABLE_REGWRITE_BUFFER(ah); 809 810 /* Write common array parameters */ 811 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 812 u32 reg = INI_RA(&ah->iniCommon, i, 0); 813 u32 val = INI_RA(&ah->iniCommon, i, 1); 814 815 REG_WRITE(ah, reg, val); 816 817 if (reg >= 0x7800 && reg < 0x78a0 818 && ah->config.analog_shiftreg 819 && (common->bus_ops->ath_bus_type != ATH_USB)) { 820 udelay(100); 821 } 822 823 DO_DELAY(regWrites); 824 } 825 826 REGWRITE_BUFFER_FLUSH(ah); 827 828 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 829 830 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 831 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 832 regWrites); 833 834 ar5008_hw_override_ini(ah, chan); 835 ar5008_hw_set_channel_regs(ah, chan); 836 ar5008_hw_init_chain_masks(ah); 837 ath9k_olc_init(ah); 838 ath9k_hw_apply_txpower(ah, chan, false); 839 840 /* Write analog registers */ 841 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 842 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 843 return -EIO; 844 } 845 846 return 0; 847 } 848 849 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 850 { 851 u32 rfMode = 0; 852 853 if (chan == NULL) 854 return; 855 856 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 857 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 858 859 if (!AR_SREV_9280_20_OR_LATER(ah)) 860 rfMode |= (IS_CHAN_5GHZ(chan)) ? 861 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 862 863 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 864 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 865 866 REG_WRITE(ah, AR_PHY_MODE, rfMode); 867 } 868 869 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 870 { 871 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 872 } 873 874 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 875 struct ath9k_channel *chan) 876 { 877 u32 coef_scaled, ds_coef_exp, ds_coef_man; 878 u32 clockMhzScaled = 0x64000000; 879 struct chan_centers centers; 880 881 if (IS_CHAN_HALF_RATE(chan)) 882 clockMhzScaled = clockMhzScaled >> 1; 883 else if (IS_CHAN_QUARTER_RATE(chan)) 884 clockMhzScaled = clockMhzScaled >> 2; 885 886 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 887 coef_scaled = clockMhzScaled / centers.synth_center; 888 889 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 890 &ds_coef_exp); 891 892 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 893 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 894 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 895 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 896 897 coef_scaled = (9 * coef_scaled) / 10; 898 899 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 900 &ds_coef_exp); 901 902 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 903 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 904 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 905 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 906 } 907 908 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 909 { 910 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 911 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 912 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 913 } 914 915 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 916 { 917 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 918 919 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 920 921 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 922 } 923 924 static void ar5008_restore_chainmask(struct ath_hw *ah) 925 { 926 int rx_chainmask = ah->rxchainmask; 927 928 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 929 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 930 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 931 } 932 } 933 934 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 935 struct ath9k_channel *chan) 936 { 937 u32 pll; 938 939 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 940 941 if (chan && IS_CHAN_HALF_RATE(chan)) 942 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 943 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 944 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 945 946 if (chan && IS_CHAN_5GHZ(chan)) 947 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 948 else 949 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 950 951 return pll; 952 } 953 954 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 955 struct ath9k_channel *chan) 956 { 957 u32 pll; 958 959 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 960 961 if (chan && IS_CHAN_HALF_RATE(chan)) 962 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 963 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 964 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 965 966 if (chan && IS_CHAN_5GHZ(chan)) 967 pll |= SM(0xa, AR_RTC_PLL_DIV); 968 else 969 pll |= SM(0xb, AR_RTC_PLL_DIV); 970 971 return pll; 972 } 973 974 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 975 enum ath9k_ani_cmd cmd, 976 int param) 977 { 978 struct ath_common *common = ath9k_hw_common(ah); 979 struct ath9k_channel *chan = ah->curchan; 980 struct ar5416AniState *aniState = &chan->ani; 981 s32 value, value2; 982 983 switch (cmd & ah->ani_function) { 984 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 985 /* 986 * on == 1 means ofdm weak signal detection is ON 987 * on == 1 is the default, for less noise immunity 988 * 989 * on == 0 means ofdm weak signal detection is OFF 990 * on == 0 means more noise imm 991 */ 992 u32 on = param ? 1 : 0; 993 /* 994 * make register setting for default 995 * (weak sig detect ON) come from INI file 996 */ 997 int m1ThreshLow = on ? 998 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 999 int m2ThreshLow = on ? 1000 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 1001 int m1Thresh = on ? 1002 aniState->iniDef.m1Thresh : m1Thresh_off; 1003 int m2Thresh = on ? 1004 aniState->iniDef.m2Thresh : m2Thresh_off; 1005 int m2CountThr = on ? 1006 aniState->iniDef.m2CountThr : m2CountThr_off; 1007 int m2CountThrLow = on ? 1008 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 1009 int m1ThreshLowExt = on ? 1010 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 1011 int m2ThreshLowExt = on ? 1012 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1013 int m1ThreshExt = on ? 1014 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1015 int m2ThreshExt = on ? 1016 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1017 1018 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1019 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1020 m1ThreshLow); 1021 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1022 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1023 m2ThreshLow); 1024 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1025 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 1026 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1027 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 1028 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1029 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 1030 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1031 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1032 m2CountThrLow); 1033 1034 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1035 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 1036 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1037 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 1038 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1039 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1040 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1041 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1042 1043 if (on) 1044 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1045 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1046 else 1047 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1048 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1049 1050 if (on != aniState->ofdmWeakSigDetect) { 1051 ath_dbg(common, ANI, 1052 "** ch %d: ofdm weak signal: %s=>%s\n", 1053 chan->channel, 1054 aniState->ofdmWeakSigDetect ? 1055 "on" : "off", 1056 on ? "on" : "off"); 1057 if (on) 1058 ah->stats.ast_ani_ofdmon++; 1059 else 1060 ah->stats.ast_ani_ofdmoff++; 1061 aniState->ofdmWeakSigDetect = on; 1062 } 1063 break; 1064 } 1065 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1066 u32 level = param; 1067 1068 if (level >= ARRAY_SIZE(firstep_table)) { 1069 ath_dbg(common, ANI, 1070 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1071 level, ARRAY_SIZE(firstep_table)); 1072 return false; 1073 } 1074 1075 /* 1076 * make register setting relative to default 1077 * from INI file & cap value 1078 */ 1079 value = firstep_table[level] - 1080 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1081 aniState->iniDef.firstep; 1082 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1083 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1084 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1085 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1086 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1087 AR_PHY_FIND_SIG_FIRSTEP, 1088 value); 1089 /* 1090 * we need to set first step low register too 1091 * make register setting relative to default 1092 * from INI file & cap value 1093 */ 1094 value2 = firstep_table[level] - 1095 firstep_table[ATH9K_ANI_FIRSTEP_LVL] + 1096 aniState->iniDef.firstepLow; 1097 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1098 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1099 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1100 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1101 1102 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1103 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); 1104 1105 if (level != aniState->firstepLevel) { 1106 ath_dbg(common, ANI, 1107 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1108 chan->channel, 1109 aniState->firstepLevel, 1110 level, 1111 ATH9K_ANI_FIRSTEP_LVL, 1112 value, 1113 aniState->iniDef.firstep); 1114 ath_dbg(common, ANI, 1115 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1116 chan->channel, 1117 aniState->firstepLevel, 1118 level, 1119 ATH9K_ANI_FIRSTEP_LVL, 1120 value2, 1121 aniState->iniDef.firstepLow); 1122 if (level > aniState->firstepLevel) 1123 ah->stats.ast_ani_stepup++; 1124 else if (level < aniState->firstepLevel) 1125 ah->stats.ast_ani_stepdown++; 1126 aniState->firstepLevel = level; 1127 } 1128 break; 1129 } 1130 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1131 u32 level = param; 1132 1133 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1134 ath_dbg(common, ANI, 1135 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1136 level, ARRAY_SIZE(cycpwrThr1_table)); 1137 return false; 1138 } 1139 /* 1140 * make register setting relative to default 1141 * from INI file & cap value 1142 */ 1143 value = cycpwrThr1_table[level] - 1144 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1145 aniState->iniDef.cycpwrThr1; 1146 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1147 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1148 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1149 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1150 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1151 AR_PHY_TIMING5_CYCPWR_THR1, 1152 value); 1153 1154 /* 1155 * set AR_PHY_EXT_CCA for extension channel 1156 * make register setting relative to default 1157 * from INI file & cap value 1158 */ 1159 value2 = cycpwrThr1_table[level] - 1160 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + 1161 aniState->iniDef.cycpwrThr1Ext; 1162 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1163 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1164 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1165 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1166 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1167 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); 1168 1169 if (level != aniState->spurImmunityLevel) { 1170 ath_dbg(common, ANI, 1171 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1172 chan->channel, 1173 aniState->spurImmunityLevel, 1174 level, 1175 ATH9K_ANI_SPUR_IMMUNE_LVL, 1176 value, 1177 aniState->iniDef.cycpwrThr1); 1178 ath_dbg(common, ANI, 1179 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1180 chan->channel, 1181 aniState->spurImmunityLevel, 1182 level, 1183 ATH9K_ANI_SPUR_IMMUNE_LVL, 1184 value2, 1185 aniState->iniDef.cycpwrThr1Ext); 1186 if (level > aniState->spurImmunityLevel) 1187 ah->stats.ast_ani_spurup++; 1188 else if (level < aniState->spurImmunityLevel) 1189 ah->stats.ast_ani_spurdown++; 1190 aniState->spurImmunityLevel = level; 1191 } 1192 break; 1193 } 1194 case ATH9K_ANI_MRC_CCK: 1195 /* 1196 * You should not see this as AR5008, AR9001, AR9002 1197 * does not have hardware support for MRC CCK. 1198 */ 1199 WARN_ON(1); 1200 break; 1201 case ATH9K_ANI_PRESENT: 1202 break; 1203 default: 1204 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1205 return false; 1206 } 1207 1208 ath_dbg(common, ANI, 1209 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1210 aniState->spurImmunityLevel, 1211 aniState->ofdmWeakSigDetect ? "on" : "off", 1212 aniState->firstepLevel, 1213 aniState->mrcCCK ? "on" : "off", 1214 aniState->listenTime, 1215 aniState->ofdmPhyErrCount, 1216 aniState->cckPhyErrCount); 1217 return true; 1218 } 1219 1220 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1221 int16_t nfarray[NUM_NF_READINGS]) 1222 { 1223 int16_t nf; 1224 1225 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1226 nfarray[0] = sign_extend32(nf, 8); 1227 1228 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1229 nfarray[1] = sign_extend32(nf, 8); 1230 1231 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1232 nfarray[2] = sign_extend32(nf, 8); 1233 1234 if (!IS_CHAN_HT40(ah->curchan)) 1235 return; 1236 1237 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1238 nfarray[3] = sign_extend32(nf, 8); 1239 1240 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1241 nfarray[4] = sign_extend32(nf, 8); 1242 1243 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1244 nfarray[5] = sign_extend32(nf, 8); 1245 } 1246 1247 /* 1248 * Initialize the ANI register values with default (ini) values. 1249 * This routine is called during a (full) hardware reset after 1250 * all the registers are initialised from the INI. 1251 */ 1252 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1253 { 1254 struct ath_common *common = ath9k_hw_common(ah); 1255 struct ath9k_channel *chan = ah->curchan; 1256 struct ar5416AniState *aniState = &chan->ani; 1257 struct ath9k_ani_default *iniDef; 1258 u32 val; 1259 1260 iniDef = &aniState->iniDef; 1261 1262 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1263 ah->hw_version.macVersion, 1264 ah->hw_version.macRev, 1265 ah->opmode, 1266 chan->channel, 1267 chan->channelFlags); 1268 1269 val = REG_READ(ah, AR_PHY_SFCORR); 1270 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1271 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1272 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1273 1274 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1275 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1276 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1277 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1278 1279 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1280 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1281 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1282 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1283 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1284 iniDef->firstep = REG_READ_FIELD(ah, 1285 AR_PHY_FIND_SIG, 1286 AR_PHY_FIND_SIG_FIRSTEP); 1287 iniDef->firstepLow = REG_READ_FIELD(ah, 1288 AR_PHY_FIND_SIG_LOW, 1289 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1290 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1291 AR_PHY_TIMING5, 1292 AR_PHY_TIMING5_CYCPWR_THR1); 1293 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1294 AR_PHY_EXT_CCA, 1295 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1296 1297 /* these levels just got reset to defaults by the INI */ 1298 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1299 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1300 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG; 1301 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1302 } 1303 1304 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1305 { 1306 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1307 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1308 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1309 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1310 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1311 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1312 } 1313 1314 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1315 struct ath_hw_radar_conf *conf) 1316 { 1317 u32 radar_0 = 0, radar_1 = 0; 1318 1319 if (!conf) { 1320 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1321 return; 1322 } 1323 1324 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1325 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1326 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1327 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1328 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1329 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1330 1331 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1332 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1333 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1334 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1335 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1336 1337 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1338 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1339 if (conf->ext_channel) 1340 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1341 else 1342 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1343 } 1344 1345 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1346 { 1347 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1348 1349 conf->fir_power = -33; 1350 conf->radar_rssi = 20; 1351 conf->pulse_height = 10; 1352 conf->pulse_rssi = 24; 1353 conf->pulse_inband = 15; 1354 conf->pulse_maxlen = 255; 1355 conf->pulse_inband_step = 12; 1356 conf->radar_inband = 8; 1357 } 1358 1359 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1360 { 1361 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1362 static const u32 ar5416_cca_regs[6] = { 1363 AR_PHY_CCA, 1364 AR_PHY_CH1_CCA, 1365 AR_PHY_CH2_CCA, 1366 AR_PHY_EXT_CCA, 1367 AR_PHY_CH1_EXT_CCA, 1368 AR_PHY_CH2_EXT_CCA 1369 }; 1370 int ret; 1371 1372 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1373 if (ret) 1374 return ret; 1375 1376 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1377 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1378 1379 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1380 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1381 priv_ops->init_bb = ar5008_hw_init_bb; 1382 priv_ops->process_ini = ar5008_hw_process_ini; 1383 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1384 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1385 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1386 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1387 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1388 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1389 priv_ops->do_getnf = ar5008_hw_do_getnf; 1390 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1391 1392 priv_ops->ani_control = ar5008_hw_ani_control_new; 1393 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1394 1395 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1396 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1397 else 1398 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1399 1400 ar5008_hw_set_nf_limits(ah); 1401 ar5008_hw_set_radar_conf(ah); 1402 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1403 return 0; 1404 } 1405