1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 #include "ar5008_initvals.h" 22 23 /* All code below is for AR5008, AR9001, AR9002 */ 24 25 #define AR5008_OFDM_RATES 8 26 #define AR5008_HT_SS_RATES 8 27 #define AR5008_HT_DS_RATES 8 28 29 #define AR5008_HT20_SHIFT 16 30 #define AR5008_HT40_SHIFT 24 31 32 #define AR5008_11NA_OFDM_SHIFT 0 33 #define AR5008_11NA_HT_SS_SHIFT 8 34 #define AR5008_11NA_HT_DS_SHIFT 16 35 36 #define AR5008_11NG_OFDM_SHIFT 4 37 #define AR5008_11NG_HT_SS_SHIFT 12 38 #define AR5008_11NG_HT_DS_SHIFT 20 39 40 static const int firstep_table[] = 41 /* level: 0 1 2 3 4 5 6 7 8 */ 42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 43 44 /* 45 * register values to turn OFDM weak signal detection OFF 46 */ 47 static const int m1ThreshLow_off = 127; 48 static const int m2ThreshLow_off = 127; 49 static const int m1Thresh_off = 127; 50 static const int m2Thresh_off = 127; 51 static const int m2CountThr_off = 31; 52 static const int m2CountThrLow_off = 63; 53 static const int m1ThreshLowExt_off = 127; 54 static const int m2ThreshLowExt_off = 127; 55 static const int m1ThreshExt_off = 127; 56 static const int m2ThreshExt_off = 127; 57 58 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 59 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 60 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 61 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 62 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 63 64 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 65 { 66 struct ar5416IniArray *array = &ah->iniBank6; 67 u32 *data = ah->analogBank6Data; 68 int r; 69 70 ENABLE_REGWRITE_BUFFER(ah); 71 72 for (r = 0; r < array->ia_rows; r++) { 73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 74 DO_DELAY(*writecnt); 75 } 76 77 REGWRITE_BUFFER_FLUSH(ah); 78 } 79 80 /** 81 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 82 * @rfbuf: 83 * @reg32: 84 * @numBits: 85 * @firstBit: 86 * @column: 87 * 88 * Performs analog "swizzling" of parameters into their location. 89 * Used on external AR2133/AR5133 radios. 90 */ 91 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 92 u32 numBits, u32 firstBit, 93 u32 column) 94 { 95 u32 tmp32, mask, arrayEntry, lastBit; 96 int32_t bitPosition, bitsLeft; 97 98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 99 arrayEntry = (firstBit - 1) / 8; 100 bitPosition = (firstBit - 1) % 8; 101 bitsLeft = numBits; 102 while (bitsLeft > 0) { 103 lastBit = (bitPosition + bitsLeft > 8) ? 104 8 : bitPosition + bitsLeft; 105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 106 (column * 8); 107 rfBuf[arrayEntry] &= ~mask; 108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 109 (column * 8)) & mask; 110 bitsLeft -= 8 - bitPosition; 111 tmp32 = tmp32 >> (8 - bitPosition); 112 bitPosition = 0; 113 arrayEntry++; 114 } 115 } 116 117 /* 118 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 119 * rf_pwd_icsyndiv. 120 * 121 * Theoretical Rules: 122 * if 2 GHz band 123 * if forceBiasAuto 124 * if synth_freq < 2412 125 * bias = 0 126 * else if 2412 <= synth_freq <= 2422 127 * bias = 1 128 * else // synth_freq > 2422 129 * bias = 2 130 * else if forceBias > 0 131 * bias = forceBias & 7 132 * else 133 * no change, use value from ini file 134 * else 135 * no change, invalid band 136 * 137 * 1st Mod: 138 * 2422 also uses value of 2 139 * <approved> 140 * 141 * 2nd Mod: 142 * Less than 2412 uses value of 0, 2412 and above uses value of 2 143 */ 144 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 145 { 146 struct ath_common *common = ath9k_hw_common(ah); 147 u32 tmp_reg; 148 int reg_writes = 0; 149 u32 new_bias = 0; 150 151 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 152 return; 153 154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 155 156 if (synth_freq < 2412) 157 new_bias = 0; 158 else if (synth_freq < 2422) 159 new_bias = 1; 160 else 161 new_bias = 2; 162 163 /* pre-reverse this field */ 164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 165 166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 167 new_bias, synth_freq); 168 169 /* swizzle rf_pwd_icsyndiv */ 170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 171 172 /* write Bank 6 with new params */ 173 ar5008_write_bank6(ah, ®_writes); 174 } 175 176 /** 177 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 178 * @ah: atheros hardware structure 179 * @chan: 180 * 181 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 182 * the channel value. Assumes writes enabled to analog bus and bank6 register 183 * cache in ah->analogBank6Data. 184 */ 185 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 186 { 187 struct ath_common *common = ath9k_hw_common(ah); 188 u32 channelSel = 0; 189 u32 bModeSynth = 0; 190 u32 aModeRefSel = 0; 191 u32 reg32 = 0; 192 u16 freq; 193 struct chan_centers centers; 194 195 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 196 freq = centers.synth_center; 197 198 if (freq < 4800) { 199 u32 txctl; 200 201 if (((freq - 2192) % 5) == 0) { 202 channelSel = ((freq - 672) * 2 - 3040) / 10; 203 bModeSynth = 0; 204 } else if (((freq - 2224) % 5) == 0) { 205 channelSel = ((freq - 704) * 2 - 3040) / 10; 206 bModeSynth = 1; 207 } else { 208 ath_err(common, "Invalid channel %u MHz\n", freq); 209 return -EINVAL; 210 } 211 212 channelSel = (channelSel << 2) & 0xff; 213 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 214 215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 216 if (freq == 2484) { 217 218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 220 } else { 221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 223 } 224 225 } else if ((freq % 20) == 0 && freq >= 5120) { 226 channelSel = 227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 228 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 229 } else if ((freq % 10) == 0) { 230 channelSel = 231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 233 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 234 else 235 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 236 } else if ((freq % 5) == 0) { 237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 238 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 239 } else { 240 ath_err(common, "Invalid channel %u MHz\n", freq); 241 return -EINVAL; 242 } 243 244 ar5008_hw_force_bias(ah, freq); 245 246 reg32 = 247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 248 (1 << 5) | 0x1; 249 250 REG_WRITE(ah, AR_PHY(0x37), reg32); 251 252 ah->curchan = chan; 253 254 return 0; 255 } 256 257 /** 258 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 259 * @ah: atheros hardware structure 260 * @chan: 261 * 262 * For non single-chip solutions. Converts to baseband spur frequency given the 263 * input channel frequency and compute register settings below. 264 */ 265 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 266 struct ath9k_channel *chan) 267 { 268 int bb_spur = AR_NO_SPUR; 269 int bin, cur_bin; 270 int spur_freq_sd; 271 int spur_delta_phase; 272 int denominator; 273 int upper, lower, cur_vit_mask; 274 int tmp, new; 275 int i; 276 static int pilot_mask_reg[4] = { 277 AR_PHY_TIMING7, AR_PHY_TIMING8, 278 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 279 }; 280 static int chan_mask_reg[4] = { 281 AR_PHY_TIMING9, AR_PHY_TIMING10, 282 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 283 }; 284 static int inc[4] = { 0, 100, 0, 0 }; 285 286 int8_t mask_m[123]; 287 int8_t mask_p[123]; 288 int8_t mask_amt; 289 int tmp_mask; 290 int cur_bb_spur; 291 bool is2GHz = IS_CHAN_2GHZ(chan); 292 293 memset(&mask_m, 0, sizeof(int8_t) * 123); 294 memset(&mask_p, 0, sizeof(int8_t) * 123); 295 296 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 297 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 298 if (AR_NO_SPUR == cur_bb_spur) 299 break; 300 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 301 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 302 bb_spur = cur_bb_spur; 303 break; 304 } 305 } 306 307 if (AR_NO_SPUR == bb_spur) 308 return; 309 310 bin = bb_spur * 32; 311 312 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 313 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 314 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 315 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 316 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 317 318 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 319 320 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 321 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 322 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 323 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 324 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 325 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 326 327 spur_delta_phase = ((bb_spur * 524288) / 100) & 328 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 329 330 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 331 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 332 333 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 334 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 335 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 336 REG_WRITE(ah, AR_PHY_TIMING11, new); 337 338 cur_bin = -6000; 339 upper = bin + 100; 340 lower = bin - 100; 341 342 for (i = 0; i < 4; i++) { 343 int pilot_mask = 0; 344 int chan_mask = 0; 345 int bp = 0; 346 for (bp = 0; bp < 30; bp++) { 347 if ((cur_bin > lower) && (cur_bin < upper)) { 348 pilot_mask = pilot_mask | 0x1 << bp; 349 chan_mask = chan_mask | 0x1 << bp; 350 } 351 cur_bin += 100; 352 } 353 cur_bin += inc[i]; 354 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 355 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 356 } 357 358 cur_vit_mask = 6100; 359 upper = bin + 120; 360 lower = bin - 120; 361 362 for (i = 0; i < 123; i++) { 363 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 364 365 /* workaround for gcc bug #37014 */ 366 volatile int tmp_v = abs(cur_vit_mask - bin); 367 368 if (tmp_v < 75) 369 mask_amt = 1; 370 else 371 mask_amt = 0; 372 if (cur_vit_mask < 0) 373 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 374 else 375 mask_p[cur_vit_mask / 100] = mask_amt; 376 } 377 cur_vit_mask -= 100; 378 } 379 380 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 381 | (mask_m[48] << 26) | (mask_m[49] << 24) 382 | (mask_m[50] << 22) | (mask_m[51] << 20) 383 | (mask_m[52] << 18) | (mask_m[53] << 16) 384 | (mask_m[54] << 14) | (mask_m[55] << 12) 385 | (mask_m[56] << 10) | (mask_m[57] << 8) 386 | (mask_m[58] << 6) | (mask_m[59] << 4) 387 | (mask_m[60] << 2) | (mask_m[61] << 0); 388 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 389 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 390 391 tmp_mask = (mask_m[31] << 28) 392 | (mask_m[32] << 26) | (mask_m[33] << 24) 393 | (mask_m[34] << 22) | (mask_m[35] << 20) 394 | (mask_m[36] << 18) | (mask_m[37] << 16) 395 | (mask_m[48] << 14) | (mask_m[39] << 12) 396 | (mask_m[40] << 10) | (mask_m[41] << 8) 397 | (mask_m[42] << 6) | (mask_m[43] << 4) 398 | (mask_m[44] << 2) | (mask_m[45] << 0); 399 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 400 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 401 402 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 403 | (mask_m[18] << 26) | (mask_m[18] << 24) 404 | (mask_m[20] << 22) | (mask_m[20] << 20) 405 | (mask_m[22] << 18) | (mask_m[22] << 16) 406 | (mask_m[24] << 14) | (mask_m[24] << 12) 407 | (mask_m[25] << 10) | (mask_m[26] << 8) 408 | (mask_m[27] << 6) | (mask_m[28] << 4) 409 | (mask_m[29] << 2) | (mask_m[30] << 0); 410 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 411 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 412 413 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 414 | (mask_m[2] << 26) | (mask_m[3] << 24) 415 | (mask_m[4] << 22) | (mask_m[5] << 20) 416 | (mask_m[6] << 18) | (mask_m[7] << 16) 417 | (mask_m[8] << 14) | (mask_m[9] << 12) 418 | (mask_m[10] << 10) | (mask_m[11] << 8) 419 | (mask_m[12] << 6) | (mask_m[13] << 4) 420 | (mask_m[14] << 2) | (mask_m[15] << 0); 421 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 422 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 423 424 tmp_mask = (mask_p[15] << 28) 425 | (mask_p[14] << 26) | (mask_p[13] << 24) 426 | (mask_p[12] << 22) | (mask_p[11] << 20) 427 | (mask_p[10] << 18) | (mask_p[9] << 16) 428 | (mask_p[8] << 14) | (mask_p[7] << 12) 429 | (mask_p[6] << 10) | (mask_p[5] << 8) 430 | (mask_p[4] << 6) | (mask_p[3] << 4) 431 | (mask_p[2] << 2) | (mask_p[1] << 0); 432 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 433 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 434 435 tmp_mask = (mask_p[30] << 28) 436 | (mask_p[29] << 26) | (mask_p[28] << 24) 437 | (mask_p[27] << 22) | (mask_p[26] << 20) 438 | (mask_p[25] << 18) | (mask_p[24] << 16) 439 | (mask_p[23] << 14) | (mask_p[22] << 12) 440 | (mask_p[21] << 10) | (mask_p[20] << 8) 441 | (mask_p[19] << 6) | (mask_p[18] << 4) 442 | (mask_p[17] << 2) | (mask_p[16] << 0); 443 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 444 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 445 446 tmp_mask = (mask_p[45] << 28) 447 | (mask_p[44] << 26) | (mask_p[43] << 24) 448 | (mask_p[42] << 22) | (mask_p[41] << 20) 449 | (mask_p[40] << 18) | (mask_p[39] << 16) 450 | (mask_p[38] << 14) | (mask_p[37] << 12) 451 | (mask_p[36] << 10) | (mask_p[35] << 8) 452 | (mask_p[34] << 6) | (mask_p[33] << 4) 453 | (mask_p[32] << 2) | (mask_p[31] << 0); 454 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 455 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 456 457 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 458 | (mask_p[59] << 26) | (mask_p[58] << 24) 459 | (mask_p[57] << 22) | (mask_p[56] << 20) 460 | (mask_p[55] << 18) | (mask_p[54] << 16) 461 | (mask_p[53] << 14) | (mask_p[52] << 12) 462 | (mask_p[51] << 10) | (mask_p[50] << 8) 463 | (mask_p[49] << 6) | (mask_p[48] << 4) 464 | (mask_p[47] << 2) | (mask_p[46] << 0); 465 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 466 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 467 } 468 469 /** 470 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 471 * @ah: atheros hardware structure 472 * 473 * Only required for older devices with external AR2133/AR5133 radios. 474 */ 475 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 476 { 477 int size = ah->iniBank6.ia_rows * sizeof(u32); 478 479 if (AR_SREV_9280_20_OR_LATER(ah)) 480 return 0; 481 482 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 483 if (!ah->analogBank6Data) 484 return -ENOMEM; 485 486 return 0; 487 } 488 489 490 /* * 491 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 492 * @ah: atheros hardware structure 493 * @chan: 494 * @modesIndex: 495 * 496 * Used for the external AR2133/AR5133 radios. 497 * 498 * Reads the EEPROM header info from the device structure and programs 499 * all rf registers. This routine requires access to the analog 500 * rf device. This is not required for single-chip devices. 501 */ 502 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 503 struct ath9k_channel *chan, 504 u16 modesIndex) 505 { 506 u32 eepMinorRev; 507 u32 ob5GHz = 0, db5GHz = 0; 508 u32 ob2GHz = 0, db2GHz = 0; 509 int regWrites = 0; 510 int i; 511 512 /* 513 * Software does not need to program bank data 514 * for single chip devices, that is AR9280 or anything 515 * after that. 516 */ 517 if (AR_SREV_9280_20_OR_LATER(ah)) 518 return true; 519 520 /* Setup rf parameters */ 521 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 522 523 for (i = 0; i < ah->iniBank6.ia_rows; i++) 524 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 525 526 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 527 if (eepMinorRev >= 2) { 528 if (IS_CHAN_2GHZ(chan)) { 529 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 530 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 531 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 532 ob2GHz, 3, 197, 0); 533 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 534 db2GHz, 3, 194, 0); 535 } else { 536 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 537 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 538 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 539 ob5GHz, 3, 203, 0); 540 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 541 db5GHz, 3, 200, 0); 542 } 543 } 544 545 /* Write Analog registers */ 546 REG_WRITE_ARRAY(&bank0, 1, regWrites); 547 REG_WRITE_ARRAY(&bank1, 1, regWrites); 548 REG_WRITE_ARRAY(&bank2, 1, regWrites); 549 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 550 ar5008_write_bank6(ah, ®Writes); 551 REG_WRITE_ARRAY(&bank7, 1, regWrites); 552 553 return true; 554 } 555 556 static void ar5008_hw_init_bb(struct ath_hw *ah, 557 struct ath9k_channel *chan) 558 { 559 u32 synthDelay; 560 561 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 562 563 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 564 565 ath9k_hw_synth_delay(ah, chan, synthDelay); 566 } 567 568 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 569 { 570 int rx_chainmask, tx_chainmask; 571 572 rx_chainmask = ah->rxchainmask; 573 tx_chainmask = ah->txchainmask; 574 575 576 switch (rx_chainmask) { 577 case 0x5: 578 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 579 AR_PHY_SWAP_ALT_CHAIN); 580 case 0x3: 581 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 582 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 583 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 584 break; 585 } 586 case 0x1: 587 case 0x2: 588 case 0x7: 589 ENABLE_REGWRITE_BUFFER(ah); 590 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 591 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 592 break; 593 default: 594 ENABLE_REGWRITE_BUFFER(ah); 595 break; 596 } 597 598 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 599 600 REGWRITE_BUFFER_FLUSH(ah); 601 602 if (tx_chainmask == 0x5) { 603 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 604 AR_PHY_SWAP_ALT_CHAIN); 605 } 606 if (AR_SREV_9100(ah)) 607 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 608 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 609 } 610 611 static void ar5008_hw_override_ini(struct ath_hw *ah, 612 struct ath9k_channel *chan) 613 { 614 u32 val; 615 616 /* 617 * Set the RX_ABORT and RX_DIS and clear if off only after 618 * RXE is set for MAC. This prevents frames with corrupted 619 * descriptor status. 620 */ 621 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 622 623 if (AR_SREV_9280_20_OR_LATER(ah)) { 624 /* 625 * For AR9280 and above, there is a new feature that allows 626 * Multicast search based on both MAC Address and Key ID. 627 * By default, this feature is enabled. But since the driver 628 * is not using this feature, we switch it off; otherwise 629 * multicast search based on MAC addr only will fail. 630 */ 631 val = REG_READ(ah, AR_PCU_MISC_MODE2) & 632 (~AR_ADHOC_MCAST_KEYID_ENABLE); 633 634 if (!AR_SREV_9271(ah)) 635 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 636 637 if (AR_SREV_9287_11_OR_LATER(ah)) 638 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 639 640 val |= AR_PCU_MISC_MODE2_CFP_IGNORE; 641 642 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 643 } 644 645 if (AR_SREV_9280_20_OR_LATER(ah)) 646 return; 647 /* 648 * Disable BB clock gating 649 * Necessary to avoid issues on AR5416 2.0 650 */ 651 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 652 653 /* 654 * Disable RIFS search on some chips to avoid baseband 655 * hang issues. 656 */ 657 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 658 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 659 val &= ~AR_PHY_RIFS_INIT_DELAY; 660 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 661 } 662 } 663 664 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 665 struct ath9k_channel *chan) 666 { 667 u32 phymode; 668 u32 enableDacFifo = 0; 669 670 if (AR_SREV_9285_12_OR_LATER(ah)) 671 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 672 AR_PHY_FC_ENABLE_DAC_FIFO); 673 674 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 675 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 676 677 if (IS_CHAN_HT40(chan)) { 678 phymode |= AR_PHY_FC_DYN2040_EN; 679 680 if (IS_CHAN_HT40PLUS(chan)) 681 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 682 683 } 684 REG_WRITE(ah, AR_PHY_TURBO, phymode); 685 686 ath9k_hw_set11nmac2040(ah, chan); 687 688 ENABLE_REGWRITE_BUFFER(ah); 689 690 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 691 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 692 693 REGWRITE_BUFFER_FLUSH(ah); 694 } 695 696 697 static int ar5008_hw_process_ini(struct ath_hw *ah, 698 struct ath9k_channel *chan) 699 { 700 struct ath_common *common = ath9k_hw_common(ah); 701 int i, regWrites = 0; 702 u32 modesIndex, freqIndex; 703 704 if (IS_CHAN_5GHZ(chan)) { 705 freqIndex = 1; 706 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 707 } else { 708 freqIndex = 2; 709 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 710 } 711 712 /* 713 * Set correct baseband to analog shift setting to 714 * access analog chips. 715 */ 716 REG_WRITE(ah, AR_PHY(0), 0x00000007); 717 718 /* Write ADDAC shifts */ 719 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 720 if (ah->eep_ops->set_addac) 721 ah->eep_ops->set_addac(ah, chan); 722 723 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 724 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 725 726 ENABLE_REGWRITE_BUFFER(ah); 727 728 for (i = 0; i < ah->iniModes.ia_rows; i++) { 729 u32 reg = INI_RA(&ah->iniModes, i, 0); 730 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 731 732 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 733 val &= ~AR_AN_TOP2_PWDCLKIND; 734 735 REG_WRITE(ah, reg, val); 736 737 if (reg >= 0x7800 && reg < 0x78a0 738 && ah->config.analog_shiftreg 739 && (common->bus_ops->ath_bus_type != ATH_USB)) { 740 udelay(100); 741 } 742 743 DO_DELAY(regWrites); 744 } 745 746 REGWRITE_BUFFER_FLUSH(ah); 747 748 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 749 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 750 751 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 752 AR_SREV_9287_11_OR_LATER(ah)) 753 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 754 755 if (AR_SREV_9271_10(ah)) { 756 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 757 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 758 } 759 760 ENABLE_REGWRITE_BUFFER(ah); 761 762 /* Write common array parameters */ 763 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 764 u32 reg = INI_RA(&ah->iniCommon, i, 0); 765 u32 val = INI_RA(&ah->iniCommon, i, 1); 766 767 REG_WRITE(ah, reg, val); 768 769 if (reg >= 0x7800 && reg < 0x78a0 770 && ah->config.analog_shiftreg 771 && (common->bus_ops->ath_bus_type != ATH_USB)) { 772 udelay(100); 773 } 774 775 DO_DELAY(regWrites); 776 } 777 778 REGWRITE_BUFFER_FLUSH(ah); 779 780 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 781 782 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 783 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 784 regWrites); 785 786 ar5008_hw_override_ini(ah, chan); 787 ar5008_hw_set_channel_regs(ah, chan); 788 ar5008_hw_init_chain_masks(ah); 789 ath9k_olc_init(ah); 790 ath9k_hw_apply_txpower(ah, chan, false); 791 792 /* Write analog registers */ 793 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 794 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 795 return -EIO; 796 } 797 798 return 0; 799 } 800 801 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 802 { 803 u32 rfMode = 0; 804 805 if (chan == NULL) 806 return; 807 808 if (IS_CHAN_2GHZ(chan)) 809 rfMode |= AR_PHY_MODE_DYNAMIC; 810 else 811 rfMode |= AR_PHY_MODE_OFDM; 812 813 if (!AR_SREV_9280_20_OR_LATER(ah)) 814 rfMode |= (IS_CHAN_5GHZ(chan)) ? 815 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 816 817 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 818 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 819 820 REG_WRITE(ah, AR_PHY_MODE, rfMode); 821 } 822 823 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 824 { 825 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 826 } 827 828 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 829 struct ath9k_channel *chan) 830 { 831 u32 coef_scaled, ds_coef_exp, ds_coef_man; 832 u32 clockMhzScaled = 0x64000000; 833 struct chan_centers centers; 834 835 if (IS_CHAN_HALF_RATE(chan)) 836 clockMhzScaled = clockMhzScaled >> 1; 837 else if (IS_CHAN_QUARTER_RATE(chan)) 838 clockMhzScaled = clockMhzScaled >> 2; 839 840 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 841 coef_scaled = clockMhzScaled / centers.synth_center; 842 843 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 844 &ds_coef_exp); 845 846 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 847 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 848 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 849 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 850 851 coef_scaled = (9 * coef_scaled) / 10; 852 853 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 854 &ds_coef_exp); 855 856 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 857 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 858 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 859 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 860 } 861 862 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 863 { 864 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 865 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 866 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 867 } 868 869 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 870 { 871 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 872 873 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 874 875 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 876 } 877 878 static void ar5008_restore_chainmask(struct ath_hw *ah) 879 { 880 int rx_chainmask = ah->rxchainmask; 881 882 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 883 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 884 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 885 } 886 } 887 888 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 889 struct ath9k_channel *chan) 890 { 891 u32 pll; 892 893 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 894 895 if (chan && IS_CHAN_HALF_RATE(chan)) 896 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 897 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 898 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 899 900 if (chan && IS_CHAN_5GHZ(chan)) 901 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 902 else 903 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 904 905 return pll; 906 } 907 908 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 909 struct ath9k_channel *chan) 910 { 911 u32 pll; 912 913 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 914 915 if (chan && IS_CHAN_HALF_RATE(chan)) 916 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 917 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 918 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 919 920 if (chan && IS_CHAN_5GHZ(chan)) 921 pll |= SM(0xa, AR_RTC_PLL_DIV); 922 else 923 pll |= SM(0xb, AR_RTC_PLL_DIV); 924 925 return pll; 926 } 927 928 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 929 enum ath9k_ani_cmd cmd, 930 int param) 931 { 932 struct ath_common *common = ath9k_hw_common(ah); 933 struct ath9k_channel *chan = ah->curchan; 934 struct ar5416AniState *aniState = &ah->ani; 935 s32 value; 936 937 switch (cmd & ah->ani_function) { 938 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 939 /* 940 * on == 1 means ofdm weak signal detection is ON 941 * on == 1 is the default, for less noise immunity 942 * 943 * on == 0 means ofdm weak signal detection is OFF 944 * on == 0 means more noise imm 945 */ 946 u32 on = param ? 1 : 0; 947 /* 948 * make register setting for default 949 * (weak sig detect ON) come from INI file 950 */ 951 int m1ThreshLow = on ? 952 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 953 int m2ThreshLow = on ? 954 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 955 int m1Thresh = on ? 956 aniState->iniDef.m1Thresh : m1Thresh_off; 957 int m2Thresh = on ? 958 aniState->iniDef.m2Thresh : m2Thresh_off; 959 int m2CountThr = on ? 960 aniState->iniDef.m2CountThr : m2CountThr_off; 961 int m2CountThrLow = on ? 962 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 963 int m1ThreshLowExt = on ? 964 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 965 int m2ThreshLowExt = on ? 966 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 967 int m1ThreshExt = on ? 968 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 969 int m2ThreshExt = on ? 970 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 971 972 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 973 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 974 m1ThreshLow); 975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 976 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 977 m2ThreshLow); 978 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 979 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 980 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 981 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 982 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 983 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 984 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 985 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 986 m2CountThrLow); 987 988 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 989 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 990 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 991 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 992 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 993 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 994 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 995 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 996 997 if (on) 998 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 999 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1000 else 1001 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1002 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1003 1004 if (on != aniState->ofdmWeakSigDetect) { 1005 ath_dbg(common, ANI, 1006 "** ch %d: ofdm weak signal: %s=>%s\n", 1007 chan->channel, 1008 aniState->ofdmWeakSigDetect ? 1009 "on" : "off", 1010 on ? "on" : "off"); 1011 if (on) 1012 ah->stats.ast_ani_ofdmon++; 1013 else 1014 ah->stats.ast_ani_ofdmoff++; 1015 aniState->ofdmWeakSigDetect = on; 1016 } 1017 break; 1018 } 1019 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1020 u32 level = param; 1021 1022 value = level * 2; 1023 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1024 AR_PHY_FIND_SIG_FIRSTEP, value); 1025 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1026 AR_PHY_FIND_SIG_FIRSTEP_LOW, value); 1027 1028 if (level != aniState->firstepLevel) { 1029 ath_dbg(common, ANI, 1030 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1031 chan->channel, 1032 aniState->firstepLevel, 1033 level, 1034 ATH9K_ANI_FIRSTEP_LVL, 1035 value, 1036 aniState->iniDef.firstep); 1037 ath_dbg(common, ANI, 1038 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1039 chan->channel, 1040 aniState->firstepLevel, 1041 level, 1042 ATH9K_ANI_FIRSTEP_LVL, 1043 value, 1044 aniState->iniDef.firstepLow); 1045 if (level > aniState->firstepLevel) 1046 ah->stats.ast_ani_stepup++; 1047 else if (level < aniState->firstepLevel) 1048 ah->stats.ast_ani_stepdown++; 1049 aniState->firstepLevel = level; 1050 } 1051 break; 1052 } 1053 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1054 u32 level = param; 1055 1056 value = (level + 1) * 2; 1057 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1058 AR_PHY_TIMING5_CYCPWR_THR1, value); 1059 1060 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1061 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); 1062 1063 if (level != aniState->spurImmunityLevel) { 1064 ath_dbg(common, ANI, 1065 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1066 chan->channel, 1067 aniState->spurImmunityLevel, 1068 level, 1069 ATH9K_ANI_SPUR_IMMUNE_LVL, 1070 value, 1071 aniState->iniDef.cycpwrThr1); 1072 ath_dbg(common, ANI, 1073 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1074 chan->channel, 1075 aniState->spurImmunityLevel, 1076 level, 1077 ATH9K_ANI_SPUR_IMMUNE_LVL, 1078 value, 1079 aniState->iniDef.cycpwrThr1Ext); 1080 if (level > aniState->spurImmunityLevel) 1081 ah->stats.ast_ani_spurup++; 1082 else if (level < aniState->spurImmunityLevel) 1083 ah->stats.ast_ani_spurdown++; 1084 aniState->spurImmunityLevel = level; 1085 } 1086 break; 1087 } 1088 case ATH9K_ANI_MRC_CCK: 1089 /* 1090 * You should not see this as AR5008, AR9001, AR9002 1091 * does not have hardware support for MRC CCK. 1092 */ 1093 WARN_ON(1); 1094 break; 1095 default: 1096 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1097 return false; 1098 } 1099 1100 ath_dbg(common, ANI, 1101 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1102 aniState->spurImmunityLevel, 1103 aniState->ofdmWeakSigDetect ? "on" : "off", 1104 aniState->firstepLevel, 1105 aniState->mrcCCK ? "on" : "off", 1106 aniState->listenTime, 1107 aniState->ofdmPhyErrCount, 1108 aniState->cckPhyErrCount); 1109 return true; 1110 } 1111 1112 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1113 int16_t nfarray[NUM_NF_READINGS]) 1114 { 1115 int16_t nf; 1116 1117 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1118 nfarray[0] = sign_extend32(nf, 8); 1119 1120 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1121 nfarray[1] = sign_extend32(nf, 8); 1122 1123 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1124 nfarray[2] = sign_extend32(nf, 8); 1125 1126 if (!IS_CHAN_HT40(ah->curchan)) 1127 return; 1128 1129 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1130 nfarray[3] = sign_extend32(nf, 8); 1131 1132 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1133 nfarray[4] = sign_extend32(nf, 8); 1134 1135 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1136 nfarray[5] = sign_extend32(nf, 8); 1137 } 1138 1139 /* 1140 * Initialize the ANI register values with default (ini) values. 1141 * This routine is called during a (full) hardware reset after 1142 * all the registers are initialised from the INI. 1143 */ 1144 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1145 { 1146 struct ath_common *common = ath9k_hw_common(ah); 1147 struct ath9k_channel *chan = ah->curchan; 1148 struct ar5416AniState *aniState = &ah->ani; 1149 struct ath9k_ani_default *iniDef; 1150 u32 val; 1151 1152 iniDef = &aniState->iniDef; 1153 1154 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1155 ah->hw_version.macVersion, 1156 ah->hw_version.macRev, 1157 ah->opmode, 1158 chan->channel); 1159 1160 val = REG_READ(ah, AR_PHY_SFCORR); 1161 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1162 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1163 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1164 1165 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1166 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1167 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1168 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1169 1170 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1171 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1172 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1173 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1174 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1175 iniDef->firstep = REG_READ_FIELD(ah, 1176 AR_PHY_FIND_SIG, 1177 AR_PHY_FIND_SIG_FIRSTEP); 1178 iniDef->firstepLow = REG_READ_FIELD(ah, 1179 AR_PHY_FIND_SIG_LOW, 1180 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1181 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1182 AR_PHY_TIMING5, 1183 AR_PHY_TIMING5_CYCPWR_THR1); 1184 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1185 AR_PHY_EXT_CCA, 1186 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1187 1188 /* these levels just got reset to defaults by the INI */ 1189 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1190 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1191 aniState->ofdmWeakSigDetect = true; 1192 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1193 } 1194 1195 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1196 { 1197 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1198 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1199 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1200 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1201 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1202 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1203 } 1204 1205 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1206 struct ath_hw_radar_conf *conf) 1207 { 1208 u32 radar_0 = 0, radar_1; 1209 1210 if (!conf) { 1211 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1212 return; 1213 } 1214 1215 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1216 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1217 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1218 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1219 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1220 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1221 1222 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1223 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1224 AR_PHY_RADAR_1_RELPWR_THRESH); 1225 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1226 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1227 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1228 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1229 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1230 1231 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1232 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1233 if (conf->ext_channel) 1234 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1235 else 1236 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1237 } 1238 1239 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1240 { 1241 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1242 1243 conf->fir_power = -33; 1244 conf->radar_rssi = 20; 1245 conf->pulse_height = 10; 1246 conf->pulse_rssi = 15; 1247 conf->pulse_inband = 15; 1248 conf->pulse_maxlen = 255; 1249 conf->pulse_inband_step = 12; 1250 conf->radar_inband = 8; 1251 } 1252 1253 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) 1254 { 1255 #define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x)) 1256 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); 1257 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], 1258 rate_array[rate2s])); 1259 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], 1260 rate_array[rate5_5s])); 1261 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], 1262 rate_array[rate11s])); 1263 #undef CCK_DELTA 1264 } 1265 1266 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, 1267 int offset) 1268 { 1269 int i, idx = 0; 1270 1271 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) { 1272 ah->tx_power[i] = rate_array[idx]; 1273 idx++; 1274 } 1275 } 1276 1277 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, 1278 int ss_offset, int ds_offset, 1279 bool is_40, int ht40_delta) 1280 { 1281 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT; 1282 1283 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) { 1284 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; 1285 mcs_idx++; 1286 } 1287 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], 1288 AR5008_HT_SS_RATES); 1289 } 1290 1291 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1292 struct ath9k_channel *chan, int ht40_delta) 1293 { 1294 if (IS_CHAN_5GHZ(chan)) { 1295 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1296 AR5008_11NA_OFDM_SHIFT); 1297 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1298 ar5008_hw_init_txpower_ht(ah, rate_array, 1299 AR5008_11NA_HT_SS_SHIFT, 1300 AR5008_11NA_HT_DS_SHIFT, 1301 IS_CHAN_HT40(chan), 1302 ht40_delta); 1303 } 1304 } else { 1305 ar5008_hw_init_txpower_cck(ah, rate_array); 1306 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1307 AR5008_11NG_OFDM_SHIFT); 1308 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1309 ar5008_hw_init_txpower_ht(ah, rate_array, 1310 AR5008_11NG_HT_SS_SHIFT, 1311 AR5008_11NG_HT_DS_SHIFT, 1312 IS_CHAN_HT40(chan), 1313 ht40_delta); 1314 } 1315 } 1316 } 1317 1318 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1319 { 1320 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1321 static const u32 ar5416_cca_regs[6] = { 1322 AR_PHY_CCA, 1323 AR_PHY_CH1_CCA, 1324 AR_PHY_CH2_CCA, 1325 AR_PHY_EXT_CCA, 1326 AR_PHY_CH1_EXT_CCA, 1327 AR_PHY_CH2_EXT_CCA 1328 }; 1329 int ret; 1330 1331 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1332 if (ret) 1333 return ret; 1334 1335 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1336 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1337 1338 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1339 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1340 priv_ops->init_bb = ar5008_hw_init_bb; 1341 priv_ops->process_ini = ar5008_hw_process_ini; 1342 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1343 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1344 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1345 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1346 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1347 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1348 priv_ops->do_getnf = ar5008_hw_do_getnf; 1349 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1350 1351 priv_ops->ani_control = ar5008_hw_ani_control_new; 1352 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1353 1354 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1355 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1356 else 1357 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1358 1359 ar5008_hw_set_nf_limits(ah); 1360 ar5008_hw_set_radar_conf(ah); 1361 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1362 return 0; 1363 } 1364