1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 #include "ar5008_initvals.h" 22 23 /* All code below is for AR5008, AR9001, AR9002 */ 24 25 #define AR5008_OFDM_RATES 8 26 #define AR5008_HT_SS_RATES 8 27 #define AR5008_HT_DS_RATES 8 28 29 #define AR5008_HT20_SHIFT 16 30 #define AR5008_HT40_SHIFT 24 31 32 #define AR5008_11NA_OFDM_SHIFT 0 33 #define AR5008_11NA_HT_SS_SHIFT 8 34 #define AR5008_11NA_HT_DS_SHIFT 16 35 36 #define AR5008_11NG_OFDM_SHIFT 4 37 #define AR5008_11NG_HT_SS_SHIFT 12 38 #define AR5008_11NG_HT_DS_SHIFT 20 39 40 static const int firstep_table[] = 41 /* level: 0 1 2 3 4 5 6 7 8 */ 42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 43 44 /* 45 * register values to turn OFDM weak signal detection OFF 46 */ 47 static const int m1ThreshLow_off = 127; 48 static const int m2ThreshLow_off = 127; 49 static const int m1Thresh_off = 127; 50 static const int m2Thresh_off = 127; 51 static const int m2CountThr_off = 31; 52 static const int m2CountThrLow_off = 63; 53 static const int m1ThreshLowExt_off = 127; 54 static const int m2ThreshLowExt_off = 127; 55 static const int m1ThreshExt_off = 127; 56 static const int m2ThreshExt_off = 127; 57 58 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 59 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 60 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 61 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 62 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 63 64 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 65 { 66 struct ar5416IniArray *array = &ah->iniBank6; 67 u32 *data = ah->analogBank6Data; 68 int r; 69 70 ENABLE_REGWRITE_BUFFER(ah); 71 72 for (r = 0; r < array->ia_rows; r++) { 73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 74 DO_DELAY(*writecnt); 75 } 76 77 REGWRITE_BUFFER_FLUSH(ah); 78 } 79 80 /** 81 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 82 * @rfbuf: 83 * @reg32: 84 * @numBits: 85 * @firstBit: 86 * @column: 87 * 88 * Performs analog "swizzling" of parameters into their location. 89 * Used on external AR2133/AR5133 radios. 90 */ 91 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 92 u32 numBits, u32 firstBit, 93 u32 column) 94 { 95 u32 tmp32, mask, arrayEntry, lastBit; 96 int32_t bitPosition, bitsLeft; 97 98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 99 arrayEntry = (firstBit - 1) / 8; 100 bitPosition = (firstBit - 1) % 8; 101 bitsLeft = numBits; 102 while (bitsLeft > 0) { 103 lastBit = (bitPosition + bitsLeft > 8) ? 104 8 : bitPosition + bitsLeft; 105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 106 (column * 8); 107 rfBuf[arrayEntry] &= ~mask; 108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 109 (column * 8)) & mask; 110 bitsLeft -= 8 - bitPosition; 111 tmp32 = tmp32 >> (8 - bitPosition); 112 bitPosition = 0; 113 arrayEntry++; 114 } 115 } 116 117 /* 118 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 119 * rf_pwd_icsyndiv. 120 * 121 * Theoretical Rules: 122 * if 2 GHz band 123 * if forceBiasAuto 124 * if synth_freq < 2412 125 * bias = 0 126 * else if 2412 <= synth_freq <= 2422 127 * bias = 1 128 * else // synth_freq > 2422 129 * bias = 2 130 * else if forceBias > 0 131 * bias = forceBias & 7 132 * else 133 * no change, use value from ini file 134 * else 135 * no change, invalid band 136 * 137 * 1st Mod: 138 * 2422 also uses value of 2 139 * <approved> 140 * 141 * 2nd Mod: 142 * Less than 2412 uses value of 0, 2412 and above uses value of 2 143 */ 144 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 145 { 146 struct ath_common *common = ath9k_hw_common(ah); 147 u32 tmp_reg; 148 int reg_writes = 0; 149 u32 new_bias = 0; 150 151 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 152 return; 153 154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 155 156 if (synth_freq < 2412) 157 new_bias = 0; 158 else if (synth_freq < 2422) 159 new_bias = 1; 160 else 161 new_bias = 2; 162 163 /* pre-reverse this field */ 164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 165 166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 167 new_bias, synth_freq); 168 169 /* swizzle rf_pwd_icsyndiv */ 170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 171 172 /* write Bank 6 with new params */ 173 ar5008_write_bank6(ah, ®_writes); 174 } 175 176 /** 177 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 178 * @ah: atheros hardware structure 179 * @chan: 180 * 181 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 182 * the channel value. Assumes writes enabled to analog bus and bank6 register 183 * cache in ah->analogBank6Data. 184 */ 185 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 186 { 187 struct ath_common *common = ath9k_hw_common(ah); 188 u32 channelSel = 0; 189 u32 bModeSynth = 0; 190 u32 aModeRefSel = 0; 191 u32 reg32 = 0; 192 u16 freq; 193 struct chan_centers centers; 194 195 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 196 freq = centers.synth_center; 197 198 if (freq < 4800) { 199 u32 txctl; 200 201 if (((freq - 2192) % 5) == 0) { 202 channelSel = ((freq - 672) * 2 - 3040) / 10; 203 bModeSynth = 0; 204 } else if (((freq - 2224) % 5) == 0) { 205 channelSel = ((freq - 704) * 2 - 3040) / 10; 206 bModeSynth = 1; 207 } else { 208 ath_err(common, "Invalid channel %u MHz\n", freq); 209 return -EINVAL; 210 } 211 212 channelSel = (channelSel << 2) & 0xff; 213 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 214 215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 216 if (freq == 2484) { 217 218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 220 } else { 221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 223 } 224 225 } else if ((freq % 20) == 0 && freq >= 5120) { 226 channelSel = 227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 228 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 229 } else if ((freq % 10) == 0) { 230 channelSel = 231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 233 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 234 else 235 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 236 } else if ((freq % 5) == 0) { 237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 238 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 239 } else { 240 ath_err(common, "Invalid channel %u MHz\n", freq); 241 return -EINVAL; 242 } 243 244 ar5008_hw_force_bias(ah, freq); 245 246 reg32 = 247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 248 (1 << 5) | 0x1; 249 250 REG_WRITE(ah, AR_PHY(0x37), reg32); 251 252 ah->curchan = chan; 253 254 return 0; 255 } 256 257 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah, 258 struct ath9k_channel *chan, int bin) 259 { 260 int cur_bin; 261 int upper, lower, cur_vit_mask; 262 int i; 263 int8_t mask_m[123]; 264 int8_t mask_p[123]; 265 int8_t mask_amt; 266 int tmp_mask; 267 static const int pilot_mask_reg[4] = { 268 AR_PHY_TIMING7, AR_PHY_TIMING8, 269 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 270 }; 271 static const int chan_mask_reg[4] = { 272 AR_PHY_TIMING9, AR_PHY_TIMING10, 273 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 274 }; 275 static const int inc[4] = { 0, 100, 0, 0 }; 276 277 memset(&mask_m, 0, sizeof(int8_t) * 123); 278 memset(&mask_p, 0, sizeof(int8_t) * 123); 279 280 cur_bin = -6000; 281 upper = bin + 100; 282 lower = bin - 100; 283 284 for (i = 0; i < 4; i++) { 285 int pilot_mask = 0; 286 int chan_mask = 0; 287 int bp = 0; 288 289 for (bp = 0; bp < 30; bp++) { 290 if ((cur_bin > lower) && (cur_bin < upper)) { 291 pilot_mask = pilot_mask | 0x1 << bp; 292 chan_mask = chan_mask | 0x1 << bp; 293 } 294 cur_bin += 100; 295 } 296 cur_bin += inc[i]; 297 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 298 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 299 } 300 301 cur_vit_mask = 6100; 302 upper = bin + 120; 303 lower = bin - 120; 304 305 for (i = 0; i < 123; i++) { 306 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 307 /* workaround for gcc bug #37014 */ 308 volatile int tmp_v = abs(cur_vit_mask - bin); 309 310 if (tmp_v < 75) 311 mask_amt = 1; 312 else 313 mask_amt = 0; 314 if (cur_vit_mask < 0) 315 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 316 else 317 mask_p[cur_vit_mask / 100] = mask_amt; 318 } 319 cur_vit_mask -= 100; 320 } 321 322 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 323 | (mask_m[48] << 26) | (mask_m[49] << 24) 324 | (mask_m[50] << 22) | (mask_m[51] << 20) 325 | (mask_m[52] << 18) | (mask_m[53] << 16) 326 | (mask_m[54] << 14) | (mask_m[55] << 12) 327 | (mask_m[56] << 10) | (mask_m[57] << 8) 328 | (mask_m[58] << 6) | (mask_m[59] << 4) 329 | (mask_m[60] << 2) | (mask_m[61] << 0); 330 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 331 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 332 333 tmp_mask = (mask_m[31] << 28) 334 | (mask_m[32] << 26) | (mask_m[33] << 24) 335 | (mask_m[34] << 22) | (mask_m[35] << 20) 336 | (mask_m[36] << 18) | (mask_m[37] << 16) 337 | (mask_m[48] << 14) | (mask_m[39] << 12) 338 | (mask_m[40] << 10) | (mask_m[41] << 8) 339 | (mask_m[42] << 6) | (mask_m[43] << 4) 340 | (mask_m[44] << 2) | (mask_m[45] << 0); 341 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 342 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 343 344 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 345 | (mask_m[18] << 26) | (mask_m[18] << 24) 346 | (mask_m[20] << 22) | (mask_m[20] << 20) 347 | (mask_m[22] << 18) | (mask_m[22] << 16) 348 | (mask_m[24] << 14) | (mask_m[24] << 12) 349 | (mask_m[25] << 10) | (mask_m[26] << 8) 350 | (mask_m[27] << 6) | (mask_m[28] << 4) 351 | (mask_m[29] << 2) | (mask_m[30] << 0); 352 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 353 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 354 355 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 356 | (mask_m[2] << 26) | (mask_m[3] << 24) 357 | (mask_m[4] << 22) | (mask_m[5] << 20) 358 | (mask_m[6] << 18) | (mask_m[7] << 16) 359 | (mask_m[8] << 14) | (mask_m[9] << 12) 360 | (mask_m[10] << 10) | (mask_m[11] << 8) 361 | (mask_m[12] << 6) | (mask_m[13] << 4) 362 | (mask_m[14] << 2) | (mask_m[15] << 0); 363 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 364 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 365 366 tmp_mask = (mask_p[15] << 28) 367 | (mask_p[14] << 26) | (mask_p[13] << 24) 368 | (mask_p[12] << 22) | (mask_p[11] << 20) 369 | (mask_p[10] << 18) | (mask_p[9] << 16) 370 | (mask_p[8] << 14) | (mask_p[7] << 12) 371 | (mask_p[6] << 10) | (mask_p[5] << 8) 372 | (mask_p[4] << 6) | (mask_p[3] << 4) 373 | (mask_p[2] << 2) | (mask_p[1] << 0); 374 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 375 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 376 377 tmp_mask = (mask_p[30] << 28) 378 | (mask_p[29] << 26) | (mask_p[28] << 24) 379 | (mask_p[27] << 22) | (mask_p[26] << 20) 380 | (mask_p[25] << 18) | (mask_p[24] << 16) 381 | (mask_p[23] << 14) | (mask_p[22] << 12) 382 | (mask_p[21] << 10) | (mask_p[20] << 8) 383 | (mask_p[19] << 6) | (mask_p[18] << 4) 384 | (mask_p[17] << 2) | (mask_p[16] << 0); 385 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 386 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 387 388 tmp_mask = (mask_p[45] << 28) 389 | (mask_p[44] << 26) | (mask_p[43] << 24) 390 | (mask_p[42] << 22) | (mask_p[41] << 20) 391 | (mask_p[40] << 18) | (mask_p[39] << 16) 392 | (mask_p[38] << 14) | (mask_p[37] << 12) 393 | (mask_p[36] << 10) | (mask_p[35] << 8) 394 | (mask_p[34] << 6) | (mask_p[33] << 4) 395 | (mask_p[32] << 2) | (mask_p[31] << 0); 396 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 397 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 398 399 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 400 | (mask_p[59] << 26) | (mask_p[58] << 24) 401 | (mask_p[57] << 22) | (mask_p[56] << 20) 402 | (mask_p[55] << 18) | (mask_p[54] << 16) 403 | (mask_p[53] << 14) | (mask_p[52] << 12) 404 | (mask_p[51] << 10) | (mask_p[50] << 8) 405 | (mask_p[49] << 6) | (mask_p[48] << 4) 406 | (mask_p[47] << 2) | (mask_p[46] << 0); 407 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 408 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 409 } 410 411 /** 412 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 413 * @ah: atheros hardware structure 414 * @chan: 415 * 416 * For non single-chip solutions. Converts to baseband spur frequency given the 417 * input channel frequency and compute register settings below. 418 */ 419 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 420 struct ath9k_channel *chan) 421 { 422 int bb_spur = AR_NO_SPUR; 423 int bin; 424 int spur_freq_sd; 425 int spur_delta_phase; 426 int denominator; 427 int tmp, new; 428 int i; 429 430 int cur_bb_spur; 431 bool is2GHz = IS_CHAN_2GHZ(chan); 432 433 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 434 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 435 if (AR_NO_SPUR == cur_bb_spur) 436 break; 437 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 438 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 439 bb_spur = cur_bb_spur; 440 break; 441 } 442 } 443 444 if (AR_NO_SPUR == bb_spur) 445 return; 446 447 bin = bb_spur * 32; 448 449 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 450 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 451 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 452 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 453 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 454 455 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 456 457 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 458 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 459 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 460 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 461 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 462 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 463 464 spur_delta_phase = ((bb_spur * 524288) / 100) & 465 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 466 467 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 468 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 469 470 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 471 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 472 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 473 REG_WRITE(ah, AR_PHY_TIMING11, new); 474 475 ar5008_hw_cmn_spur_mitigate(ah, chan, bin); 476 } 477 478 /** 479 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 480 * @ah: atheros hardware structure 481 * 482 * Only required for older devices with external AR2133/AR5133 radios. 483 */ 484 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 485 { 486 int size = ah->iniBank6.ia_rows * sizeof(u32); 487 488 if (AR_SREV_9280_20_OR_LATER(ah)) 489 return 0; 490 491 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 492 if (!ah->analogBank6Data) 493 return -ENOMEM; 494 495 return 0; 496 } 497 498 499 /* * 500 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 501 * @ah: atheros hardware structure 502 * @chan: 503 * @modesIndex: 504 * 505 * Used for the external AR2133/AR5133 radios. 506 * 507 * Reads the EEPROM header info from the device structure and programs 508 * all rf registers. This routine requires access to the analog 509 * rf device. This is not required for single-chip devices. 510 */ 511 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 512 struct ath9k_channel *chan, 513 u16 modesIndex) 514 { 515 u32 eepMinorRev; 516 u32 ob5GHz = 0, db5GHz = 0; 517 u32 ob2GHz = 0, db2GHz = 0; 518 int regWrites = 0; 519 int i; 520 521 /* 522 * Software does not need to program bank data 523 * for single chip devices, that is AR9280 or anything 524 * after that. 525 */ 526 if (AR_SREV_9280_20_OR_LATER(ah)) 527 return true; 528 529 /* Setup rf parameters */ 530 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 531 532 for (i = 0; i < ah->iniBank6.ia_rows; i++) 533 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 534 535 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 536 if (eepMinorRev >= 2) { 537 if (IS_CHAN_2GHZ(chan)) { 538 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 539 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 540 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 541 ob2GHz, 3, 197, 0); 542 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 543 db2GHz, 3, 194, 0); 544 } else { 545 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 546 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 547 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 548 ob5GHz, 3, 203, 0); 549 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 550 db5GHz, 3, 200, 0); 551 } 552 } 553 554 /* Write Analog registers */ 555 REG_WRITE_ARRAY(&bank0, 1, regWrites); 556 REG_WRITE_ARRAY(&bank1, 1, regWrites); 557 REG_WRITE_ARRAY(&bank2, 1, regWrites); 558 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 559 ar5008_write_bank6(ah, ®Writes); 560 REG_WRITE_ARRAY(&bank7, 1, regWrites); 561 562 return true; 563 } 564 565 static void ar5008_hw_init_bb(struct ath_hw *ah, 566 struct ath9k_channel *chan) 567 { 568 u32 synthDelay; 569 570 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 571 572 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 573 574 ath9k_hw_synth_delay(ah, chan, synthDelay); 575 } 576 577 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 578 { 579 int rx_chainmask, tx_chainmask; 580 581 rx_chainmask = ah->rxchainmask; 582 tx_chainmask = ah->txchainmask; 583 584 585 switch (rx_chainmask) { 586 case 0x5: 587 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 588 AR_PHY_SWAP_ALT_CHAIN); 589 case 0x3: 590 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 591 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 592 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 593 break; 594 } 595 case 0x1: 596 case 0x2: 597 case 0x7: 598 ENABLE_REGWRITE_BUFFER(ah); 599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 601 break; 602 default: 603 ENABLE_REGWRITE_BUFFER(ah); 604 break; 605 } 606 607 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 608 609 REGWRITE_BUFFER_FLUSH(ah); 610 611 if (tx_chainmask == 0x5) { 612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 613 AR_PHY_SWAP_ALT_CHAIN); 614 } 615 if (AR_SREV_9100(ah)) 616 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 617 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 618 } 619 620 static void ar5008_hw_override_ini(struct ath_hw *ah, 621 struct ath9k_channel *chan) 622 { 623 u32 val; 624 625 /* 626 * Set the RX_ABORT and RX_DIS and clear if off only after 627 * RXE is set for MAC. This prevents frames with corrupted 628 * descriptor status. 629 */ 630 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 631 632 if (AR_SREV_9280_20_OR_LATER(ah)) { 633 /* 634 * For AR9280 and above, there is a new feature that allows 635 * Multicast search based on both MAC Address and Key ID. 636 * By default, this feature is enabled. But since the driver 637 * is not using this feature, we switch it off; otherwise 638 * multicast search based on MAC addr only will fail. 639 */ 640 val = REG_READ(ah, AR_PCU_MISC_MODE2) & 641 (~AR_ADHOC_MCAST_KEYID_ENABLE); 642 643 if (!AR_SREV_9271(ah)) 644 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 645 646 if (AR_SREV_9287_11_OR_LATER(ah)) 647 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 648 649 val |= AR_PCU_MISC_MODE2_CFP_IGNORE; 650 651 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 652 } 653 654 if (AR_SREV_9280_20_OR_LATER(ah)) 655 return; 656 /* 657 * Disable BB clock gating 658 * Necessary to avoid issues on AR5416 2.0 659 */ 660 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 661 662 /* 663 * Disable RIFS search on some chips to avoid baseband 664 * hang issues. 665 */ 666 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 667 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 668 val &= ~AR_PHY_RIFS_INIT_DELAY; 669 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 670 } 671 } 672 673 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 674 struct ath9k_channel *chan) 675 { 676 u32 phymode; 677 u32 enableDacFifo = 0; 678 679 if (AR_SREV_9285_12_OR_LATER(ah)) 680 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 681 AR_PHY_FC_ENABLE_DAC_FIFO); 682 683 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 684 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 685 686 if (IS_CHAN_HT40(chan)) { 687 phymode |= AR_PHY_FC_DYN2040_EN; 688 689 if (IS_CHAN_HT40PLUS(chan)) 690 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 691 692 } 693 ENABLE_REGWRITE_BUFFER(ah); 694 REG_WRITE(ah, AR_PHY_TURBO, phymode); 695 696 /* This function do only REG_WRITE, so 697 * we can include it to REGWRITE_BUFFER. */ 698 ath9k_hw_set11nmac2040(ah, chan); 699 700 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 701 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 702 703 REGWRITE_BUFFER_FLUSH(ah); 704 } 705 706 707 static int ar5008_hw_process_ini(struct ath_hw *ah, 708 struct ath9k_channel *chan) 709 { 710 struct ath_common *common = ath9k_hw_common(ah); 711 int i, regWrites = 0; 712 u32 modesIndex, freqIndex; 713 714 if (IS_CHAN_5GHZ(chan)) { 715 freqIndex = 1; 716 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 717 } else { 718 freqIndex = 2; 719 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 720 } 721 722 /* 723 * Set correct baseband to analog shift setting to 724 * access analog chips. 725 */ 726 REG_WRITE(ah, AR_PHY(0), 0x00000007); 727 728 /* Write ADDAC shifts */ 729 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 730 if (ah->eep_ops->set_addac) 731 ah->eep_ops->set_addac(ah, chan); 732 733 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 734 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 735 736 ENABLE_REGWRITE_BUFFER(ah); 737 738 for (i = 0; i < ah->iniModes.ia_rows; i++) { 739 u32 reg = INI_RA(&ah->iniModes, i, 0); 740 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 741 742 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 743 val &= ~AR_AN_TOP2_PWDCLKIND; 744 745 REG_WRITE(ah, reg, val); 746 747 if (reg >= 0x7800 && reg < 0x78a0 748 && ah->config.analog_shiftreg 749 && (common->bus_ops->ath_bus_type != ATH_USB)) { 750 udelay(100); 751 } 752 753 DO_DELAY(regWrites); 754 } 755 756 REGWRITE_BUFFER_FLUSH(ah); 757 758 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 759 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 760 761 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 762 AR_SREV_9287_11_OR_LATER(ah)) 763 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 764 765 if (AR_SREV_9271_10(ah)) { 766 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 767 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 768 } 769 770 ENABLE_REGWRITE_BUFFER(ah); 771 772 /* Write common array parameters */ 773 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 774 u32 reg = INI_RA(&ah->iniCommon, i, 0); 775 u32 val = INI_RA(&ah->iniCommon, i, 1); 776 777 REG_WRITE(ah, reg, val); 778 779 if (reg >= 0x7800 && reg < 0x78a0 780 && ah->config.analog_shiftreg 781 && (common->bus_ops->ath_bus_type != ATH_USB)) { 782 udelay(100); 783 } 784 785 DO_DELAY(regWrites); 786 } 787 788 REGWRITE_BUFFER_FLUSH(ah); 789 790 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 791 792 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 793 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 794 regWrites); 795 796 ar5008_hw_override_ini(ah, chan); 797 ar5008_hw_set_channel_regs(ah, chan); 798 ar5008_hw_init_chain_masks(ah); 799 ath9k_olc_init(ah); 800 ath9k_hw_apply_txpower(ah, chan, false); 801 802 /* Write analog registers */ 803 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 804 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 805 return -EIO; 806 } 807 808 return 0; 809 } 810 811 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 812 { 813 u32 rfMode = 0; 814 815 if (chan == NULL) 816 return; 817 818 if (IS_CHAN_2GHZ(chan)) 819 rfMode |= AR_PHY_MODE_DYNAMIC; 820 else 821 rfMode |= AR_PHY_MODE_OFDM; 822 823 if (!AR_SREV_9280_20_OR_LATER(ah)) 824 rfMode |= (IS_CHAN_5GHZ(chan)) ? 825 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 826 827 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 828 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 829 830 REG_WRITE(ah, AR_PHY_MODE, rfMode); 831 } 832 833 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 834 { 835 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 836 } 837 838 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 839 struct ath9k_channel *chan) 840 { 841 u32 coef_scaled, ds_coef_exp, ds_coef_man; 842 u32 clockMhzScaled = 0x64000000; 843 struct chan_centers centers; 844 845 if (IS_CHAN_HALF_RATE(chan)) 846 clockMhzScaled = clockMhzScaled >> 1; 847 else if (IS_CHAN_QUARTER_RATE(chan)) 848 clockMhzScaled = clockMhzScaled >> 2; 849 850 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 851 coef_scaled = clockMhzScaled / centers.synth_center; 852 853 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 854 &ds_coef_exp); 855 856 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 857 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 858 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 859 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 860 861 coef_scaled = (9 * coef_scaled) / 10; 862 863 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 864 &ds_coef_exp); 865 866 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 867 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 868 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 869 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 870 } 871 872 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 873 { 874 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 875 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 876 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 877 } 878 879 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 880 { 881 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 882 883 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 884 885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 886 } 887 888 static void ar5008_restore_chainmask(struct ath_hw *ah) 889 { 890 int rx_chainmask = ah->rxchainmask; 891 892 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 893 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 894 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 895 } 896 } 897 898 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 899 struct ath9k_channel *chan) 900 { 901 u32 pll; 902 903 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 904 905 if (chan && IS_CHAN_HALF_RATE(chan)) 906 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 907 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 908 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 909 910 if (chan && IS_CHAN_5GHZ(chan)) 911 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 912 else 913 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 914 915 return pll; 916 } 917 918 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 919 struct ath9k_channel *chan) 920 { 921 u32 pll; 922 923 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 924 925 if (chan && IS_CHAN_HALF_RATE(chan)) 926 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 927 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 928 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 929 930 if (chan && IS_CHAN_5GHZ(chan)) 931 pll |= SM(0xa, AR_RTC_PLL_DIV); 932 else 933 pll |= SM(0xb, AR_RTC_PLL_DIV); 934 935 return pll; 936 } 937 938 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 939 enum ath9k_ani_cmd cmd, 940 int param) 941 { 942 struct ath_common *common = ath9k_hw_common(ah); 943 struct ath9k_channel *chan = ah->curchan; 944 struct ar5416AniState *aniState = &ah->ani; 945 s32 value; 946 947 switch (cmd & ah->ani_function) { 948 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 949 /* 950 * on == 1 means ofdm weak signal detection is ON 951 * on == 1 is the default, for less noise immunity 952 * 953 * on == 0 means ofdm weak signal detection is OFF 954 * on == 0 means more noise imm 955 */ 956 u32 on = param ? 1 : 0; 957 /* 958 * make register setting for default 959 * (weak sig detect ON) come from INI file 960 */ 961 int m1ThreshLow = on ? 962 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 963 int m2ThreshLow = on ? 964 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 965 int m1Thresh = on ? 966 aniState->iniDef.m1Thresh : m1Thresh_off; 967 int m2Thresh = on ? 968 aniState->iniDef.m2Thresh : m2Thresh_off; 969 int m2CountThr = on ? 970 aniState->iniDef.m2CountThr : m2CountThr_off; 971 int m2CountThrLow = on ? 972 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 973 int m1ThreshLowExt = on ? 974 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 975 int m2ThreshLowExt = on ? 976 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 977 int m1ThreshExt = on ? 978 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 979 int m2ThreshExt = on ? 980 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 981 982 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 983 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 984 m1ThreshLow); 985 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 986 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 987 m2ThreshLow); 988 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 989 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 990 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 991 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 992 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 993 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 994 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 995 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 996 m2CountThrLow); 997 998 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 999 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1001 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1003 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1004 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1005 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1006 1007 if (on) 1008 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1009 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1010 else 1011 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1012 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1013 1014 if (on != aniState->ofdmWeakSigDetect) { 1015 ath_dbg(common, ANI, 1016 "** ch %d: ofdm weak signal: %s=>%s\n", 1017 chan->channel, 1018 aniState->ofdmWeakSigDetect ? 1019 "on" : "off", 1020 on ? "on" : "off"); 1021 if (on) 1022 ah->stats.ast_ani_ofdmon++; 1023 else 1024 ah->stats.ast_ani_ofdmoff++; 1025 aniState->ofdmWeakSigDetect = on; 1026 } 1027 break; 1028 } 1029 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1030 u32 level = param; 1031 1032 value = level * 2; 1033 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1034 AR_PHY_FIND_SIG_FIRSTEP, value); 1035 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1036 AR_PHY_FIND_SIG_FIRSTEP_LOW, value); 1037 1038 if (level != aniState->firstepLevel) { 1039 ath_dbg(common, ANI, 1040 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1041 chan->channel, 1042 aniState->firstepLevel, 1043 level, 1044 ATH9K_ANI_FIRSTEP_LVL, 1045 value, 1046 aniState->iniDef.firstep); 1047 ath_dbg(common, ANI, 1048 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1049 chan->channel, 1050 aniState->firstepLevel, 1051 level, 1052 ATH9K_ANI_FIRSTEP_LVL, 1053 value, 1054 aniState->iniDef.firstepLow); 1055 if (level > aniState->firstepLevel) 1056 ah->stats.ast_ani_stepup++; 1057 else if (level < aniState->firstepLevel) 1058 ah->stats.ast_ani_stepdown++; 1059 aniState->firstepLevel = level; 1060 } 1061 break; 1062 } 1063 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1064 u32 level = param; 1065 1066 value = (level + 1) * 2; 1067 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1068 AR_PHY_TIMING5_CYCPWR_THR1, value); 1069 1070 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1071 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); 1072 1073 if (level != aniState->spurImmunityLevel) { 1074 ath_dbg(common, ANI, 1075 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1076 chan->channel, 1077 aniState->spurImmunityLevel, 1078 level, 1079 ATH9K_ANI_SPUR_IMMUNE_LVL, 1080 value, 1081 aniState->iniDef.cycpwrThr1); 1082 ath_dbg(common, ANI, 1083 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1084 chan->channel, 1085 aniState->spurImmunityLevel, 1086 level, 1087 ATH9K_ANI_SPUR_IMMUNE_LVL, 1088 value, 1089 aniState->iniDef.cycpwrThr1Ext); 1090 if (level > aniState->spurImmunityLevel) 1091 ah->stats.ast_ani_spurup++; 1092 else if (level < aniState->spurImmunityLevel) 1093 ah->stats.ast_ani_spurdown++; 1094 aniState->spurImmunityLevel = level; 1095 } 1096 break; 1097 } 1098 case ATH9K_ANI_MRC_CCK: 1099 /* 1100 * You should not see this as AR5008, AR9001, AR9002 1101 * does not have hardware support for MRC CCK. 1102 */ 1103 WARN_ON(1); 1104 break; 1105 default: 1106 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1107 return false; 1108 } 1109 1110 ath_dbg(common, ANI, 1111 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1112 aniState->spurImmunityLevel, 1113 aniState->ofdmWeakSigDetect ? "on" : "off", 1114 aniState->firstepLevel, 1115 aniState->mrcCCK ? "on" : "off", 1116 aniState->listenTime, 1117 aniState->ofdmPhyErrCount, 1118 aniState->cckPhyErrCount); 1119 return true; 1120 } 1121 1122 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1123 int16_t nfarray[NUM_NF_READINGS]) 1124 { 1125 int16_t nf; 1126 1127 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1128 nfarray[0] = sign_extend32(nf, 8); 1129 1130 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1131 nfarray[1] = sign_extend32(nf, 8); 1132 1133 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1134 nfarray[2] = sign_extend32(nf, 8); 1135 1136 if (!IS_CHAN_HT40(ah->curchan)) 1137 return; 1138 1139 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1140 nfarray[3] = sign_extend32(nf, 8); 1141 1142 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1143 nfarray[4] = sign_extend32(nf, 8); 1144 1145 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1146 nfarray[5] = sign_extend32(nf, 8); 1147 } 1148 1149 /* 1150 * Initialize the ANI register values with default (ini) values. 1151 * This routine is called during a (full) hardware reset after 1152 * all the registers are initialised from the INI. 1153 */ 1154 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1155 { 1156 struct ath_common *common = ath9k_hw_common(ah); 1157 struct ath9k_channel *chan = ah->curchan; 1158 struct ar5416AniState *aniState = &ah->ani; 1159 struct ath9k_ani_default *iniDef; 1160 u32 val; 1161 1162 iniDef = &aniState->iniDef; 1163 1164 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1165 ah->hw_version.macVersion, 1166 ah->hw_version.macRev, 1167 ah->opmode, 1168 chan->channel); 1169 1170 val = REG_READ(ah, AR_PHY_SFCORR); 1171 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1172 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1173 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1174 1175 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1176 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1177 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1178 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1179 1180 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1181 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1182 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1183 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1184 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1185 iniDef->firstep = REG_READ_FIELD(ah, 1186 AR_PHY_FIND_SIG, 1187 AR_PHY_FIND_SIG_FIRSTEP); 1188 iniDef->firstepLow = REG_READ_FIELD(ah, 1189 AR_PHY_FIND_SIG_LOW, 1190 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1191 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1192 AR_PHY_TIMING5, 1193 AR_PHY_TIMING5_CYCPWR_THR1); 1194 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1195 AR_PHY_EXT_CCA, 1196 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1197 1198 /* these levels just got reset to defaults by the INI */ 1199 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1200 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1201 aniState->ofdmWeakSigDetect = true; 1202 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1203 } 1204 1205 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1206 { 1207 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1208 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1209 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1210 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1211 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1212 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1213 } 1214 1215 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1216 struct ath_hw_radar_conf *conf) 1217 { 1218 u32 radar_0 = 0, radar_1; 1219 1220 if (!conf) { 1221 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1222 return; 1223 } 1224 1225 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1226 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1227 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1228 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1229 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1230 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1231 1232 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1233 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1234 AR_PHY_RADAR_1_RELPWR_THRESH); 1235 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1236 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1237 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1238 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1239 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1240 1241 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1242 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1243 if (conf->ext_channel) 1244 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1245 else 1246 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1247 } 1248 1249 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1250 { 1251 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1252 1253 conf->fir_power = -33; 1254 conf->radar_rssi = 20; 1255 conf->pulse_height = 10; 1256 conf->pulse_rssi = 15; 1257 conf->pulse_inband = 15; 1258 conf->pulse_maxlen = 255; 1259 conf->pulse_inband_step = 12; 1260 conf->radar_inband = 8; 1261 } 1262 1263 static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array) 1264 { 1265 #define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x)) 1266 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]); 1267 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l], 1268 rate_array[rate2s])); 1269 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l], 1270 rate_array[rate5_5s])); 1271 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l], 1272 rate_array[rate11s])); 1273 #undef CCK_DELTA 1274 } 1275 1276 static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array, 1277 int offset) 1278 { 1279 int i, idx = 0; 1280 1281 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) { 1282 ah->tx_power[i] = rate_array[idx]; 1283 idx++; 1284 } 1285 } 1286 1287 static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array, 1288 int ss_offset, int ds_offset, 1289 bool is_40, int ht40_delta) 1290 { 1291 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT; 1292 1293 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) { 1294 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta; 1295 mcs_idx++; 1296 } 1297 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset], 1298 AR5008_HT_SS_RATES); 1299 } 1300 1301 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array, 1302 struct ath9k_channel *chan, int ht40_delta) 1303 { 1304 if (IS_CHAN_5GHZ(chan)) { 1305 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1306 AR5008_11NA_OFDM_SHIFT); 1307 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1308 ar5008_hw_init_txpower_ht(ah, rate_array, 1309 AR5008_11NA_HT_SS_SHIFT, 1310 AR5008_11NA_HT_DS_SHIFT, 1311 IS_CHAN_HT40(chan), 1312 ht40_delta); 1313 } 1314 } else { 1315 ar5008_hw_init_txpower_cck(ah, rate_array); 1316 ar5008_hw_init_txpower_ofdm(ah, rate_array, 1317 AR5008_11NG_OFDM_SHIFT); 1318 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { 1319 ar5008_hw_init_txpower_ht(ah, rate_array, 1320 AR5008_11NG_HT_SS_SHIFT, 1321 AR5008_11NG_HT_DS_SHIFT, 1322 IS_CHAN_HT40(chan), 1323 ht40_delta); 1324 } 1325 } 1326 } 1327 1328 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1329 { 1330 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1331 static const u32 ar5416_cca_regs[6] = { 1332 AR_PHY_CCA, 1333 AR_PHY_CH1_CCA, 1334 AR_PHY_CH2_CCA, 1335 AR_PHY_EXT_CCA, 1336 AR_PHY_CH1_EXT_CCA, 1337 AR_PHY_CH2_EXT_CCA 1338 }; 1339 int ret; 1340 1341 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1342 if (ret) 1343 return ret; 1344 1345 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1346 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1347 1348 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1349 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1350 priv_ops->init_bb = ar5008_hw_init_bb; 1351 priv_ops->process_ini = ar5008_hw_process_ini; 1352 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1353 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1354 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1355 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1356 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1357 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1358 priv_ops->do_getnf = ar5008_hw_do_getnf; 1359 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1360 1361 priv_ops->ani_control = ar5008_hw_ani_control_new; 1362 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1363 1364 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1365 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1366 else 1367 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1368 1369 ar5008_hw_set_nf_limits(ah); 1370 ar5008_hw_set_radar_conf(ah); 1371 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1372 return 0; 1373 } 1374