1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 22 /* All code below is for AR5008, AR9001, AR9002 */ 23 24 static const int firstep_table[] = 25 /* level: 0 1 2 3 4 5 6 7 8 */ 26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 27 28 static const int cycpwrThr1_table[] = 29 /* level: 0 1 2 3 4 5 6 7 8 */ 30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 31 32 /* 33 * register values to turn OFDM weak signal detection OFF 34 */ 35 static const int m1ThreshLow_off = 127; 36 static const int m2ThreshLow_off = 127; 37 static const int m1Thresh_off = 127; 38 static const int m2Thresh_off = 127; 39 static const int m2CountThr_off = 31; 40 static const int m2CountThrLow_off = 63; 41 static const int m1ThreshLowExt_off = 127; 42 static const int m2ThreshLowExt_off = 127; 43 static const int m1ThreshExt_off = 127; 44 static const int m2ThreshExt_off = 127; 45 46 47 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array, 48 int col) 49 { 50 int i; 51 52 for (i = 0; i < array->ia_rows; i++) 53 bank[i] = INI_RA(array, i, col); 54 } 55 56 57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \ 58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr)) 59 60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, 61 u32 *data, unsigned int *writecnt) 62 { 63 int r; 64 65 ENABLE_REGWRITE_BUFFER(ah); 66 67 for (r = 0; r < array->ia_rows; r++) { 68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 69 DO_DELAY(*writecnt); 70 } 71 72 REGWRITE_BUFFER_FLUSH(ah); 73 } 74 75 /** 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 77 * @rfbuf: 78 * @reg32: 79 * @numBits: 80 * @firstBit: 81 * @column: 82 * 83 * Performs analog "swizzling" of parameters into their location. 84 * Used on external AR2133/AR5133 radios. 85 */ 86 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 87 u32 numBits, u32 firstBit, 88 u32 column) 89 { 90 u32 tmp32, mask, arrayEntry, lastBit; 91 int32_t bitPosition, bitsLeft; 92 93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 94 arrayEntry = (firstBit - 1) / 8; 95 bitPosition = (firstBit - 1) % 8; 96 bitsLeft = numBits; 97 while (bitsLeft > 0) { 98 lastBit = (bitPosition + bitsLeft > 8) ? 99 8 : bitPosition + bitsLeft; 100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 101 (column * 8); 102 rfBuf[arrayEntry] &= ~mask; 103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 104 (column * 8)) & mask; 105 bitsLeft -= 8 - bitPosition; 106 tmp32 = tmp32 >> (8 - bitPosition); 107 bitPosition = 0; 108 arrayEntry++; 109 } 110 } 111 112 /* 113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 114 * rf_pwd_icsyndiv. 115 * 116 * Theoretical Rules: 117 * if 2 GHz band 118 * if forceBiasAuto 119 * if synth_freq < 2412 120 * bias = 0 121 * else if 2412 <= synth_freq <= 2422 122 * bias = 1 123 * else // synth_freq > 2422 124 * bias = 2 125 * else if forceBias > 0 126 * bias = forceBias & 7 127 * else 128 * no change, use value from ini file 129 * else 130 * no change, invalid band 131 * 132 * 1st Mod: 133 * 2422 also uses value of 2 134 * <approved> 135 * 136 * 2nd Mod: 137 * Less than 2412 uses value of 0, 2412 and above uses value of 2 138 */ 139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 140 { 141 struct ath_common *common = ath9k_hw_common(ah); 142 u32 tmp_reg; 143 int reg_writes = 0; 144 u32 new_bias = 0; 145 146 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 147 return; 148 149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 150 151 if (synth_freq < 2412) 152 new_bias = 0; 153 else if (synth_freq < 2422) 154 new_bias = 1; 155 else 156 new_bias = 2; 157 158 /* pre-reverse this field */ 159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 160 161 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 162 new_bias, synth_freq); 163 164 /* swizzle rf_pwd_icsyndiv */ 165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 166 167 /* write Bank 6 with new params */ 168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes); 169 } 170 171 /** 172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 173 * @ah: atheros hardware structure 174 * @chan: 175 * 176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 177 * the channel value. Assumes writes enabled to analog bus and bank6 register 178 * cache in ah->analogBank6Data. 179 */ 180 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 181 { 182 struct ath_common *common = ath9k_hw_common(ah); 183 u32 channelSel = 0; 184 u32 bModeSynth = 0; 185 u32 aModeRefSel = 0; 186 u32 reg32 = 0; 187 u16 freq; 188 struct chan_centers centers; 189 190 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 191 freq = centers.synth_center; 192 193 if (freq < 4800) { 194 u32 txctl; 195 196 if (((freq - 2192) % 5) == 0) { 197 channelSel = ((freq - 672) * 2 - 3040) / 10; 198 bModeSynth = 0; 199 } else if (((freq - 2224) % 5) == 0) { 200 channelSel = ((freq - 704) * 2 - 3040) / 10; 201 bModeSynth = 1; 202 } else { 203 ath_err(common, "Invalid channel %u MHz\n", freq); 204 return -EINVAL; 205 } 206 207 channelSel = (channelSel << 2) & 0xff; 208 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 209 210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 211 if (freq == 2484) { 212 213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 215 } else { 216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 218 } 219 220 } else if ((freq % 20) == 0 && freq >= 5120) { 221 channelSel = 222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 223 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 224 } else if ((freq % 10) == 0) { 225 channelSel = 226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 228 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 229 else 230 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 231 } else if ((freq % 5) == 0) { 232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 233 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 234 } else { 235 ath_err(common, "Invalid channel %u MHz\n", freq); 236 return -EINVAL; 237 } 238 239 ar5008_hw_force_bias(ah, freq); 240 241 reg32 = 242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 243 (1 << 5) | 0x1; 244 245 REG_WRITE(ah, AR_PHY(0x37), reg32); 246 247 ah->curchan = chan; 248 ah->curchan_rad_index = -1; 249 250 return 0; 251 } 252 253 /** 254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 255 * @ah: atheros hardware structure 256 * @chan: 257 * 258 * For non single-chip solutions. Converts to baseband spur frequency given the 259 * input channel frequency and compute register settings below. 260 */ 261 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 262 struct ath9k_channel *chan) 263 { 264 int bb_spur = AR_NO_SPUR; 265 int bin, cur_bin; 266 int spur_freq_sd; 267 int spur_delta_phase; 268 int denominator; 269 int upper, lower, cur_vit_mask; 270 int tmp, new; 271 int i; 272 static int pilot_mask_reg[4] = { 273 AR_PHY_TIMING7, AR_PHY_TIMING8, 274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 275 }; 276 static int chan_mask_reg[4] = { 277 AR_PHY_TIMING9, AR_PHY_TIMING10, 278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 279 }; 280 static int inc[4] = { 0, 100, 0, 0 }; 281 282 int8_t mask_m[123]; 283 int8_t mask_p[123]; 284 int8_t mask_amt; 285 int tmp_mask; 286 int cur_bb_spur; 287 bool is2GHz = IS_CHAN_2GHZ(chan); 288 289 memset(&mask_m, 0, sizeof(int8_t) * 123); 290 memset(&mask_p, 0, sizeof(int8_t) * 123); 291 292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 294 if (AR_NO_SPUR == cur_bb_spur) 295 break; 296 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 298 bb_spur = cur_bb_spur; 299 break; 300 } 301 } 302 303 if (AR_NO_SPUR == bb_spur) 304 return; 305 306 bin = bb_spur * 32; 307 308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 313 314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 315 316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 318 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 321 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 322 323 spur_delta_phase = ((bb_spur * 524288) / 100) & 324 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 325 326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 328 329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 332 REG_WRITE(ah, AR_PHY_TIMING11, new); 333 334 cur_bin = -6000; 335 upper = bin + 100; 336 lower = bin - 100; 337 338 for (i = 0; i < 4; i++) { 339 int pilot_mask = 0; 340 int chan_mask = 0; 341 int bp = 0; 342 for (bp = 0; bp < 30; bp++) { 343 if ((cur_bin > lower) && (cur_bin < upper)) { 344 pilot_mask = pilot_mask | 0x1 << bp; 345 chan_mask = chan_mask | 0x1 << bp; 346 } 347 cur_bin += 100; 348 } 349 cur_bin += inc[i]; 350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 351 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 352 } 353 354 cur_vit_mask = 6100; 355 upper = bin + 120; 356 lower = bin - 120; 357 358 for (i = 0; i < 123; i++) { 359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 360 361 /* workaround for gcc bug #37014 */ 362 volatile int tmp_v = abs(cur_vit_mask - bin); 363 364 if (tmp_v < 75) 365 mask_amt = 1; 366 else 367 mask_amt = 0; 368 if (cur_vit_mask < 0) 369 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 370 else 371 mask_p[cur_vit_mask / 100] = mask_amt; 372 } 373 cur_vit_mask -= 100; 374 } 375 376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 377 | (mask_m[48] << 26) | (mask_m[49] << 24) 378 | (mask_m[50] << 22) | (mask_m[51] << 20) 379 | (mask_m[52] << 18) | (mask_m[53] << 16) 380 | (mask_m[54] << 14) | (mask_m[55] << 12) 381 | (mask_m[56] << 10) | (mask_m[57] << 8) 382 | (mask_m[58] << 6) | (mask_m[59] << 4) 383 | (mask_m[60] << 2) | (mask_m[61] << 0); 384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 386 387 tmp_mask = (mask_m[31] << 28) 388 | (mask_m[32] << 26) | (mask_m[33] << 24) 389 | (mask_m[34] << 22) | (mask_m[35] << 20) 390 | (mask_m[36] << 18) | (mask_m[37] << 16) 391 | (mask_m[48] << 14) | (mask_m[39] << 12) 392 | (mask_m[40] << 10) | (mask_m[41] << 8) 393 | (mask_m[42] << 6) | (mask_m[43] << 4) 394 | (mask_m[44] << 2) | (mask_m[45] << 0); 395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 397 398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 399 | (mask_m[18] << 26) | (mask_m[18] << 24) 400 | (mask_m[20] << 22) | (mask_m[20] << 20) 401 | (mask_m[22] << 18) | (mask_m[22] << 16) 402 | (mask_m[24] << 14) | (mask_m[24] << 12) 403 | (mask_m[25] << 10) | (mask_m[26] << 8) 404 | (mask_m[27] << 6) | (mask_m[28] << 4) 405 | (mask_m[29] << 2) | (mask_m[30] << 0); 406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 408 409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 410 | (mask_m[2] << 26) | (mask_m[3] << 24) 411 | (mask_m[4] << 22) | (mask_m[5] << 20) 412 | (mask_m[6] << 18) | (mask_m[7] << 16) 413 | (mask_m[8] << 14) | (mask_m[9] << 12) 414 | (mask_m[10] << 10) | (mask_m[11] << 8) 415 | (mask_m[12] << 6) | (mask_m[13] << 4) 416 | (mask_m[14] << 2) | (mask_m[15] << 0); 417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 419 420 tmp_mask = (mask_p[15] << 28) 421 | (mask_p[14] << 26) | (mask_p[13] << 24) 422 | (mask_p[12] << 22) | (mask_p[11] << 20) 423 | (mask_p[10] << 18) | (mask_p[9] << 16) 424 | (mask_p[8] << 14) | (mask_p[7] << 12) 425 | (mask_p[6] << 10) | (mask_p[5] << 8) 426 | (mask_p[4] << 6) | (mask_p[3] << 4) 427 | (mask_p[2] << 2) | (mask_p[1] << 0); 428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 430 431 tmp_mask = (mask_p[30] << 28) 432 | (mask_p[29] << 26) | (mask_p[28] << 24) 433 | (mask_p[27] << 22) | (mask_p[26] << 20) 434 | (mask_p[25] << 18) | (mask_p[24] << 16) 435 | (mask_p[23] << 14) | (mask_p[22] << 12) 436 | (mask_p[21] << 10) | (mask_p[20] << 8) 437 | (mask_p[19] << 6) | (mask_p[18] << 4) 438 | (mask_p[17] << 2) | (mask_p[16] << 0); 439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 441 442 tmp_mask = (mask_p[45] << 28) 443 | (mask_p[44] << 26) | (mask_p[43] << 24) 444 | (mask_p[42] << 22) | (mask_p[41] << 20) 445 | (mask_p[40] << 18) | (mask_p[39] << 16) 446 | (mask_p[38] << 14) | (mask_p[37] << 12) 447 | (mask_p[36] << 10) | (mask_p[35] << 8) 448 | (mask_p[34] << 6) | (mask_p[33] << 4) 449 | (mask_p[32] << 2) | (mask_p[31] << 0); 450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 452 453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 454 | (mask_p[59] << 26) | (mask_p[58] << 24) 455 | (mask_p[57] << 22) | (mask_p[56] << 20) 456 | (mask_p[55] << 18) | (mask_p[54] << 16) 457 | (mask_p[53] << 14) | (mask_p[52] << 12) 458 | (mask_p[51] << 10) | (mask_p[50] << 8) 459 | (mask_p[49] << 6) | (mask_p[48] << 4) 460 | (mask_p[47] << 2) | (mask_p[46] << 0); 461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 463 } 464 465 /** 466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 467 * @ah: atheros hardware structure 468 * 469 * Only required for older devices with external AR2133/AR5133 radios. 470 */ 471 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 472 { 473 #define ATH_ALLOC_BANK(bank, size) do { \ 474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \ 475 if (!bank) { \ 476 ath_err(common, "Cannot allocate RF banks\n"); \ 477 return -ENOMEM; \ 478 } \ 479 } while (0); 480 481 struct ath_common *common = ath9k_hw_common(ah); 482 483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 484 485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows); 486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows); 487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows); 488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows); 489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows); 490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows); 491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows); 492 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows); 493 494 return 0; 495 #undef ATH_ALLOC_BANK 496 } 497 498 499 /** 500 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers 501 * @ah: atheros hardware struture 502 * For the external AR2133/AR5133 radios banks. 503 */ 504 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah) 505 { 506 #define ATH_FREE_BANK(bank) do { \ 507 kfree(bank); \ 508 bank = NULL; \ 509 } while (0); 510 511 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 512 513 ATH_FREE_BANK(ah->analogBank0Data); 514 ATH_FREE_BANK(ah->analogBank1Data); 515 ATH_FREE_BANK(ah->analogBank2Data); 516 ATH_FREE_BANK(ah->analogBank3Data); 517 ATH_FREE_BANK(ah->analogBank6Data); 518 ATH_FREE_BANK(ah->analogBank6TPCData); 519 ATH_FREE_BANK(ah->analogBank7Data); 520 ATH_FREE_BANK(ah->bank6Temp); 521 522 #undef ATH_FREE_BANK 523 } 524 525 /* * 526 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 527 * @ah: atheros hardware structure 528 * @chan: 529 * @modesIndex: 530 * 531 * Used for the external AR2133/AR5133 radios. 532 * 533 * Reads the EEPROM header info from the device structure and programs 534 * all rf registers. This routine requires access to the analog 535 * rf device. This is not required for single-chip devices. 536 */ 537 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 538 struct ath9k_channel *chan, 539 u16 modesIndex) 540 { 541 u32 eepMinorRev; 542 u32 ob5GHz = 0, db5GHz = 0; 543 u32 ob2GHz = 0, db2GHz = 0; 544 int regWrites = 0; 545 546 /* 547 * Software does not need to program bank data 548 * for single chip devices, that is AR9280 or anything 549 * after that. 550 */ 551 if (AR_SREV_9280_20_OR_LATER(ah)) 552 return true; 553 554 /* Setup rf parameters */ 555 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 556 557 /* Setup Bank 0 Write */ 558 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1); 559 560 /* Setup Bank 1 Write */ 561 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1); 562 563 /* Setup Bank 2 Write */ 564 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1); 565 566 /* Setup Bank 6 Write */ 567 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3, 568 modesIndex); 569 { 570 int i; 571 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { 572 ah->analogBank6Data[i] = 573 INI_RA(&ah->iniBank6TPC, i, modesIndex); 574 } 575 } 576 577 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 578 if (eepMinorRev >= 2) { 579 if (IS_CHAN_2GHZ(chan)) { 580 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 581 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 582 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 583 ob2GHz, 3, 197, 0); 584 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 585 db2GHz, 3, 194, 0); 586 } else { 587 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 588 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 589 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 590 ob5GHz, 3, 203, 0); 591 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 592 db5GHz, 3, 200, 0); 593 } 594 } 595 596 /* Setup Bank 7 Setup */ 597 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1); 598 599 /* Write Analog registers */ 600 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 601 regWrites); 602 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 603 regWrites); 604 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, 605 regWrites); 606 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, 607 regWrites); 608 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, 609 regWrites); 610 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, 611 regWrites); 612 613 return true; 614 } 615 616 static void ar5008_hw_init_bb(struct ath_hw *ah, 617 struct ath9k_channel *chan) 618 { 619 u32 synthDelay; 620 621 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 622 if (IS_CHAN_B(chan)) 623 synthDelay = (4 * synthDelay) / 22; 624 else 625 synthDelay /= 10; 626 627 if (IS_CHAN_HALF_RATE(chan)) 628 synthDelay *= 2; 629 else if (IS_CHAN_QUARTER_RATE(chan)) 630 synthDelay *= 4; 631 632 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 633 634 udelay(synthDelay + BASE_ACTIVATE_DELAY); 635 } 636 637 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 638 { 639 int rx_chainmask, tx_chainmask; 640 641 rx_chainmask = ah->rxchainmask; 642 tx_chainmask = ah->txchainmask; 643 644 645 switch (rx_chainmask) { 646 case 0x5: 647 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 648 AR_PHY_SWAP_ALT_CHAIN); 649 case 0x3: 650 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 651 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 652 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 653 break; 654 } 655 case 0x1: 656 case 0x2: 657 case 0x7: 658 ENABLE_REGWRITE_BUFFER(ah); 659 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 660 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 661 break; 662 default: 663 ENABLE_REGWRITE_BUFFER(ah); 664 break; 665 } 666 667 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 668 669 REGWRITE_BUFFER_FLUSH(ah); 670 671 if (tx_chainmask == 0x5) { 672 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 673 AR_PHY_SWAP_ALT_CHAIN); 674 } 675 if (AR_SREV_9100(ah)) 676 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 677 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 678 } 679 680 static void ar5008_hw_override_ini(struct ath_hw *ah, 681 struct ath9k_channel *chan) 682 { 683 u32 val; 684 685 /* 686 * Set the RX_ABORT and RX_DIS and clear if off only after 687 * RXE is set for MAC. This prevents frames with corrupted 688 * descriptor status. 689 */ 690 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 691 692 if (AR_SREV_9280_20_OR_LATER(ah)) { 693 val = REG_READ(ah, AR_PCU_MISC_MODE2); 694 695 if (!AR_SREV_9271(ah)) 696 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 697 698 if (AR_SREV_9287_11_OR_LATER(ah)) 699 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 700 701 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 702 } 703 704 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 705 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 706 707 if (AR_SREV_9280_20_OR_LATER(ah)) 708 return; 709 /* 710 * Disable BB clock gating 711 * Necessary to avoid issues on AR5416 2.0 712 */ 713 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 714 715 /* 716 * Disable RIFS search on some chips to avoid baseband 717 * hang issues. 718 */ 719 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 720 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 721 val &= ~AR_PHY_RIFS_INIT_DELAY; 722 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 723 } 724 } 725 726 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 727 struct ath9k_channel *chan) 728 { 729 u32 phymode; 730 u32 enableDacFifo = 0; 731 732 if (AR_SREV_9285_12_OR_LATER(ah)) 733 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 734 AR_PHY_FC_ENABLE_DAC_FIFO); 735 736 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 737 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 738 739 if (IS_CHAN_HT40(chan)) { 740 phymode |= AR_PHY_FC_DYN2040_EN; 741 742 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 743 (chan->chanmode == CHANNEL_G_HT40PLUS)) 744 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 745 746 } 747 REG_WRITE(ah, AR_PHY_TURBO, phymode); 748 749 ath9k_hw_set11nmac2040(ah); 750 751 ENABLE_REGWRITE_BUFFER(ah); 752 753 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 754 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 755 756 REGWRITE_BUFFER_FLUSH(ah); 757 } 758 759 760 static int ar5008_hw_process_ini(struct ath_hw *ah, 761 struct ath9k_channel *chan) 762 { 763 struct ath_common *common = ath9k_hw_common(ah); 764 int i, regWrites = 0; 765 u32 modesIndex, freqIndex; 766 767 switch (chan->chanmode) { 768 case CHANNEL_A: 769 case CHANNEL_A_HT20: 770 modesIndex = 1; 771 freqIndex = 1; 772 break; 773 case CHANNEL_A_HT40PLUS: 774 case CHANNEL_A_HT40MINUS: 775 modesIndex = 2; 776 freqIndex = 1; 777 break; 778 case CHANNEL_G: 779 case CHANNEL_G_HT20: 780 case CHANNEL_B: 781 modesIndex = 4; 782 freqIndex = 2; 783 break; 784 case CHANNEL_G_HT40PLUS: 785 case CHANNEL_G_HT40MINUS: 786 modesIndex = 3; 787 freqIndex = 2; 788 break; 789 790 default: 791 return -EINVAL; 792 } 793 794 /* 795 * Set correct baseband to analog shift setting to 796 * access analog chips. 797 */ 798 REG_WRITE(ah, AR_PHY(0), 0x00000007); 799 800 /* Write ADDAC shifts */ 801 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 802 if (ah->eep_ops->set_addac) 803 ah->eep_ops->set_addac(ah, chan); 804 805 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 806 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 807 808 ENABLE_REGWRITE_BUFFER(ah); 809 810 for (i = 0; i < ah->iniModes.ia_rows; i++) { 811 u32 reg = INI_RA(&ah->iniModes, i, 0); 812 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 813 814 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 815 val &= ~AR_AN_TOP2_PWDCLKIND; 816 817 REG_WRITE(ah, reg, val); 818 819 if (reg >= 0x7800 && reg < 0x78a0 820 && ah->config.analog_shiftreg 821 && (common->bus_ops->ath_bus_type != ATH_USB)) { 822 udelay(100); 823 } 824 825 DO_DELAY(regWrites); 826 } 827 828 REGWRITE_BUFFER_FLUSH(ah); 829 830 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 831 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 832 833 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 834 AR_SREV_9287_11_OR_LATER(ah)) 835 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 836 837 if (AR_SREV_9271_10(ah)) { 838 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 839 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 840 } 841 842 ENABLE_REGWRITE_BUFFER(ah); 843 844 /* Write common array parameters */ 845 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 846 u32 reg = INI_RA(&ah->iniCommon, i, 0); 847 u32 val = INI_RA(&ah->iniCommon, i, 1); 848 849 REG_WRITE(ah, reg, val); 850 851 if (reg >= 0x7800 && reg < 0x78a0 852 && ah->config.analog_shiftreg 853 && (common->bus_ops->ath_bus_type != ATH_USB)) { 854 udelay(100); 855 } 856 857 DO_DELAY(regWrites); 858 } 859 860 REGWRITE_BUFFER_FLUSH(ah); 861 862 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 863 864 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 865 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 866 regWrites); 867 868 ar5008_hw_override_ini(ah, chan); 869 ar5008_hw_set_channel_regs(ah, chan); 870 ar5008_hw_init_chain_masks(ah); 871 ath9k_olc_init(ah); 872 ath9k_hw_apply_txpower(ah, chan); 873 874 /* Write analog registers */ 875 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 876 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 877 return -EIO; 878 } 879 880 return 0; 881 } 882 883 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 884 { 885 u32 rfMode = 0; 886 887 if (chan == NULL) 888 return; 889 890 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 891 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 892 893 if (!AR_SREV_9280_20_OR_LATER(ah)) 894 rfMode |= (IS_CHAN_5GHZ(chan)) ? 895 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 896 897 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 898 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 899 900 REG_WRITE(ah, AR_PHY_MODE, rfMode); 901 } 902 903 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 904 { 905 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 906 } 907 908 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 909 struct ath9k_channel *chan) 910 { 911 u32 coef_scaled, ds_coef_exp, ds_coef_man; 912 u32 clockMhzScaled = 0x64000000; 913 struct chan_centers centers; 914 915 if (IS_CHAN_HALF_RATE(chan)) 916 clockMhzScaled = clockMhzScaled >> 1; 917 else if (IS_CHAN_QUARTER_RATE(chan)) 918 clockMhzScaled = clockMhzScaled >> 2; 919 920 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 921 coef_scaled = clockMhzScaled / centers.synth_center; 922 923 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 924 &ds_coef_exp); 925 926 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 927 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 928 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 929 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 930 931 coef_scaled = (9 * coef_scaled) / 10; 932 933 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 934 &ds_coef_exp); 935 936 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 937 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 938 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 939 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 940 } 941 942 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 943 { 944 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 945 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 946 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 947 } 948 949 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 950 { 951 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 952 if (IS_CHAN_B(ah->curchan)) 953 synthDelay = (4 * synthDelay) / 22; 954 else 955 synthDelay /= 10; 956 957 udelay(synthDelay + BASE_ACTIVATE_DELAY); 958 959 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 960 } 961 962 static void ar5008_restore_chainmask(struct ath_hw *ah) 963 { 964 int rx_chainmask = ah->rxchainmask; 965 966 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 967 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 968 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 969 } 970 } 971 972 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 973 struct ath9k_channel *chan) 974 { 975 u32 pll; 976 977 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 978 979 if (chan && IS_CHAN_HALF_RATE(chan)) 980 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 981 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 982 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 983 984 if (chan && IS_CHAN_5GHZ(chan)) 985 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 986 else 987 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 988 989 return pll; 990 } 991 992 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 993 struct ath9k_channel *chan) 994 { 995 u32 pll; 996 997 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 998 999 if (chan && IS_CHAN_HALF_RATE(chan)) 1000 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1001 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1002 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1003 1004 if (chan && IS_CHAN_5GHZ(chan)) 1005 pll |= SM(0xa, AR_RTC_PLL_DIV); 1006 else 1007 pll |= SM(0xb, AR_RTC_PLL_DIV); 1008 1009 return pll; 1010 } 1011 1012 static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 1013 enum ath9k_ani_cmd cmd, 1014 int param) 1015 { 1016 struct ar5416AniState *aniState = &ah->curchan->ani; 1017 struct ath_common *common = ath9k_hw_common(ah); 1018 1019 switch (cmd & ah->ani_function) { 1020 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 1021 u32 level = param; 1022 1023 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 1024 ath_dbg(common, ANI, "level out of range (%u > %zu)\n", 1025 level, ARRAY_SIZE(ah->totalSizeDesired)); 1026 return false; 1027 } 1028 1029 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1030 AR_PHY_DESIRED_SZ_TOT_DES, 1031 ah->totalSizeDesired[level]); 1032 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 1033 AR_PHY_AGC_CTL1_COARSE_LOW, 1034 ah->coarse_low[level]); 1035 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 1036 AR_PHY_AGC_CTL1_COARSE_HIGH, 1037 ah->coarse_high[level]); 1038 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1039 AR_PHY_FIND_SIG_FIRPWR, 1040 ah->firpwr[level]); 1041 1042 if (level > aniState->noiseImmunityLevel) 1043 ah->stats.ast_ani_niup++; 1044 else if (level < aniState->noiseImmunityLevel) 1045 ah->stats.ast_ani_nidown++; 1046 aniState->noiseImmunityLevel = level; 1047 break; 1048 } 1049 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1050 static const int m1ThreshLow[] = { 127, 50 }; 1051 static const int m2ThreshLow[] = { 127, 40 }; 1052 static const int m1Thresh[] = { 127, 0x4d }; 1053 static const int m2Thresh[] = { 127, 0x40 }; 1054 static const int m2CountThr[] = { 31, 16 }; 1055 static const int m2CountThrLow[] = { 63, 48 }; 1056 u32 on = param ? 1 : 0; 1057 1058 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1059 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1060 m1ThreshLow[on]); 1061 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1062 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1063 m2ThreshLow[on]); 1064 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1065 AR_PHY_SFCORR_M1_THRESH, 1066 m1Thresh[on]); 1067 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1068 AR_PHY_SFCORR_M2_THRESH, 1069 m2Thresh[on]); 1070 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1071 AR_PHY_SFCORR_M2COUNT_THR, 1072 m2CountThr[on]); 1073 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1074 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1075 m2CountThrLow[on]); 1076 1077 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1078 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 1079 m1ThreshLow[on]); 1080 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1081 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 1082 m2ThreshLow[on]); 1083 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1084 AR_PHY_SFCORR_EXT_M1_THRESH, 1085 m1Thresh[on]); 1086 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1087 AR_PHY_SFCORR_EXT_M2_THRESH, 1088 m2Thresh[on]); 1089 1090 if (on) 1091 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1092 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1093 else 1094 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1095 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1096 1097 if (!on != aniState->ofdmWeakSigDetectOff) { 1098 if (on) 1099 ah->stats.ast_ani_ofdmon++; 1100 else 1101 ah->stats.ast_ani_ofdmoff++; 1102 aniState->ofdmWeakSigDetectOff = !on; 1103 } 1104 break; 1105 } 1106 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{ 1107 static const int weakSigThrCck[] = { 8, 6 }; 1108 u32 high = param ? 1 : 0; 1109 1110 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, 1111 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, 1112 weakSigThrCck[high]); 1113 if (high != aniState->cckWeakSigThreshold) { 1114 if (high) 1115 ah->stats.ast_ani_cckhigh++; 1116 else 1117 ah->stats.ast_ani_ccklow++; 1118 aniState->cckWeakSigThreshold = high; 1119 } 1120 break; 1121 } 1122 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1123 static const int firstep[] = { 0, 4, 8 }; 1124 u32 level = param; 1125 1126 if (level >= ARRAY_SIZE(firstep)) { 1127 ath_dbg(common, ANI, "level out of range (%u > %zu)\n", 1128 level, ARRAY_SIZE(firstep)); 1129 return false; 1130 } 1131 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1132 AR_PHY_FIND_SIG_FIRSTEP, 1133 firstep[level]); 1134 if (level > aniState->firstepLevel) 1135 ah->stats.ast_ani_stepup++; 1136 else if (level < aniState->firstepLevel) 1137 ah->stats.ast_ani_stepdown++; 1138 aniState->firstepLevel = level; 1139 break; 1140 } 1141 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1142 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 1143 u32 level = param; 1144 1145 if (level >= ARRAY_SIZE(cycpwrThr1)) { 1146 ath_dbg(common, ANI, "level out of range (%u > %zu)\n", 1147 level, ARRAY_SIZE(cycpwrThr1)); 1148 return false; 1149 } 1150 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1151 AR_PHY_TIMING5_CYCPWR_THR1, 1152 cycpwrThr1[level]); 1153 if (level > aniState->spurImmunityLevel) 1154 ah->stats.ast_ani_spurup++; 1155 else if (level < aniState->spurImmunityLevel) 1156 ah->stats.ast_ani_spurdown++; 1157 aniState->spurImmunityLevel = level; 1158 break; 1159 } 1160 case ATH9K_ANI_PRESENT: 1161 break; 1162 default: 1163 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1164 return false; 1165 } 1166 1167 ath_dbg(common, ANI, "ANI parameters:\n"); 1168 ath_dbg(common, ANI, 1169 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", 1170 aniState->noiseImmunityLevel, 1171 aniState->spurImmunityLevel, 1172 !aniState->ofdmWeakSigDetectOff); 1173 ath_dbg(common, ANI, 1174 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", 1175 aniState->cckWeakSigThreshold, 1176 aniState->firstepLevel, 1177 aniState->listenTime); 1178 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 1179 aniState->ofdmPhyErrCount, 1180 aniState->cckPhyErrCount); 1181 1182 return true; 1183 } 1184 1185 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 1186 enum ath9k_ani_cmd cmd, 1187 int param) 1188 { 1189 struct ath_common *common = ath9k_hw_common(ah); 1190 struct ath9k_channel *chan = ah->curchan; 1191 struct ar5416AniState *aniState = &chan->ani; 1192 s32 value, value2; 1193 1194 switch (cmd & ah->ani_function) { 1195 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1196 /* 1197 * on == 1 means ofdm weak signal detection is ON 1198 * on == 1 is the default, for less noise immunity 1199 * 1200 * on == 0 means ofdm weak signal detection is OFF 1201 * on == 0 means more noise imm 1202 */ 1203 u32 on = param ? 1 : 0; 1204 /* 1205 * make register setting for default 1206 * (weak sig detect ON) come from INI file 1207 */ 1208 int m1ThreshLow = on ? 1209 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 1210 int m2ThreshLow = on ? 1211 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 1212 int m1Thresh = on ? 1213 aniState->iniDef.m1Thresh : m1Thresh_off; 1214 int m2Thresh = on ? 1215 aniState->iniDef.m2Thresh : m2Thresh_off; 1216 int m2CountThr = on ? 1217 aniState->iniDef.m2CountThr : m2CountThr_off; 1218 int m2CountThrLow = on ? 1219 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 1220 int m1ThreshLowExt = on ? 1221 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 1222 int m2ThreshLowExt = on ? 1223 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1224 int m1ThreshExt = on ? 1225 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1226 int m2ThreshExt = on ? 1227 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1228 1229 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1230 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1231 m1ThreshLow); 1232 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1233 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1234 m2ThreshLow); 1235 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1236 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 1237 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1238 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 1239 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1240 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 1241 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1242 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1243 m2CountThrLow); 1244 1245 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1246 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 1247 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1248 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 1249 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1250 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1251 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1252 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1253 1254 if (on) 1255 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1256 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1257 else 1258 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1259 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1260 1261 if (!on != aniState->ofdmWeakSigDetectOff) { 1262 ath_dbg(common, ANI, 1263 "** ch %d: ofdm weak signal: %s=>%s\n", 1264 chan->channel, 1265 !aniState->ofdmWeakSigDetectOff ? 1266 "on" : "off", 1267 on ? "on" : "off"); 1268 if (on) 1269 ah->stats.ast_ani_ofdmon++; 1270 else 1271 ah->stats.ast_ani_ofdmoff++; 1272 aniState->ofdmWeakSigDetectOff = !on; 1273 } 1274 break; 1275 } 1276 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1277 u32 level = param; 1278 1279 if (level >= ARRAY_SIZE(firstep_table)) { 1280 ath_dbg(common, ANI, 1281 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1282 level, ARRAY_SIZE(firstep_table)); 1283 return false; 1284 } 1285 1286 /* 1287 * make register setting relative to default 1288 * from INI file & cap value 1289 */ 1290 value = firstep_table[level] - 1291 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1292 aniState->iniDef.firstep; 1293 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1294 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1295 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1296 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1297 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1298 AR_PHY_FIND_SIG_FIRSTEP, 1299 value); 1300 /* 1301 * we need to set first step low register too 1302 * make register setting relative to default 1303 * from INI file & cap value 1304 */ 1305 value2 = firstep_table[level] - 1306 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1307 aniState->iniDef.firstepLow; 1308 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1309 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1310 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1311 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1312 1313 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1314 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); 1315 1316 if (level != aniState->firstepLevel) { 1317 ath_dbg(common, ANI, 1318 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1319 chan->channel, 1320 aniState->firstepLevel, 1321 level, 1322 ATH9K_ANI_FIRSTEP_LVL_NEW, 1323 value, 1324 aniState->iniDef.firstep); 1325 ath_dbg(common, ANI, 1326 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1327 chan->channel, 1328 aniState->firstepLevel, 1329 level, 1330 ATH9K_ANI_FIRSTEP_LVL_NEW, 1331 value2, 1332 aniState->iniDef.firstepLow); 1333 if (level > aniState->firstepLevel) 1334 ah->stats.ast_ani_stepup++; 1335 else if (level < aniState->firstepLevel) 1336 ah->stats.ast_ani_stepdown++; 1337 aniState->firstepLevel = level; 1338 } 1339 break; 1340 } 1341 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1342 u32 level = param; 1343 1344 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1345 ath_dbg(common, ANI, 1346 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1347 level, ARRAY_SIZE(cycpwrThr1_table)); 1348 return false; 1349 } 1350 /* 1351 * make register setting relative to default 1352 * from INI file & cap value 1353 */ 1354 value = cycpwrThr1_table[level] - 1355 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1356 aniState->iniDef.cycpwrThr1; 1357 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1358 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1359 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1360 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1361 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1362 AR_PHY_TIMING5_CYCPWR_THR1, 1363 value); 1364 1365 /* 1366 * set AR_PHY_EXT_CCA for extension channel 1367 * make register setting relative to default 1368 * from INI file & cap value 1369 */ 1370 value2 = cycpwrThr1_table[level] - 1371 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1372 aniState->iniDef.cycpwrThr1Ext; 1373 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1374 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1375 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1376 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1377 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1378 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); 1379 1380 if (level != aniState->spurImmunityLevel) { 1381 ath_dbg(common, ANI, 1382 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1383 chan->channel, 1384 aniState->spurImmunityLevel, 1385 level, 1386 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1387 value, 1388 aniState->iniDef.cycpwrThr1); 1389 ath_dbg(common, ANI, 1390 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1391 chan->channel, 1392 aniState->spurImmunityLevel, 1393 level, 1394 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1395 value2, 1396 aniState->iniDef.cycpwrThr1Ext); 1397 if (level > aniState->spurImmunityLevel) 1398 ah->stats.ast_ani_spurup++; 1399 else if (level < aniState->spurImmunityLevel) 1400 ah->stats.ast_ani_spurdown++; 1401 aniState->spurImmunityLevel = level; 1402 } 1403 break; 1404 } 1405 case ATH9K_ANI_MRC_CCK: 1406 /* 1407 * You should not see this as AR5008, AR9001, AR9002 1408 * does not have hardware support for MRC CCK. 1409 */ 1410 WARN_ON(1); 1411 break; 1412 case ATH9K_ANI_PRESENT: 1413 break; 1414 default: 1415 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1416 return false; 1417 } 1418 1419 ath_dbg(common, ANI, 1420 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1421 aniState->spurImmunityLevel, 1422 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1423 aniState->firstepLevel, 1424 !aniState->mrcCCKOff ? "on" : "off", 1425 aniState->listenTime, 1426 aniState->ofdmPhyErrCount, 1427 aniState->cckPhyErrCount); 1428 return true; 1429 } 1430 1431 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1432 int16_t nfarray[NUM_NF_READINGS]) 1433 { 1434 int16_t nf; 1435 1436 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1437 nfarray[0] = sign_extend32(nf, 8); 1438 1439 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1440 nfarray[1] = sign_extend32(nf, 8); 1441 1442 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1443 nfarray[2] = sign_extend32(nf, 8); 1444 1445 if (!IS_CHAN_HT40(ah->curchan)) 1446 return; 1447 1448 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1449 nfarray[3] = sign_extend32(nf, 8); 1450 1451 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1452 nfarray[4] = sign_extend32(nf, 8); 1453 1454 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1455 nfarray[5] = sign_extend32(nf, 8); 1456 } 1457 1458 /* 1459 * Initialize the ANI register values with default (ini) values. 1460 * This routine is called during a (full) hardware reset after 1461 * all the registers are initialised from the INI. 1462 */ 1463 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1464 { 1465 struct ath_common *common = ath9k_hw_common(ah); 1466 struct ath9k_channel *chan = ah->curchan; 1467 struct ar5416AniState *aniState = &chan->ani; 1468 struct ath9k_ani_default *iniDef; 1469 u32 val; 1470 1471 iniDef = &aniState->iniDef; 1472 1473 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1474 ah->hw_version.macVersion, 1475 ah->hw_version.macRev, 1476 ah->opmode, 1477 chan->channel, 1478 chan->channelFlags); 1479 1480 val = REG_READ(ah, AR_PHY_SFCORR); 1481 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1482 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1483 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1484 1485 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1486 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1487 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1488 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1489 1490 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1491 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1492 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1493 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1494 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1495 iniDef->firstep = REG_READ_FIELD(ah, 1496 AR_PHY_FIND_SIG, 1497 AR_PHY_FIND_SIG_FIRSTEP); 1498 iniDef->firstepLow = REG_READ_FIELD(ah, 1499 AR_PHY_FIND_SIG_LOW, 1500 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1501 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1502 AR_PHY_TIMING5, 1503 AR_PHY_TIMING5_CYCPWR_THR1); 1504 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1505 AR_PHY_EXT_CCA, 1506 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1507 1508 /* these levels just got reset to defaults by the INI */ 1509 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1510 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1511 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1512 aniState->mrcCCKOff = true; /* not available on pre AR9003 */ 1513 } 1514 1515 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1516 { 1517 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1518 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1519 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1520 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1521 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1522 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1523 } 1524 1525 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1526 struct ath_hw_radar_conf *conf) 1527 { 1528 u32 radar_0 = 0, radar_1 = 0; 1529 1530 if (!conf) { 1531 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1532 return; 1533 } 1534 1535 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1536 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1537 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1538 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1539 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1540 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1541 1542 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1543 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1544 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1545 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1546 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1547 1548 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1549 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1550 if (conf->ext_channel) 1551 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1552 else 1553 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1554 } 1555 1556 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1557 { 1558 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1559 1560 conf->fir_power = -33; 1561 conf->radar_rssi = 20; 1562 conf->pulse_height = 10; 1563 conf->pulse_rssi = 24; 1564 conf->pulse_inband = 15; 1565 conf->pulse_maxlen = 255; 1566 conf->pulse_inband_step = 12; 1567 conf->radar_inband = 8; 1568 } 1569 1570 void ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1571 { 1572 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1573 static const u32 ar5416_cca_regs[6] = { 1574 AR_PHY_CCA, 1575 AR_PHY_CH1_CCA, 1576 AR_PHY_CH2_CCA, 1577 AR_PHY_EXT_CCA, 1578 AR_PHY_CH1_EXT_CCA, 1579 AR_PHY_CH2_EXT_CCA 1580 }; 1581 1582 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1583 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1584 1585 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks; 1586 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks; 1587 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1588 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1589 priv_ops->init_bb = ar5008_hw_init_bb; 1590 priv_ops->process_ini = ar5008_hw_process_ini; 1591 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1592 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1593 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1594 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1595 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1596 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1597 priv_ops->do_getnf = ar5008_hw_do_getnf; 1598 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1599 1600 if (modparam_force_new_ani) { 1601 priv_ops->ani_control = ar5008_hw_ani_control_new; 1602 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1603 } else 1604 priv_ops->ani_control = ar5008_hw_ani_control_old; 1605 1606 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1607 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1608 else 1609 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1610 1611 ar5008_hw_set_nf_limits(ah); 1612 ar5008_hw_set_radar_conf(ah); 1613 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1614 } 1615