1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include "hw.h" 20 #include "hw-ops.h" 21 22 struct ani_ofdm_level_entry { 23 int spur_immunity_level; 24 int fir_step_level; 25 int ofdm_weak_signal_on; 26 }; 27 28 /* values here are relative to the INI */ 29 30 /* 31 * Legend: 32 * 33 * SI: Spur immunity 34 * FS: FIR Step 35 * WS: OFDM / CCK Weak Signal detection 36 * MRC-CCK: Maximal Ratio Combining for CCK 37 */ 38 39 static const struct ani_ofdm_level_entry ofdm_level_table[] = { 40 /* SI FS WS */ 41 { 0, 0, 1 }, /* lvl 0 */ 42 { 1, 1, 1 }, /* lvl 1 */ 43 { 2, 2, 1 }, /* lvl 2 */ 44 { 3, 2, 1 }, /* lvl 3 (default) */ 45 { 4, 3, 1 }, /* lvl 4 */ 46 { 5, 4, 1 }, /* lvl 5 */ 47 { 6, 5, 1 }, /* lvl 6 */ 48 { 7, 6, 1 }, /* lvl 7 */ 49 { 7, 7, 1 }, /* lvl 8 */ 50 { 7, 8, 0 } /* lvl 9 */ 51 }; 52 #define ATH9K_ANI_OFDM_NUM_LEVEL \ 53 ARRAY_SIZE(ofdm_level_table) 54 #define ATH9K_ANI_OFDM_MAX_LEVEL \ 55 (ATH9K_ANI_OFDM_NUM_LEVEL-1) 56 #define ATH9K_ANI_OFDM_DEF_LEVEL \ 57 3 /* default level - matches the INI settings */ 58 59 /* 60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm. 61 * With OFDM for single stream you just add up all antenna inputs, you're 62 * only interested in what you get after FFT. Signal aligment is also not 63 * required for OFDM because any phase difference adds up in the frequency 64 * domain. 65 * 66 * MRC requires extra work for use with CCK. You need to align the antenna 67 * signals from the different antenna before you can add the signals together. 68 * You need aligment of signals as CCK is in time domain, so addition can cancel 69 * your signal completely if phase is 180 degrees (think of adding sine waves). 70 * You also need to remove noise before the addition and this is where ANI 71 * MRC CCK comes into play. One of the antenna inputs may be stronger but 72 * lower SNR, so just adding after alignment can be dangerous. 73 * 74 * Regardless of alignment in time, the antenna signals add constructively after 75 * FFT and improve your reception. For more information: 76 * 77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining 78 */ 79 80 struct ani_cck_level_entry { 81 int fir_step_level; 82 int mrc_cck_on; 83 }; 84 85 static const struct ani_cck_level_entry cck_level_table[] = { 86 /* FS MRC-CCK */ 87 { 0, 1 }, /* lvl 0 */ 88 { 1, 1 }, /* lvl 1 */ 89 { 2, 1 }, /* lvl 2 (default) */ 90 { 3, 1 }, /* lvl 3 */ 91 { 4, 0 }, /* lvl 4 */ 92 { 5, 0 }, /* lvl 5 */ 93 { 6, 0 }, /* lvl 6 */ 94 { 7, 0 }, /* lvl 7 (only for high rssi) */ 95 { 8, 0 } /* lvl 8 (only for high rssi) */ 96 }; 97 98 #define ATH9K_ANI_CCK_NUM_LEVEL \ 99 ARRAY_SIZE(cck_level_table) 100 #define ATH9K_ANI_CCK_MAX_LEVEL \ 101 (ATH9K_ANI_CCK_NUM_LEVEL-1) 102 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \ 103 (ATH9K_ANI_CCK_NUM_LEVEL-3) 104 #define ATH9K_ANI_CCK_DEF_LEVEL \ 105 2 /* default level - matches the INI settings */ 106 107 static void ath9k_hw_update_mibstats(struct ath_hw *ah, 108 struct ath9k_mib_stats *stats) 109 { 110 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); 111 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); 112 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); 113 stats->rts_good += REG_READ(ah, AR_RTS_OK); 114 stats->beacons += REG_READ(ah, AR_BEACON_CNT); 115 } 116 117 static void ath9k_ani_restart(struct ath_hw *ah) 118 { 119 struct ar5416AniState *aniState; 120 121 if (!ah->curchan) 122 return; 123 124 aniState = &ah->ani; 125 aniState->listenTime = 0; 126 127 ENABLE_REGWRITE_BUFFER(ah); 128 129 REG_WRITE(ah, AR_PHY_ERR_1, 0); 130 REG_WRITE(ah, AR_PHY_ERR_2, 0); 131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 133 134 REGWRITE_BUFFER_FLUSH(ah); 135 136 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 137 138 aniState->ofdmPhyErrCount = 0; 139 aniState->cckPhyErrCount = 0; 140 } 141 142 /* Adjust the OFDM Noise Immunity Level */ 143 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel, 144 bool scan) 145 { 146 struct ar5416AniState *aniState = &ah->ani; 147 struct ath_common *common = ath9k_hw_common(ah); 148 const struct ani_ofdm_level_entry *entry_ofdm; 149 const struct ani_cck_level_entry *entry_cck; 150 bool weak_sig; 151 152 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 153 aniState->ofdmNoiseImmunityLevel, 154 immunityLevel, BEACON_RSSI(ah), 155 ATH9K_ANI_RSSI_THR_LOW, 156 ATH9K_ANI_RSSI_THR_HIGH); 157 158 if (!scan) 159 aniState->ofdmNoiseImmunityLevel = immunityLevel; 160 161 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 162 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 163 164 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level) 165 ath9k_hw_ani_control(ah, 166 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 167 entry_ofdm->spur_immunity_level); 168 169 if (aniState->firstepLevel != entry_ofdm->fir_step_level && 170 entry_ofdm->fir_step_level >= entry_cck->fir_step_level) 171 ath9k_hw_ani_control(ah, 172 ATH9K_ANI_FIRSTEP_LEVEL, 173 entry_ofdm->fir_step_level); 174 175 weak_sig = entry_ofdm->ofdm_weak_signal_on; 176 if (ah->opmode == NL80211_IFTYPE_STATION && 177 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH) 178 weak_sig = true; 179 /* 180 * Newer chipsets are better at dealing with high PHY error counts - 181 * keep weak signal detection enabled when no RSSI threshold is 182 * available to determine if it is needed (mode != STA) 183 */ 184 else if (AR_SREV_9300_20_OR_LATER(ah) && 185 ah->opmode != NL80211_IFTYPE_STATION) 186 weak_sig = true; 187 188 /* Older chipsets are more sensitive to high PHY error counts */ 189 else if (!AR_SREV_9300_20_OR_LATER(ah) && 190 aniState->ofdmNoiseImmunityLevel >= 8) 191 weak_sig = false; 192 193 if (aniState->ofdmWeakSigDetect != weak_sig) 194 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 195 weak_sig); 196 197 if (!AR_SREV_9300_20_OR_LATER(ah)) 198 return; 199 200 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) { 201 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; 202 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI; 203 } else { 204 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI; 205 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; 206 } 207 } 208 209 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) 210 { 211 struct ar5416AniState *aniState; 212 213 if (!ah->curchan) 214 return; 215 216 aniState = &ah->ani; 217 218 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) 219 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false); 220 } 221 222 /* 223 * Set the ANI settings to match an CCK level. 224 */ 225 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, 226 bool scan) 227 { 228 struct ar5416AniState *aniState = &ah->ani; 229 struct ath_common *common = ath9k_hw_common(ah); 230 const struct ani_ofdm_level_entry *entry_ofdm; 231 const struct ani_cck_level_entry *entry_cck; 232 233 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 234 aniState->cckNoiseImmunityLevel, immunityLevel, 235 BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW, 236 ATH9K_ANI_RSSI_THR_HIGH); 237 238 if (ah->opmode == NL80211_IFTYPE_STATION && 239 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW && 240 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) 241 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; 242 243 if (!scan) 244 aniState->cckNoiseImmunityLevel = immunityLevel; 245 246 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 247 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 248 249 if (aniState->firstepLevel != entry_cck->fir_step_level && 250 entry_cck->fir_step_level >= entry_ofdm->fir_step_level) 251 ath9k_hw_ani_control(ah, 252 ATH9K_ANI_FIRSTEP_LEVEL, 253 entry_cck->fir_step_level); 254 255 /* Skip MRC CCK for pre AR9003 families */ 256 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) 257 return; 258 259 if (aniState->mrcCCK != entry_cck->mrc_cck_on) 260 ath9k_hw_ani_control(ah, 261 ATH9K_ANI_MRC_CCK, 262 entry_cck->mrc_cck_on); 263 } 264 265 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) 266 { 267 struct ar5416AniState *aniState; 268 269 if (!ah->curchan) 270 return; 271 272 aniState = &ah->ani; 273 274 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) 275 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1, 276 false); 277 } 278 279 /* 280 * only lower either OFDM or CCK errors per turn 281 * we lower the other one next time 282 */ 283 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) 284 { 285 struct ar5416AniState *aniState; 286 287 aniState = &ah->ani; 288 289 /* lower OFDM noise immunity */ 290 if (aniState->ofdmNoiseImmunityLevel > 0 && 291 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { 292 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1, 293 false); 294 return; 295 } 296 297 /* lower CCK noise immunity */ 298 if (aniState->cckNoiseImmunityLevel > 0) 299 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1, 300 false); 301 } 302 303 /* 304 * Restore the ANI parameters in the HAL and reset the statistics. 305 * This routine should be called for every hardware reset and for 306 * every channel change. 307 */ 308 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) 309 { 310 struct ar5416AniState *aniState = &ah->ani; 311 struct ath9k_channel *chan = ah->curchan; 312 struct ath_common *common = ath9k_hw_common(ah); 313 int ofdm_nil, cck_nil; 314 315 if (!ah->curchan) 316 return; 317 318 BUG_ON(aniState == NULL); 319 ah->stats.ast_ani_reset++; 320 321 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL, 322 aniState->ofdmNoiseImmunityLevel); 323 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL, 324 aniState->cckNoiseImmunityLevel); 325 326 if (is_scanning || 327 (ah->opmode != NL80211_IFTYPE_STATION && 328 ah->opmode != NL80211_IFTYPE_ADHOC)) { 329 /* 330 * If we're scanning or in AP mode, the defaults (ini) 331 * should be in place. For an AP we assume the historical 332 * levels for this channel are probably outdated so start 333 * from defaults instead. 334 */ 335 if (aniState->ofdmNoiseImmunityLevel != 336 ATH9K_ANI_OFDM_DEF_LEVEL || 337 aniState->cckNoiseImmunityLevel != 338 ATH9K_ANI_CCK_DEF_LEVEL) { 339 ath_dbg(common, ANI, 340 "Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", 341 ah->opmode, 342 chan->channel, 343 is_scanning, 344 aniState->ofdmNoiseImmunityLevel, 345 aniState->cckNoiseImmunityLevel); 346 347 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL; 348 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL; 349 } 350 } else { 351 /* 352 * restore historical levels for this channel 353 */ 354 ath_dbg(common, ANI, 355 "Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", 356 ah->opmode, 357 chan->channel, 358 is_scanning, 359 aniState->ofdmNoiseImmunityLevel, 360 aniState->cckNoiseImmunityLevel); 361 } 362 ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning); 363 ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning); 364 365 ath9k_ani_restart(ah); 366 } 367 368 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) 369 { 370 struct ath_common *common = ath9k_hw_common(ah); 371 struct ar5416AniState *aniState = &ah->ani; 372 u32 phyCnt1, phyCnt2; 373 int32_t listenTime; 374 375 ath_hw_cycle_counters_update(common); 376 listenTime = ath_hw_get_listen_time(common); 377 378 if (listenTime <= 0) { 379 ah->stats.ast_ani_lneg_or_lzero++; 380 ath9k_ani_restart(ah); 381 return false; 382 } 383 384 aniState->listenTime += listenTime; 385 386 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 387 388 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 389 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 390 391 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount; 392 aniState->ofdmPhyErrCount = phyCnt1; 393 394 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount; 395 aniState->cckPhyErrCount = phyCnt2; 396 397 return true; 398 } 399 400 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) 401 { 402 struct ar5416AniState *aniState; 403 struct ath_common *common = ath9k_hw_common(ah); 404 u32 ofdmPhyErrRate, cckPhyErrRate; 405 406 if (!ah->curchan) 407 return; 408 409 aniState = &ah->ani; 410 if (!ath9k_hw_ani_read_counters(ah)) 411 return; 412 413 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 / 414 aniState->listenTime; 415 cckPhyErrRate = aniState->cckPhyErrCount * 1000 / 416 aniState->listenTime; 417 418 ath_dbg(common, ANI, 419 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", 420 aniState->listenTime, 421 aniState->ofdmNoiseImmunityLevel, 422 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, 423 cckPhyErrRate, aniState->ofdmsTurn); 424 425 if (aniState->listenTime > ah->aniperiod) { 426 if (cckPhyErrRate < ah->config.cck_trig_low && 427 ofdmPhyErrRate < ah->config.ofdm_trig_low) { 428 ath9k_hw_ani_lower_immunity(ah); 429 aniState->ofdmsTurn = !aniState->ofdmsTurn; 430 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) { 431 ath9k_hw_ani_ofdm_err_trigger(ah); 432 aniState->ofdmsTurn = false; 433 } else if (cckPhyErrRate > ah->config.cck_trig_high) { 434 ath9k_hw_ani_cck_err_trigger(ah); 435 aniState->ofdmsTurn = true; 436 } 437 ath9k_ani_restart(ah); 438 } 439 } 440 EXPORT_SYMBOL(ath9k_hw_ani_monitor); 441 442 void ath9k_enable_mib_counters(struct ath_hw *ah) 443 { 444 struct ath_common *common = ath9k_hw_common(ah); 445 446 ath_dbg(common, ANI, "Enable MIB counters\n"); 447 448 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 449 450 ENABLE_REGWRITE_BUFFER(ah); 451 452 REG_WRITE(ah, AR_FILT_OFDM, 0); 453 REG_WRITE(ah, AR_FILT_CCK, 0); 454 REG_WRITE(ah, AR_MIBC, 455 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) 456 & 0x0f); 457 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 458 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 459 460 REGWRITE_BUFFER_FLUSH(ah); 461 } 462 463 /* Freeze the MIB counters, get the stats and then clear them */ 464 void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 465 { 466 struct ath_common *common = ath9k_hw_common(ah); 467 468 ath_dbg(common, ANI, "Disable MIB counters\n"); 469 470 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 471 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 472 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 473 REG_WRITE(ah, AR_FILT_OFDM, 0); 474 REG_WRITE(ah, AR_FILT_CCK, 0); 475 } 476 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); 477 478 void ath9k_hw_ani_init(struct ath_hw *ah) 479 { 480 struct ath_common *common = ath9k_hw_common(ah); 481 struct ar5416AniState *ani = &ah->ani; 482 483 ath_dbg(common, ANI, "Initialize ANI\n"); 484 485 if (AR_SREV_9300_20_OR_LATER(ah)) { 486 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; 487 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; 488 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH; 489 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW; 490 } else { 491 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD; 492 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD; 493 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD; 494 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD; 495 } 496 497 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 498 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 499 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false; 500 ani->ofdmsTurn = true; 501 ani->ofdmWeakSigDetect = true; 502 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 503 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 504 505 /* 506 * since we expect some ongoing maintenance on the tables, let's sanity 507 * check here default level should not modify INI setting. 508 */ 509 ah->aniperiod = ATH9K_ANI_PERIOD; 510 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL; 511 512 ath9k_ani_restart(ah); 513 ath9k_enable_mib_counters(ah); 514 } 515