1 /* 2 * Copyright (c) 2004-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef TARGET_H 18 #define TARGET_H 19 20 #define AR6003_BOARD_DATA_SZ 1024 21 #define AR6003_BOARD_EXT_DATA_SZ 768 22 23 #define RESET_CONTROL_ADDRESS 0x00000000 24 #define RESET_CONTROL_COLD_RST 0x00000100 25 #define RESET_CONTROL_MBOX_RST 0x00000004 26 27 #define CPU_CLOCK_STANDARD_S 0 28 #define CPU_CLOCK_STANDARD 0x00000003 29 #define CPU_CLOCK_ADDRESS 0x00000020 30 31 #define CLOCK_CONTROL_ADDRESS 0x00000028 32 #define CLOCK_CONTROL_LF_CLK32_S 2 33 #define CLOCK_CONTROL_LF_CLK32 0x00000004 34 35 #define SYSTEM_SLEEP_ADDRESS 0x000000c4 36 #define SYSTEM_SLEEP_DISABLE_S 0 37 #define SYSTEM_SLEEP_DISABLE 0x00000001 38 39 #define LPO_CAL_ADDRESS 0x000000e0 40 #define LPO_CAL_ENABLE_S 20 41 #define LPO_CAL_ENABLE 0x00100000 42 43 #define GPIO_PIN10_ADDRESS 0x00000050 44 #define GPIO_PIN11_ADDRESS 0x00000054 45 #define GPIO_PIN12_ADDRESS 0x00000058 46 #define GPIO_PIN13_ADDRESS 0x0000005c 47 48 #define HOST_INT_STATUS_ADDRESS 0x00000400 49 #define HOST_INT_STATUS_ERROR_S 7 50 #define HOST_INT_STATUS_ERROR 0x00000080 51 52 #define HOST_INT_STATUS_CPU_S 6 53 #define HOST_INT_STATUS_CPU 0x00000040 54 55 #define HOST_INT_STATUS_COUNTER_S 4 56 #define HOST_INT_STATUS_COUNTER 0x00000010 57 58 #define CPU_INT_STATUS_ADDRESS 0x00000401 59 60 #define ERROR_INT_STATUS_ADDRESS 0x00000402 61 #define ERROR_INT_STATUS_WAKEUP_S 2 62 #define ERROR_INT_STATUS_WAKEUP 0x00000004 63 64 #define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 65 #define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 66 67 #define ERROR_INT_STATUS_TX_OVERFLOW_S 0 68 #define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 69 70 #define COUNTER_INT_STATUS_ADDRESS 0x00000403 71 #define COUNTER_INT_STATUS_COUNTER_S 0 72 #define COUNTER_INT_STATUS_COUNTER 0x000000ff 73 74 #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 75 76 #define INT_STATUS_ENABLE_ADDRESS 0x00000418 77 #define INT_STATUS_ENABLE_ERROR_S 7 78 #define INT_STATUS_ENABLE_ERROR 0x00000080 79 80 #define INT_STATUS_ENABLE_CPU_S 6 81 #define INT_STATUS_ENABLE_CPU 0x00000040 82 83 #define INT_STATUS_ENABLE_INT_S 5 84 #define INT_STATUS_ENABLE_INT 0x00000020 85 #define INT_STATUS_ENABLE_COUNTER_S 4 86 #define INT_STATUS_ENABLE_COUNTER 0x00000010 87 88 #define INT_STATUS_ENABLE_MBOX_DATA_S 0 89 #define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f 90 91 #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 92 #define CPU_INT_STATUS_ENABLE_BIT_S 0 93 #define CPU_INT_STATUS_ENABLE_BIT 0x000000ff 94 95 #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a 96 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 97 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 98 99 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 100 #define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 101 102 #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b 103 #define COUNTER_INT_STATUS_ENABLE_BIT_S 0 104 #define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff 105 106 #define COUNT_ADDRESS 0x00000420 107 108 #define COUNT_DEC_ADDRESS 0x00000440 109 110 #define WINDOW_DATA_ADDRESS 0x00000474 111 #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 112 #define WINDOW_READ_ADDR_ADDRESS 0x0000047c 113 #define CPU_DBG_SEL_ADDRESS 0x00000483 114 #define CPU_DBG_ADDRESS 0x00000484 115 116 #define LOCAL_SCRATCH_ADDRESS 0x000000c0 117 #define ATH6KL_OPTION_SLEEP_DISABLE 0x08 118 119 #define RTC_BASE_ADDRESS 0x00004000 120 #define GPIO_BASE_ADDRESS 0x00014000 121 #define MBOX_BASE_ADDRESS 0x00018000 122 #define ANALOG_INTF_BASE_ADDRESS 0x0001c000 123 124 /* real name of the register is unknown */ 125 #define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) 126 127 #define SM(f, v) (((v) << f##_S) & f) 128 #define MS(f, v) (((v) & f) >> f##_S) 129 130 /* 131 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 132 * host_interest structure. 133 * 134 * Host Interest is shared between Host and Target in order to coordinate 135 * between the two, and is intended to remain constant (with additions only 136 * at the end). 137 */ 138 #define ATH6KL_HI_START_ADDR 0x00540600 139 140 /* 141 * These are items that the Host may need to access 142 * via BMI or via the Diagnostic Window. The position 143 * of items in this structure must remain constant. 144 * across firmware revisions! 145 * 146 * Types for each item must be fixed size across target and host platforms. 147 * The structure is used only to calculate offset for each register with 148 * HI_ITEM() macro, no values are stored to it. 149 * 150 * More items may be added at the end. 151 */ 152 struct host_interest { 153 /* 154 * Pointer to application-defined area, if any. 155 * Set by Target application during startup. 156 */ 157 u32 hi_app_host_interest; /* 0x00 */ 158 159 /* Pointer to register dump area, valid after Target crash. */ 160 u32 hi_failure_state; /* 0x04 */ 161 162 /* Pointer to debug logging header */ 163 u32 hi_dbglog_hdr; /* 0x08 */ 164 165 u32 hi_unused1; /* 0x0c */ 166 167 /* 168 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. 169 * Can be used by application rather than by OS. 170 */ 171 u32 hi_option_flag; /* 0x10 */ 172 173 /* 174 * Boolean that determines whether or not to 175 * display messages on the serial port. 176 */ 177 u32 hi_serial_enable; /* 0x14 */ 178 179 /* Start address of DataSet index, if any */ 180 u32 hi_dset_list_head; /* 0x18 */ 181 182 /* Override Target application start address */ 183 u32 hi_app_start; /* 0x1c */ 184 185 /* Clock and voltage tuning */ 186 u32 hi_skip_clock_init; /* 0x20 */ 187 u32 hi_core_clock_setting; /* 0x24 */ 188 u32 hi_cpu_clock_setting; /* 0x28 */ 189 u32 hi_system_sleep_setting; /* 0x2c */ 190 u32 hi_xtal_control_setting; /* 0x30 */ 191 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 192 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 193 u32 hi_ref_voltage_trim_setting; /* 0x3c */ 194 u32 hi_clock_info; /* 0x40 */ 195 196 /* 197 * Flash configuration overrides, used only 198 * when firmware is not executing from flash. 199 * (When using flash, modify the global variables 200 * with equivalent names.) 201 */ 202 u32 hi_bank0_addr_value; /* 0x44 */ 203 u32 hi_bank0_read_value; /* 0x48 */ 204 u32 hi_bank0_write_value; /* 0x4c */ 205 u32 hi_bank0_config_value; /* 0x50 */ 206 207 /* Pointer to Board Data */ 208 u32 hi_board_data; /* 0x54 */ 209 u32 hi_board_data_initialized; /* 0x58 */ 210 211 u32 hi_dset_ram_index_tbl; /* 0x5c */ 212 213 u32 hi_desired_baud_rate; /* 0x60 */ 214 u32 hi_dbglog_config; /* 0x64 */ 215 u32 hi_end_ram_reserve_sz; /* 0x68 */ 216 u32 hi_mbox_io_block_sz; /* 0x6c */ 217 218 u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 219 u32 hi_mbox_isr_yield_limit; /* 0x74 */ 220 221 u32 hi_refclk_hz; /* 0x78 */ 222 u32 hi_ext_clk_detected; /* 0x7c */ 223 u32 hi_dbg_uart_txpin; /* 0x80 */ 224 u32 hi_dbg_uart_rxpin; /* 0x84 */ 225 u32 hi_hci_uart_baud; /* 0x88 */ 226 u32 hi_hci_uart_pin_assignments; /* 0x8C */ 227 /* 228 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts 229 * pin 230 */ 231 u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 232 u32 hi_hci_uart_baud_step_val; /* 0x94 */ 233 234 u32 hi_allocram_start; /* 0x98 */ 235 u32 hi_allocram_sz; /* 0x9c */ 236 u32 hi_hci_bridge_flags; /* 0xa0 */ 237 u32 hi_hci_uart_support_pins; /* 0xa4 */ 238 /* 239 * NOTE: byte [0] = RESET pin (bit 7 is polarity), 240 * bytes[1]..bytes[3] are for future use 241 */ 242 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 243 /* 244 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 245 * [31:16]: wakeup timeout in ms 246 */ 247 248 /* Pointer to extended board data */ 249 u32 hi_board_ext_data; /* 0xac */ 250 u32 hi_board_ext_data_config; /* 0xb0 */ 251 252 /* 253 * Bit [0] : valid 254 * Bit[31:16: size 255 */ 256 /* 257 * hi_reset_flag is used to do some stuff when target reset. 258 * such as restore app_start after warm reset or 259 * preserve host Interest area, or preserve ROM data, literals etc. 260 */ 261 u32 hi_reset_flag; /* 0xb4 */ 262 /* indicate hi_reset_flag is valid */ 263 u32 hi_reset_flag_valid; /* 0xb8 */ 264 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 265 /* 266 * 0xbc - [31:0]: idle timeout in ms 267 */ 268 /* ACS flags */ 269 u32 hi_acs_flags; /* 0xc0 */ 270 u32 hi_console_flags; /* 0xc4 */ 271 u32 hi_nvram_state; /* 0xc8 */ 272 u32 hi_option_flag2; /* 0xcc */ 273 274 /* If non-zero, override values sent to Host in WMI_READY event. */ 275 u32 hi_sw_version_override; /* 0xd0 */ 276 u32 hi_abi_version_override; /* 0xd4 */ 277 278 /* 279 * Percentage of high priority RX traffic to total expected RX traffic - 280 * applicable only to ar6004 281 */ 282 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 283 284 /* test applications flags */ 285 u32 hi_test_apps_related ; /* 0xdc */ 286 /* location of test script */ 287 u32 hi_ota_testscript; /* 0xe0 */ 288 /* location of CAL data */ 289 u32 hi_cal_data; /* 0xe4 */ 290 /* Number of packet log buffers */ 291 u32 hi_pktlog_num_buffers; /* 0xe8 */ 292 293 } __packed; 294 295 #define HI_ITEM(item) offsetof(struct host_interest, item) 296 297 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 298 299 #define HI_OPTION_FW_MODE_IBSS 0x0 300 #define HI_OPTION_FW_MODE_BSS_STA 0x1 301 #define HI_OPTION_FW_MODE_AP 0x2 302 303 #define HI_OPTION_NUM_DEV_SHIFT 0x9 304 305 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 306 307 /* Fw Mode/SubMode Mask 308 |------------------------------------------------------------------------------| 309 | SUB | SUB | SUB | SUB | | | | 310 | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| 311 | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 312 |------------------------------------------------------------------------------| 313 */ 314 #define HI_OPTION_FW_MODE_SHIFT 0xC 315 316 /* Convert a Target virtual address into a Target physical address */ 317 #define TARG_VTOP(vaddr) (vaddr & 0x001fffff) 318 319 #define AR6003_REV2_APP_START_OVERRIDE 0x944C00 320 #define AR6003_REV2_APP_LOAD_ADDRESS 0x543180 321 #define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500 322 #define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884 323 #define AR6003_REV2_RAM_RESERVE_SIZE 6912 324 325 #define AR6003_REV3_APP_START_OVERRIDE 0x945d00 326 #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 327 #define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330 328 #define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74 329 #define AR6003_REV3_RAM_RESERVE_SIZE 512 330 331 #endif 332