1 /* 2 * Copyright (c) 2004-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/mmc/card.h> 20 #include <linux/mmc/mmc.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/mmc/sdio_ids.h> 24 #include <linux/mmc/sdio.h> 25 #include <linux/mmc/sd.h> 26 #include "hif.h" 27 #include "hif-ops.h" 28 #include "target.h" 29 #include "debug.h" 30 #include "cfg80211.h" 31 #include "trace.h" 32 33 struct ath6kl_sdio { 34 struct sdio_func *func; 35 36 /* protects access to bus_req_freeq */ 37 spinlock_t lock; 38 39 /* free list */ 40 struct list_head bus_req_freeq; 41 42 /* available bus requests */ 43 struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 44 45 struct ath6kl *ar; 46 47 u8 *dma_buffer; 48 49 /* protects access to dma_buffer */ 50 struct mutex dma_buffer_mutex; 51 52 /* scatter request list head */ 53 struct list_head scat_req; 54 55 atomic_t irq_handling; 56 wait_queue_head_t irq_wq; 57 58 /* protects access to scat_req */ 59 spinlock_t scat_lock; 60 61 bool scatter_enabled; 62 63 bool is_disabled; 64 const struct sdio_device_id *id; 65 struct work_struct wr_async_work; 66 struct list_head wr_asyncq; 67 68 /* protects access to wr_asyncq */ 69 spinlock_t wr_async_lock; 70 }; 71 72 #define CMD53_ARG_READ 0 73 #define CMD53_ARG_WRITE 1 74 #define CMD53_ARG_BLOCK_BASIS 1 75 #define CMD53_ARG_FIXED_ADDRESS 0 76 #define CMD53_ARG_INCR_ADDRESS 1 77 78 static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 79 { 80 return ar->hif_priv; 81 } 82 83 /* 84 * Macro to check if DMA buffer is WORD-aligned and DMA-able. 85 * Most host controllers assume the buffer is DMA'able and will 86 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 87 * check fails on stack memory. 88 */ 89 static inline bool buf_needs_bounce(u8 *buf) 90 { 91 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 92 } 93 94 static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 95 { 96 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 97 98 /* EP1 has an extended range */ 99 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 100 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 101 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 102 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 103 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 104 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 105 } 106 107 static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 108 u8 mode, u8 opcode, u32 addr, 109 u16 blksz) 110 { 111 *arg = (((rw & 1) << 31) | 112 ((func & 0x7) << 28) | 113 ((mode & 1) << 27) | 114 ((opcode & 1) << 26) | 115 ((addr & 0x1FFFF) << 9) | 116 (blksz & 0x1FF)); 117 } 118 119 static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 120 unsigned int address, 121 unsigned char val) 122 { 123 const u8 func = 0; 124 125 *arg = ((write & 1) << 31) | 126 ((func & 0x7) << 28) | 127 ((raw & 1) << 27) | 128 (1 << 26) | 129 ((address & 0x1FFFF) << 9) | 130 (1 << 8) | 131 (val & 0xFF); 132 } 133 134 static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 135 unsigned int address, 136 unsigned char byte) 137 { 138 struct mmc_command io_cmd; 139 140 memset(&io_cmd, 0, sizeof(io_cmd)); 141 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 142 io_cmd.opcode = SD_IO_RW_DIRECT; 143 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 144 145 return mmc_wait_for_cmd(card->host, &io_cmd, 0); 146 } 147 148 static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 149 u8 *buf, u32 len) 150 { 151 int ret = 0; 152 153 sdio_claim_host(func); 154 155 if (request & HIF_WRITE) { 156 /* FIXME: looks like ugly workaround for something */ 157 if (addr >= HIF_MBOX_BASE_ADDR && 158 addr <= HIF_MBOX_END_ADDR) 159 addr += (HIF_MBOX_WIDTH - len); 160 161 /* FIXME: this also looks like ugly workaround */ 162 if (addr == HIF_MBOX0_EXT_BASE_ADDR) 163 addr += HIF_MBOX0_EXT_WIDTH - len; 164 165 if (request & HIF_FIXED_ADDRESS) 166 ret = sdio_writesb(func, addr, buf, len); 167 else 168 ret = sdio_memcpy_toio(func, addr, buf, len); 169 } else { 170 if (request & HIF_FIXED_ADDRESS) 171 ret = sdio_readsb(func, buf, addr, len); 172 else 173 ret = sdio_memcpy_fromio(func, buf, addr, len); 174 } 175 176 sdio_release_host(func); 177 178 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 179 request & HIF_WRITE ? "wr" : "rd", addr, 180 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 181 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 182 183 trace_ath6kl_sdio(addr, request, buf, len); 184 185 return ret; 186 } 187 188 static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 189 { 190 struct bus_request *bus_req; 191 192 spin_lock_bh(&ar_sdio->lock); 193 194 if (list_empty(&ar_sdio->bus_req_freeq)) { 195 spin_unlock_bh(&ar_sdio->lock); 196 return NULL; 197 } 198 199 bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 200 struct bus_request, list); 201 list_del(&bus_req->list); 202 203 spin_unlock_bh(&ar_sdio->lock); 204 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 205 __func__, bus_req); 206 207 return bus_req; 208 } 209 210 static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 211 struct bus_request *bus_req) 212 { 213 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 214 __func__, bus_req); 215 216 spin_lock_bh(&ar_sdio->lock); 217 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 218 spin_unlock_bh(&ar_sdio->lock); 219 } 220 221 static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 222 struct mmc_data *data) 223 { 224 struct scatterlist *sg; 225 int i; 226 227 data->blksz = HIF_MBOX_BLOCK_SIZE; 228 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 229 230 ath6kl_dbg(ATH6KL_DBG_SCATTER, 231 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 232 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 233 data->blksz, data->blocks, scat_req->len, 234 scat_req->scat_entries); 235 236 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 237 MMC_DATA_READ; 238 239 /* fill SG entries */ 240 sg = scat_req->sgentries; 241 sg_init_table(sg, scat_req->scat_entries); 242 243 /* assemble SG list */ 244 for (i = 0; i < scat_req->scat_entries; i++, sg++) { 245 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 246 i, scat_req->scat_list[i].buf, 247 scat_req->scat_list[i].len); 248 249 sg_set_buf(sg, scat_req->scat_list[i].buf, 250 scat_req->scat_list[i].len); 251 } 252 253 /* set scatter-gather table for request */ 254 data->sg = scat_req->sgentries; 255 data->sg_len = scat_req->scat_entries; 256 } 257 258 static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 259 struct bus_request *req) 260 { 261 struct mmc_request mmc_req; 262 struct mmc_command cmd; 263 struct mmc_data data; 264 struct hif_scatter_req *scat_req; 265 u8 opcode, rw; 266 int status, len; 267 268 scat_req = req->scat_req; 269 270 if (scat_req->virt_scat) { 271 len = scat_req->len; 272 if (scat_req->req & HIF_BLOCK_BASIS) 273 len = round_down(len, HIF_MBOX_BLOCK_SIZE); 274 275 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 276 scat_req->addr, scat_req->virt_dma_buf, 277 len); 278 goto scat_complete; 279 } 280 281 memset(&mmc_req, 0, sizeof(struct mmc_request)); 282 memset(&cmd, 0, sizeof(struct mmc_command)); 283 memset(&data, 0, sizeof(struct mmc_data)); 284 285 ath6kl_sdio_setup_scat_data(scat_req, &data); 286 287 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 288 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 289 290 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 291 292 /* Fixup the address so that the last byte will fall on MBOX EOM */ 293 if (scat_req->req & HIF_WRITE) { 294 if (scat_req->addr == HIF_MBOX_BASE_ADDR) 295 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 296 else 297 /* Uses extended address range */ 298 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 299 } 300 301 /* set command argument */ 302 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 303 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 304 data.blocks); 305 306 cmd.opcode = SD_IO_RW_EXTENDED; 307 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 308 309 mmc_req.cmd = &cmd; 310 mmc_req.data = &data; 311 312 sdio_claim_host(ar_sdio->func); 313 314 mmc_set_data_timeout(&data, ar_sdio->func->card); 315 316 trace_ath6kl_sdio_scat(scat_req->addr, 317 scat_req->req, 318 scat_req->len, 319 scat_req->scat_entries, 320 scat_req->scat_list); 321 322 /* synchronous call to process request */ 323 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 324 325 sdio_release_host(ar_sdio->func); 326 327 status = cmd.error ? cmd.error : data.error; 328 329 scat_complete: 330 scat_req->status = status; 331 332 if (scat_req->status) 333 ath6kl_err("Scatter write request failed:%d\n", 334 scat_req->status); 335 336 if (scat_req->req & HIF_ASYNCHRONOUS) 337 scat_req->complete(ar_sdio->ar->htc_target, scat_req); 338 339 return status; 340 } 341 342 static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 343 int n_scat_entry, int n_scat_req, 344 bool virt_scat) 345 { 346 struct hif_scatter_req *s_req; 347 struct bus_request *bus_req; 348 int i, scat_req_sz, scat_list_sz, size; 349 u8 *virt_buf; 350 351 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 352 scat_req_sz = sizeof(*s_req) + scat_list_sz; 353 354 if (!virt_scat) 355 size = sizeof(struct scatterlist) * n_scat_entry; 356 else 357 size = 2 * L1_CACHE_BYTES + 358 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 359 360 for (i = 0; i < n_scat_req; i++) { 361 /* allocate the scatter request */ 362 s_req = kzalloc(scat_req_sz, GFP_KERNEL); 363 if (!s_req) 364 return -ENOMEM; 365 366 if (virt_scat) { 367 virt_buf = kzalloc(size, GFP_KERNEL); 368 if (!virt_buf) { 369 kfree(s_req); 370 return -ENOMEM; 371 } 372 373 s_req->virt_dma_buf = 374 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 375 } else { 376 /* allocate sglist */ 377 s_req->sgentries = kzalloc(size, GFP_KERNEL); 378 379 if (!s_req->sgentries) { 380 kfree(s_req); 381 return -ENOMEM; 382 } 383 } 384 385 /* allocate a bus request for this scatter request */ 386 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 387 if (!bus_req) { 388 kfree(s_req->sgentries); 389 kfree(s_req->virt_dma_buf); 390 kfree(s_req); 391 return -ENOMEM; 392 } 393 394 /* assign the scatter request to this bus request */ 395 bus_req->scat_req = s_req; 396 s_req->busrequest = bus_req; 397 398 s_req->virt_scat = virt_scat; 399 400 /* add it to the scatter pool */ 401 hif_scatter_req_add(ar_sdio->ar, s_req); 402 } 403 404 return 0; 405 } 406 407 static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 408 u32 len, u32 request) 409 { 410 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 411 u8 *tbuf = NULL; 412 int ret; 413 bool bounced = false; 414 415 if (request & HIF_BLOCK_BASIS) 416 len = round_down(len, HIF_MBOX_BLOCK_SIZE); 417 418 if (buf_needs_bounce(buf)) { 419 if (!ar_sdio->dma_buffer) 420 return -ENOMEM; 421 mutex_lock(&ar_sdio->dma_buffer_mutex); 422 tbuf = ar_sdio->dma_buffer; 423 424 if (request & HIF_WRITE) 425 memcpy(tbuf, buf, len); 426 427 bounced = true; 428 } else 429 tbuf = buf; 430 431 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 432 if ((request & HIF_READ) && bounced) 433 memcpy(buf, tbuf, len); 434 435 if (bounced) 436 mutex_unlock(&ar_sdio->dma_buffer_mutex); 437 438 return ret; 439 } 440 441 static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 442 struct bus_request *req) 443 { 444 if (req->scat_req) 445 ath6kl_sdio_scat_rw(ar_sdio, req); 446 else { 447 void *context; 448 int status; 449 450 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 451 req->buffer, req->length, 452 req->request); 453 context = req->packet; 454 ath6kl_sdio_free_bus_req(ar_sdio, req); 455 ath6kl_hif_rw_comp_handler(context, status); 456 } 457 } 458 459 static void ath6kl_sdio_write_async_work(struct work_struct *work) 460 { 461 struct ath6kl_sdio *ar_sdio; 462 struct bus_request *req, *tmp_req; 463 464 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 465 466 spin_lock_bh(&ar_sdio->wr_async_lock); 467 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 468 list_del(&req->list); 469 spin_unlock_bh(&ar_sdio->wr_async_lock); 470 __ath6kl_sdio_write_async(ar_sdio, req); 471 spin_lock_bh(&ar_sdio->wr_async_lock); 472 } 473 spin_unlock_bh(&ar_sdio->wr_async_lock); 474 } 475 476 static void ath6kl_sdio_irq_handler(struct sdio_func *func) 477 { 478 int status; 479 struct ath6kl_sdio *ar_sdio; 480 481 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 482 483 ar_sdio = sdio_get_drvdata(func); 484 atomic_set(&ar_sdio->irq_handling, 1); 485 /* 486 * Release the host during interrups so we can pick it back up when 487 * we process commands. 488 */ 489 sdio_release_host(ar_sdio->func); 490 491 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 492 sdio_claim_host(ar_sdio->func); 493 494 atomic_set(&ar_sdio->irq_handling, 0); 495 wake_up(&ar_sdio->irq_wq); 496 497 WARN_ON(status && status != -ECANCELED); 498 } 499 500 static int ath6kl_sdio_power_on(struct ath6kl *ar) 501 { 502 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 503 struct sdio_func *func = ar_sdio->func; 504 int ret = 0; 505 506 if (!ar_sdio->is_disabled) 507 return 0; 508 509 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 510 511 sdio_claim_host(func); 512 513 ret = sdio_enable_func(func); 514 if (ret) { 515 ath6kl_err("Unable to enable sdio func: %d)\n", ret); 516 sdio_release_host(func); 517 return ret; 518 } 519 520 sdio_release_host(func); 521 522 /* 523 * Wait for hardware to initialise. It should take a lot less than 524 * 10 ms but let's be conservative here. 525 */ 526 msleep(10); 527 528 ar_sdio->is_disabled = false; 529 530 return ret; 531 } 532 533 static int ath6kl_sdio_power_off(struct ath6kl *ar) 534 { 535 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 536 int ret; 537 538 if (ar_sdio->is_disabled) 539 return 0; 540 541 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 542 543 /* Disable the card */ 544 sdio_claim_host(ar_sdio->func); 545 ret = sdio_disable_func(ar_sdio->func); 546 sdio_release_host(ar_sdio->func); 547 548 if (ret) 549 return ret; 550 551 ar_sdio->is_disabled = true; 552 553 return ret; 554 } 555 556 static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 557 u32 length, u32 request, 558 struct htc_packet *packet) 559 { 560 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 561 struct bus_request *bus_req; 562 563 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 564 565 if (WARN_ON_ONCE(!bus_req)) 566 return -ENOMEM; 567 568 bus_req->address = address; 569 bus_req->buffer = buffer; 570 bus_req->length = length; 571 bus_req->request = request; 572 bus_req->packet = packet; 573 574 spin_lock_bh(&ar_sdio->wr_async_lock); 575 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 576 spin_unlock_bh(&ar_sdio->wr_async_lock); 577 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 578 579 return 0; 580 } 581 582 static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 583 { 584 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 585 int ret; 586 587 sdio_claim_host(ar_sdio->func); 588 589 /* Register the isr */ 590 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 591 if (ret) 592 ath6kl_err("Failed to claim sdio irq: %d\n", ret); 593 594 sdio_release_host(ar_sdio->func); 595 } 596 597 static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar) 598 { 599 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 600 601 return !atomic_read(&ar_sdio->irq_handling); 602 } 603 604 static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 605 { 606 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 607 int ret; 608 609 sdio_claim_host(ar_sdio->func); 610 611 if (atomic_read(&ar_sdio->irq_handling)) { 612 sdio_release_host(ar_sdio->func); 613 614 ret = wait_event_interruptible(ar_sdio->irq_wq, 615 ath6kl_sdio_is_on_irq(ar)); 616 if (ret) 617 return; 618 619 sdio_claim_host(ar_sdio->func); 620 } 621 622 ret = sdio_release_irq(ar_sdio->func); 623 if (ret) 624 ath6kl_err("Failed to release sdio irq: %d\n", ret); 625 626 sdio_release_host(ar_sdio->func); 627 } 628 629 static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 630 { 631 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 632 struct hif_scatter_req *node = NULL; 633 634 spin_lock_bh(&ar_sdio->scat_lock); 635 636 if (!list_empty(&ar_sdio->scat_req)) { 637 node = list_first_entry(&ar_sdio->scat_req, 638 struct hif_scatter_req, list); 639 list_del(&node->list); 640 641 node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req); 642 } 643 644 spin_unlock_bh(&ar_sdio->scat_lock); 645 646 return node; 647 } 648 649 static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 650 struct hif_scatter_req *s_req) 651 { 652 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 653 654 spin_lock_bh(&ar_sdio->scat_lock); 655 656 list_add_tail(&s_req->list, &ar_sdio->scat_req); 657 658 spin_unlock_bh(&ar_sdio->scat_lock); 659 660 } 661 662 /* scatter gather read write request */ 663 static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 664 struct hif_scatter_req *scat_req) 665 { 666 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 667 u32 request = scat_req->req; 668 int status = 0; 669 670 if (!scat_req->len) 671 return -EINVAL; 672 673 ath6kl_dbg(ATH6KL_DBG_SCATTER, 674 "hif-scatter: total len: %d scatter entries: %d\n", 675 scat_req->len, scat_req->scat_entries); 676 677 if (request & HIF_SYNCHRONOUS) 678 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 679 else { 680 spin_lock_bh(&ar_sdio->wr_async_lock); 681 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 682 spin_unlock_bh(&ar_sdio->wr_async_lock); 683 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 684 } 685 686 return status; 687 } 688 689 /* clean up scatter support */ 690 static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 691 { 692 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 693 struct hif_scatter_req *s_req, *tmp_req; 694 695 /* empty the free list */ 696 spin_lock_bh(&ar_sdio->scat_lock); 697 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 698 list_del(&s_req->list); 699 spin_unlock_bh(&ar_sdio->scat_lock); 700 701 /* 702 * FIXME: should we also call completion handler with 703 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 704 * that the packet is properly freed? 705 */ 706 if (s_req->busrequest) 707 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 708 kfree(s_req->virt_dma_buf); 709 kfree(s_req->sgentries); 710 kfree(s_req); 711 712 spin_lock_bh(&ar_sdio->scat_lock); 713 } 714 spin_unlock_bh(&ar_sdio->scat_lock); 715 } 716 717 /* setup of HIF scatter resources */ 718 static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 719 { 720 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 721 struct htc_target *target = ar->htc_target; 722 int ret = 0; 723 bool virt_scat = false; 724 725 if (ar_sdio->scatter_enabled) 726 return 0; 727 728 ar_sdio->scatter_enabled = true; 729 730 /* check if host supports scatter and it meets our requirements */ 731 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 732 ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 733 ar_sdio->func->card->host->max_segs, 734 MAX_SCATTER_ENTRIES_PER_REQ); 735 virt_scat = true; 736 } 737 738 if (!virt_scat) { 739 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 740 MAX_SCATTER_ENTRIES_PER_REQ, 741 MAX_SCATTER_REQUESTS, virt_scat); 742 743 if (!ret) { 744 ath6kl_dbg(ATH6KL_DBG_BOOT, 745 "hif-scatter enabled requests %d entries %d\n", 746 MAX_SCATTER_REQUESTS, 747 MAX_SCATTER_ENTRIES_PER_REQ); 748 749 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 750 target->max_xfer_szper_scatreq = 751 MAX_SCATTER_REQ_TRANSFER_SIZE; 752 } else { 753 ath6kl_sdio_cleanup_scatter(ar); 754 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 755 } 756 } 757 758 if (virt_scat || ret) { 759 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 760 ATH6KL_SCATTER_ENTRIES_PER_REQ, 761 ATH6KL_SCATTER_REQS, virt_scat); 762 763 if (ret) { 764 ath6kl_err("failed to alloc virtual scatter resources !\n"); 765 ath6kl_sdio_cleanup_scatter(ar); 766 return ret; 767 } 768 769 ath6kl_dbg(ATH6KL_DBG_BOOT, 770 "virtual scatter enabled requests %d entries %d\n", 771 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 772 773 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 774 target->max_xfer_szper_scatreq = 775 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 776 } 777 778 return 0; 779 } 780 781 static int ath6kl_sdio_config(struct ath6kl *ar) 782 { 783 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 784 struct sdio_func *func = ar_sdio->func; 785 int ret; 786 787 sdio_claim_host(func); 788 789 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 790 MANUFACTURER_ID_AR6003_BASE) { 791 /* enable 4-bit ASYNC interrupt on AR6003 or later */ 792 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 793 CCCR_SDIO_IRQ_MODE_REG, 794 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 795 if (ret) { 796 ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 797 ret); 798 goto out; 799 } 800 801 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 802 } 803 804 /* give us some time to enable, in ms */ 805 func->enable_timeout = 100; 806 807 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 808 if (ret) { 809 ath6kl_err("Set sdio block size %d failed: %d)\n", 810 HIF_MBOX_BLOCK_SIZE, ret); 811 goto out; 812 } 813 814 out: 815 sdio_release_host(func); 816 817 return ret; 818 } 819 820 static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar) 821 { 822 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 823 struct sdio_func *func = ar_sdio->func; 824 mmc_pm_flag_t flags; 825 int ret; 826 827 flags = sdio_get_host_pm_caps(func); 828 829 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 830 831 if (!(flags & MMC_PM_WAKE_SDIO_IRQ) || 832 !(flags & MMC_PM_KEEP_POWER)) 833 return -EINVAL; 834 835 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 836 if (ret) { 837 ath6kl_err("set sdio keep pwr flag failed: %d\n", ret); 838 return ret; 839 } 840 841 /* sdio irq wakes up host */ 842 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 843 if (ret) 844 ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 845 846 return ret; 847 } 848 849 static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 850 { 851 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 852 struct sdio_func *func = ar_sdio->func; 853 mmc_pm_flag_t flags; 854 bool try_deepsleep = false; 855 int ret; 856 857 if (ar->suspend_mode == WLAN_POWER_STATE_WOW || 858 (!ar->suspend_mode && wow)) { 859 860 ret = ath6kl_set_sdio_pm_caps(ar); 861 if (ret) 862 goto cut_pwr; 863 864 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 865 if (ret && ret != -ENOTCONN) 866 ath6kl_err("wow suspend failed: %d\n", ret); 867 868 if (ret && 869 (!ar->wow_suspend_mode || 870 ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP)) 871 try_deepsleep = true; 872 else if (ret && 873 ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR) 874 goto cut_pwr; 875 if (!ret) 876 return 0; 877 } 878 879 if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP || 880 !ar->suspend_mode || try_deepsleep) { 881 882 flags = sdio_get_host_pm_caps(func); 883 if (!(flags & MMC_PM_KEEP_POWER)) 884 goto cut_pwr; 885 886 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 887 if (ret) 888 goto cut_pwr; 889 890 /* 891 * Workaround to support Deep Sleep with MSM, set the host pm 892 * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable 893 * the sdc2_clock and internally allows MSM to enter 894 * TCXO shutdown properly. 895 */ 896 if ((flags & MMC_PM_WAKE_SDIO_IRQ)) { 897 ret = sdio_set_host_pm_flags(func, 898 MMC_PM_WAKE_SDIO_IRQ); 899 if (ret) 900 goto cut_pwr; 901 } 902 903 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, 904 NULL); 905 if (ret) 906 goto cut_pwr; 907 908 return 0; 909 } 910 911 cut_pwr: 912 if (func->card && func->card->host) 913 func->card->host->pm_flags &= ~MMC_PM_KEEP_POWER; 914 915 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL); 916 } 917 918 static int ath6kl_sdio_resume(struct ath6kl *ar) 919 { 920 switch (ar->state) { 921 case ATH6KL_STATE_OFF: 922 case ATH6KL_STATE_CUTPOWER: 923 ath6kl_dbg(ATH6KL_DBG_SUSPEND, 924 "sdio resume configuring sdio\n"); 925 926 /* need to set sdio settings after power is cut from sdio */ 927 ath6kl_sdio_config(ar); 928 break; 929 930 case ATH6KL_STATE_ON: 931 break; 932 933 case ATH6KL_STATE_DEEPSLEEP: 934 break; 935 936 case ATH6KL_STATE_WOW: 937 break; 938 939 case ATH6KL_STATE_SUSPENDING: 940 break; 941 942 case ATH6KL_STATE_RESUMING: 943 break; 944 945 case ATH6KL_STATE_RECOVERY: 946 break; 947 } 948 949 ath6kl_cfg80211_resume(ar); 950 951 return 0; 952 } 953 954 /* set the window address register (using 4-byte register access ). */ 955 static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr) 956 { 957 int status; 958 u8 addr_val[4]; 959 s32 i; 960 961 /* 962 * Write bytes 1,2,3 of the register to set the upper address bytes, 963 * the LSB is written last to initiate the access cycle 964 */ 965 966 for (i = 1; i <= 3; i++) { 967 /* 968 * Fill the buffer with the address byte value we want to 969 * hit 4 times. 970 */ 971 memset(addr_val, ((u8 *)&addr)[i], 4); 972 973 /* 974 * Hit each byte of the register address with a 4-byte 975 * write operation to the same address, this is a harmless 976 * operation. 977 */ 978 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val, 979 4, HIF_WR_SYNC_BYTE_FIX); 980 if (status) 981 break; 982 } 983 984 if (status) { 985 ath6kl_err("%s: failed to write initial bytes of 0x%x to window reg: 0x%X\n", 986 __func__, addr, reg_addr); 987 return status; 988 } 989 990 /* 991 * Write the address register again, this time write the whole 992 * 4-byte value. The effect here is that the LSB write causes the 993 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no 994 * effect since we are writing the same values again 995 */ 996 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr), 997 4, HIF_WR_SYNC_BYTE_INC); 998 999 if (status) { 1000 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n", 1001 __func__, addr, reg_addr); 1002 return status; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data) 1009 { 1010 int status; 1011 1012 /* set window register to start read cycle */ 1013 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS, 1014 address); 1015 1016 if (status) 1017 return status; 1018 1019 /* read the data */ 1020 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1021 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC); 1022 if (status) { 1023 ath6kl_err("%s: failed to read from window data addr\n", 1024 __func__); 1025 return status; 1026 } 1027 1028 return status; 1029 } 1030 1031 static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address, 1032 __le32 data) 1033 { 1034 int status; 1035 u32 val = (__force u32) data; 1036 1037 /* set write data */ 1038 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1039 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); 1040 if (status) { 1041 ath6kl_err("%s: failed to write 0x%x to window data addr\n", 1042 __func__, data); 1043 return status; 1044 } 1045 1046 /* set window register, which starts the write cycle */ 1047 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS, 1048 address); 1049 } 1050 1051 static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 1052 { 1053 u32 addr; 1054 unsigned long timeout; 1055 int ret; 1056 1057 ar->bmi.cmd_credits = 0; 1058 1059 /* Read the counter register to get the command credits */ 1060 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 1061 1062 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 1063 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 1064 1065 /* 1066 * Hit the credit counter with a 4-byte access, the first byte 1067 * read will hit the counter and cause a decrement, while the 1068 * remaining 3 bytes has no effect. The rationale behind this 1069 * is to make all HIF accesses 4-byte aligned. 1070 */ 1071 ret = ath6kl_sdio_read_write_sync(ar, addr, 1072 (u8 *)&ar->bmi.cmd_credits, 4, 1073 HIF_RD_SYNC_BYTE_INC); 1074 if (ret) { 1075 ath6kl_err("Unable to decrement the command credit count register: %d\n", 1076 ret); 1077 return ret; 1078 } 1079 1080 /* The counter is only 8 bits. 1081 * Ignore anything in the upper 3 bytes 1082 */ 1083 ar->bmi.cmd_credits &= 0xFF; 1084 } 1085 1086 if (!ar->bmi.cmd_credits) { 1087 ath6kl_err("bmi communication timeout\n"); 1088 return -ETIMEDOUT; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 1095 { 1096 unsigned long timeout; 1097 u32 rx_word = 0; 1098 int ret = 0; 1099 1100 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 1101 while ((time_before(jiffies, timeout)) && !rx_word) { 1102 ret = ath6kl_sdio_read_write_sync(ar, 1103 RX_LOOKAHEAD_VALID_ADDRESS, 1104 (u8 *)&rx_word, sizeof(rx_word), 1105 HIF_RD_SYNC_BYTE_INC); 1106 if (ret) { 1107 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 1108 return ret; 1109 } 1110 1111 /* all we really want is one bit */ 1112 rx_word &= (1 << ENDPOINT1); 1113 } 1114 1115 if (!rx_word) { 1116 ath6kl_err("bmi_recv_buf FIFO empty\n"); 1117 return -EINVAL; 1118 } 1119 1120 return ret; 1121 } 1122 1123 static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 1124 { 1125 int ret; 1126 u32 addr; 1127 1128 ret = ath6kl_sdio_bmi_credits(ar); 1129 if (ret) 1130 return ret; 1131 1132 addr = ar->mbox_info.htc_addr; 1133 1134 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 1135 HIF_WR_SYNC_BYTE_INC); 1136 if (ret) { 1137 ath6kl_err("unable to send the bmi data to the device\n"); 1138 return ret; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 1145 { 1146 int ret; 1147 u32 addr; 1148 1149 /* 1150 * During normal bootup, small reads may be required. 1151 * Rather than issue an HIF Read and then wait as the Target 1152 * adds successive bytes to the FIFO, we wait here until 1153 * we know that response data is available. 1154 * 1155 * This allows us to cleanly timeout on an unexpected 1156 * Target failure rather than risk problems at the HIF level. 1157 * In particular, this avoids SDIO timeouts and possibly garbage 1158 * data on some host controllers. And on an interconnect 1159 * such as Compact Flash (as well as some SDIO masters) which 1160 * does not provide any indication on data timeout, it avoids 1161 * a potential hang or garbage response. 1162 * 1163 * Synchronization is more difficult for reads larger than the 1164 * size of the MBOX FIFO (128B), because the Target is unable 1165 * to push the 129th byte of data until AFTER the Host posts an 1166 * HIF Read and removes some FIFO data. So for large reads the 1167 * Host proceeds to post an HIF Read BEFORE all the data is 1168 * actually available to read. Fortunately, large BMI reads do 1169 * not occur in practice -- they're supported for debug/development. 1170 * 1171 * So Host/Target BMI synchronization is divided into these cases: 1172 * CASE 1: length < 4 1173 * Should not happen 1174 * 1175 * CASE 2: 4 <= length <= 128 1176 * Wait for first 4 bytes to be in FIFO 1177 * If CONSERVATIVE_BMI_READ is enabled, also wait for 1178 * a BMI command credit, which indicates that the ENTIRE 1179 * response is available in the the FIFO 1180 * 1181 * CASE 3: length > 128 1182 * Wait for the first 4 bytes to be in FIFO 1183 * 1184 * For most uses, a small timeout should be sufficient and we will 1185 * usually see a response quickly; but there may be some unusual 1186 * (debug) cases of BMI_EXECUTE where we want an larger timeout. 1187 * For now, we use an unbounded busy loop while waiting for 1188 * BMI_EXECUTE. 1189 * 1190 * If BMI_EXECUTE ever needs to support longer-latency execution, 1191 * especially in production, this code needs to be enhanced to sleep 1192 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 1193 * a function of Host processor speed. 1194 */ 1195 if (len >= 4) { /* NB: Currently, always true */ 1196 ret = ath6kl_bmi_get_rx_lkahd(ar); 1197 if (ret) 1198 return ret; 1199 } 1200 1201 addr = ar->mbox_info.htc_addr; 1202 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 1203 HIF_RD_SYNC_BYTE_INC); 1204 if (ret) { 1205 ath6kl_err("Unable to read the bmi data from the device: %d\n", 1206 ret); 1207 return ret; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static void ath6kl_sdio_stop(struct ath6kl *ar) 1214 { 1215 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 1216 struct bus_request *req, *tmp_req; 1217 void *context; 1218 1219 /* FIXME: make sure that wq is not queued again */ 1220 1221 cancel_work_sync(&ar_sdio->wr_async_work); 1222 1223 spin_lock_bh(&ar_sdio->wr_async_lock); 1224 1225 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 1226 list_del(&req->list); 1227 1228 if (req->scat_req) { 1229 /* this is a scatter gather request */ 1230 req->scat_req->status = -ECANCELED; 1231 req->scat_req->complete(ar_sdio->ar->htc_target, 1232 req->scat_req); 1233 } else { 1234 context = req->packet; 1235 ath6kl_sdio_free_bus_req(ar_sdio, req); 1236 ath6kl_hif_rw_comp_handler(context, -ECANCELED); 1237 } 1238 } 1239 1240 spin_unlock_bh(&ar_sdio->wr_async_lock); 1241 1242 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 1243 } 1244 1245 static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1246 .read_write_sync = ath6kl_sdio_read_write_sync, 1247 .write_async = ath6kl_sdio_write_async, 1248 .irq_enable = ath6kl_sdio_irq_enable, 1249 .irq_disable = ath6kl_sdio_irq_disable, 1250 .scatter_req_get = ath6kl_sdio_scatter_req_get, 1251 .scatter_req_add = ath6kl_sdio_scatter_req_add, 1252 .enable_scatter = ath6kl_sdio_enable_scatter, 1253 .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1254 .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1255 .suspend = ath6kl_sdio_suspend, 1256 .resume = ath6kl_sdio_resume, 1257 .diag_read32 = ath6kl_sdio_diag_read32, 1258 .diag_write32 = ath6kl_sdio_diag_write32, 1259 .bmi_read = ath6kl_sdio_bmi_read, 1260 .bmi_write = ath6kl_sdio_bmi_write, 1261 .power_on = ath6kl_sdio_power_on, 1262 .power_off = ath6kl_sdio_power_off, 1263 .stop = ath6kl_sdio_stop, 1264 }; 1265 1266 #ifdef CONFIG_PM_SLEEP 1267 1268 /* 1269 * Empty handlers so that mmc subsystem doesn't remove us entirely during 1270 * suspend. We instead follow cfg80211 suspend/resume handlers. 1271 */ 1272 static int ath6kl_sdio_pm_suspend(struct device *device) 1273 { 1274 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1275 1276 return 0; 1277 } 1278 1279 static int ath6kl_sdio_pm_resume(struct device *device) 1280 { 1281 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1282 1283 return 0; 1284 } 1285 1286 static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1287 ath6kl_sdio_pm_resume); 1288 1289 #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1290 1291 #else 1292 1293 #define ATH6KL_SDIO_PM_OPS NULL 1294 1295 #endif /* CONFIG_PM_SLEEP */ 1296 1297 static int ath6kl_sdio_probe(struct sdio_func *func, 1298 const struct sdio_device_id *id) 1299 { 1300 int ret; 1301 struct ath6kl_sdio *ar_sdio; 1302 struct ath6kl *ar; 1303 int count; 1304 1305 ath6kl_dbg(ATH6KL_DBG_BOOT, 1306 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1307 func->num, func->vendor, func->device, 1308 func->max_blksize, func->cur_blksize); 1309 1310 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1311 if (!ar_sdio) 1312 return -ENOMEM; 1313 1314 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1315 if (!ar_sdio->dma_buffer) { 1316 ret = -ENOMEM; 1317 goto err_hif; 1318 } 1319 1320 ar_sdio->func = func; 1321 sdio_set_drvdata(func, ar_sdio); 1322 1323 ar_sdio->id = id; 1324 ar_sdio->is_disabled = true; 1325 1326 spin_lock_init(&ar_sdio->lock); 1327 spin_lock_init(&ar_sdio->scat_lock); 1328 spin_lock_init(&ar_sdio->wr_async_lock); 1329 mutex_init(&ar_sdio->dma_buffer_mutex); 1330 1331 INIT_LIST_HEAD(&ar_sdio->scat_req); 1332 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1333 INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1334 1335 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1336 1337 init_waitqueue_head(&ar_sdio->irq_wq); 1338 1339 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1340 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1341 1342 ar = ath6kl_core_create(&ar_sdio->func->dev); 1343 if (!ar) { 1344 ath6kl_err("Failed to alloc ath6kl core\n"); 1345 ret = -ENOMEM; 1346 goto err_dma; 1347 } 1348 1349 ar_sdio->ar = ar; 1350 ar->hif_type = ATH6KL_HIF_TYPE_SDIO; 1351 ar->hif_priv = ar_sdio; 1352 ar->hif_ops = &ath6kl_sdio_ops; 1353 ar->bmi.max_data_size = 256; 1354 1355 ath6kl_sdio_set_mbox_info(ar); 1356 1357 ret = ath6kl_sdio_config(ar); 1358 if (ret) { 1359 ath6kl_err("Failed to config sdio: %d\n", ret); 1360 goto err_core_alloc; 1361 } 1362 1363 ret = ath6kl_core_init(ar, ATH6KL_HTC_TYPE_MBOX); 1364 if (ret) { 1365 ath6kl_err("Failed to init ath6kl core\n"); 1366 goto err_core_alloc; 1367 } 1368 1369 return ret; 1370 1371 err_core_alloc: 1372 ath6kl_core_destroy(ar_sdio->ar); 1373 err_dma: 1374 kfree(ar_sdio->dma_buffer); 1375 err_hif: 1376 kfree(ar_sdio); 1377 1378 return ret; 1379 } 1380 1381 static void ath6kl_sdio_remove(struct sdio_func *func) 1382 { 1383 struct ath6kl_sdio *ar_sdio; 1384 1385 ath6kl_dbg(ATH6KL_DBG_BOOT, 1386 "sdio removed func %d vendor 0x%x device 0x%x\n", 1387 func->num, func->vendor, func->device); 1388 1389 ar_sdio = sdio_get_drvdata(func); 1390 1391 ath6kl_stop_txrx(ar_sdio->ar); 1392 cancel_work_sync(&ar_sdio->wr_async_work); 1393 1394 ath6kl_core_cleanup(ar_sdio->ar); 1395 ath6kl_core_destroy(ar_sdio->ar); 1396 1397 kfree(ar_sdio->dma_buffer); 1398 kfree(ar_sdio); 1399 } 1400 1401 static const struct sdio_device_id ath6kl_sdio_devices[] = { 1402 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1403 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1404 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))}, 1405 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, 1406 {}, 1407 }; 1408 1409 MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1410 1411 static struct sdio_driver ath6kl_sdio_driver = { 1412 .name = "ath6kl_sdio", 1413 .id_table = ath6kl_sdio_devices, 1414 .probe = ath6kl_sdio_probe, 1415 .remove = ath6kl_sdio_remove, 1416 .drv.pm = ATH6KL_SDIO_PM_OPS, 1417 }; 1418 1419 static int __init ath6kl_sdio_init(void) 1420 { 1421 int ret; 1422 1423 ret = sdio_register_driver(&ath6kl_sdio_driver); 1424 if (ret) 1425 ath6kl_err("sdio driver registration failed: %d\n", ret); 1426 1427 return ret; 1428 } 1429 1430 static void __exit ath6kl_sdio_exit(void) 1431 { 1432 sdio_unregister_driver(&ath6kl_sdio_driver); 1433 } 1434 1435 module_init(ath6kl_sdio_init); 1436 module_exit(ath6kl_sdio_exit); 1437 1438 MODULE_AUTHOR("Atheros Communications, Inc."); 1439 MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1440 MODULE_LICENSE("Dual BSD/GPL"); 1441 1442 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE); 1443 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE); 1444 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE); 1445 MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE); 1446 MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE); 1447 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE); 1448 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE); 1449 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE); 1450 MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE); 1451 MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE); 1452 MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE); 1453 MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE); 1454 MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE); 1455 MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE); 1456 MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE); 1457 MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE); 1458 MODULE_FIRMWARE(AR6004_HW_1_2_FW_DIR "/" AR6004_HW_1_2_FIRMWARE_FILE); 1459 MODULE_FIRMWARE(AR6004_HW_1_2_BOARD_DATA_FILE); 1460 MODULE_FIRMWARE(AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE); 1461 MODULE_FIRMWARE(AR6004_HW_1_3_FW_DIR "/" AR6004_HW_1_3_FIRMWARE_FILE); 1462 MODULE_FIRMWARE(AR6004_HW_1_3_BOARD_DATA_FILE); 1463 MODULE_FIRMWARE(AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE); 1464