1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 179d9779e7SPaul Gortmaker #include <linux/module.h> 18bdcd8170SKalle Valo #include <linux/mmc/card.h> 19bdcd8170SKalle Valo #include <linux/mmc/mmc.h> 20bdcd8170SKalle Valo #include <linux/mmc/host.h> 21bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 22bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio.h> 24bdcd8170SKalle Valo #include <linux/mmc/sd.h> 252e1cb23cSKalle Valo #include "hif.h" 26bdcd8170SKalle Valo #include "hif-ops.h" 27bdcd8170SKalle Valo #include "target.h" 28bdcd8170SKalle Valo #include "debug.h" 299df337a1SVivek Natarajan #include "cfg80211.h" 30bdcd8170SKalle Valo 31bdcd8170SKalle Valo struct ath6kl_sdio { 32bdcd8170SKalle Valo struct sdio_func *func; 33bdcd8170SKalle Valo 34bdcd8170SKalle Valo spinlock_t lock; 35bdcd8170SKalle Valo 36bdcd8170SKalle Valo /* free list */ 37bdcd8170SKalle Valo struct list_head bus_req_freeq; 38bdcd8170SKalle Valo 39bdcd8170SKalle Valo /* available bus requests */ 40bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 41bdcd8170SKalle Valo 42bdcd8170SKalle Valo struct ath6kl *ar; 43fdb28589SRaja Mani 44bdcd8170SKalle Valo u8 *dma_buffer; 45bdcd8170SKalle Valo 46fdb28589SRaja Mani /* protects access to dma_buffer */ 47fdb28589SRaja Mani struct mutex dma_buffer_mutex; 48fdb28589SRaja Mani 49bdcd8170SKalle Valo /* scatter request list head */ 50bdcd8170SKalle Valo struct list_head scat_req; 51bdcd8170SKalle Valo 529d82682dSVasanthakumar Thiagarajan /* Avoids disabling irq while the interrupts being handled */ 539d82682dSVasanthakumar Thiagarajan struct mutex mtx_irq; 549d82682dSVasanthakumar Thiagarajan 55bdcd8170SKalle Valo spinlock_t scat_lock; 5632a07e44SKalle Valo bool scatter_enabled; 5732a07e44SKalle Valo 58bdcd8170SKalle Valo bool is_disabled; 59bdcd8170SKalle Valo const struct sdio_device_id *id; 60bdcd8170SKalle Valo struct work_struct wr_async_work; 61bdcd8170SKalle Valo struct list_head wr_asyncq; 62bdcd8170SKalle Valo spinlock_t wr_async_lock; 63bdcd8170SKalle Valo }; 64bdcd8170SKalle Valo 65bdcd8170SKalle Valo #define CMD53_ARG_READ 0 66bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1 67bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1 68bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0 69bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1 70bdcd8170SKalle Valo 71bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 72bdcd8170SKalle Valo { 73bdcd8170SKalle Valo return ar->hif_priv; 74bdcd8170SKalle Valo } 75bdcd8170SKalle Valo 76bdcd8170SKalle Valo /* 77bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able. 78bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will 79bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 80bdcd8170SKalle Valo * check fails on stack memory. 81bdcd8170SKalle Valo */ 82bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf) 83bdcd8170SKalle Valo { 84bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 85bdcd8170SKalle Valo } 86bdcd8170SKalle Valo 87bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 88bdcd8170SKalle Valo { 89bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 90bdcd8170SKalle Valo 91bdcd8170SKalle Valo /* EP1 has an extended range */ 92bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 93bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 94bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 95bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 96bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 97bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 98bdcd8170SKalle Valo } 99bdcd8170SKalle Valo 100bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 101bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr, 102bdcd8170SKalle Valo u16 blksz) 103bdcd8170SKalle Valo { 104bdcd8170SKalle Valo *arg = (((rw & 1) << 31) | 105bdcd8170SKalle Valo ((func & 0x7) << 28) | 106bdcd8170SKalle Valo ((mode & 1) << 27) | 107bdcd8170SKalle Valo ((opcode & 1) << 26) | 108bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) | 109bdcd8170SKalle Valo (blksz & 0x1FF)); 110bdcd8170SKalle Valo } 111bdcd8170SKalle Valo 112bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 113bdcd8170SKalle Valo unsigned int address, 114bdcd8170SKalle Valo unsigned char val) 115bdcd8170SKalle Valo { 116bdcd8170SKalle Valo const u8 func = 0; 117bdcd8170SKalle Valo 118bdcd8170SKalle Valo *arg = ((write & 1) << 31) | 119bdcd8170SKalle Valo ((func & 0x7) << 28) | 120bdcd8170SKalle Valo ((raw & 1) << 27) | 121bdcd8170SKalle Valo (1 << 26) | 122bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) | 123bdcd8170SKalle Valo (1 << 8) | 124bdcd8170SKalle Valo (val & 0xFF); 125bdcd8170SKalle Valo } 126bdcd8170SKalle Valo 127bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 128bdcd8170SKalle Valo unsigned int address, 129bdcd8170SKalle Valo unsigned char byte) 130bdcd8170SKalle Valo { 131bdcd8170SKalle Valo struct mmc_command io_cmd; 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd)); 134bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 135bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT; 136bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 137bdcd8170SKalle Valo 138bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0); 139bdcd8170SKalle Valo } 140bdcd8170SKalle Valo 141da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 142da220695SVasanthakumar Thiagarajan u8 *buf, u32 len) 143da220695SVasanthakumar Thiagarajan { 144da220695SVasanthakumar Thiagarajan int ret = 0; 145da220695SVasanthakumar Thiagarajan 146861dd058SVasanthakumar Thiagarajan sdio_claim_host(func); 147861dd058SVasanthakumar Thiagarajan 148da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) { 149f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */ 150da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR && 151da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR) 152da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len); 153da220695SVasanthakumar Thiagarajan 154f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */ 155da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR) 156da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len; 157da220695SVasanthakumar Thiagarajan 158da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 159da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len); 160da220695SVasanthakumar Thiagarajan else 161da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len); 162da220695SVasanthakumar Thiagarajan } else { 163da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 164da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len); 165da220695SVasanthakumar Thiagarajan else 166da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len); 167da220695SVasanthakumar Thiagarajan } 168da220695SVasanthakumar Thiagarajan 169861dd058SVasanthakumar Thiagarajan sdio_release_host(func); 170861dd058SVasanthakumar Thiagarajan 171f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 172f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr, 173f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 174f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 175f7325b85SKalle Valo 176da220695SVasanthakumar Thiagarajan return ret; 177da220695SVasanthakumar Thiagarajan } 178da220695SVasanthakumar Thiagarajan 179bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 180bdcd8170SKalle Valo { 181bdcd8170SKalle Valo struct bus_request *bus_req; 182bdcd8170SKalle Valo 183151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 184bdcd8170SKalle Valo 185bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) { 186151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 187bdcd8170SKalle Valo return NULL; 188bdcd8170SKalle Valo } 189bdcd8170SKalle Valo 190bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 191bdcd8170SKalle Valo struct bus_request, list); 192bdcd8170SKalle Valo list_del(&bus_req->list); 193bdcd8170SKalle Valo 194151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 195f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 196f7325b85SKalle Valo __func__, bus_req); 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo return bus_req; 199bdcd8170SKalle Valo } 200bdcd8170SKalle Valo 201bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 202bdcd8170SKalle Valo struct bus_request *bus_req) 203bdcd8170SKalle Valo { 204f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 205f7325b85SKalle Valo __func__, bus_req); 206bdcd8170SKalle Valo 207151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 208bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 209151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 210bdcd8170SKalle Valo } 211bdcd8170SKalle Valo 212bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 213bdcd8170SKalle Valo struct mmc_data *data) 214bdcd8170SKalle Valo { 215bdcd8170SKalle Valo struct scatterlist *sg; 216bdcd8170SKalle Valo int i; 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE; 219bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, 222bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 223bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 224bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len, 225bdcd8170SKalle Valo scat_req->scat_entries); 226bdcd8170SKalle Valo 227bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 228bdcd8170SKalle Valo MMC_DATA_READ; 229bdcd8170SKalle Valo 230bdcd8170SKalle Valo /* fill SG entries */ 231d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries; 232bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries); 233bdcd8170SKalle Valo 234bdcd8170SKalle Valo /* assemble SG list */ 235bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) { 236bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 237bdcd8170SKalle Valo i, scat_req->scat_list[i].buf, 238bdcd8170SKalle Valo scat_req->scat_list[i].len); 239bdcd8170SKalle Valo 240bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf, 241bdcd8170SKalle Valo scat_req->scat_list[i].len); 242bdcd8170SKalle Valo } 243bdcd8170SKalle Valo 244bdcd8170SKalle Valo /* set scatter-gather table for request */ 245d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries; 246bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries; 247bdcd8170SKalle Valo } 248bdcd8170SKalle Valo 249bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 250bdcd8170SKalle Valo struct bus_request *req) 251bdcd8170SKalle Valo { 252bdcd8170SKalle Valo struct mmc_request mmc_req; 253bdcd8170SKalle Valo struct mmc_command cmd; 254bdcd8170SKalle Valo struct mmc_data data; 255bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 256bdcd8170SKalle Valo u8 opcode, rw; 257348a8fbcSVasanthakumar Thiagarajan int status, len; 258bdcd8170SKalle Valo 259bdcd8170SKalle Valo scat_req = req->scat_req; 260bdcd8170SKalle Valo 261348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) { 262348a8fbcSVasanthakumar Thiagarajan len = scat_req->len; 263348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS) 264348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE); 265348a8fbcSVasanthakumar Thiagarajan 266348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 267348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf, 268348a8fbcSVasanthakumar Thiagarajan len); 269348a8fbcSVasanthakumar Thiagarajan goto scat_complete; 270348a8fbcSVasanthakumar Thiagarajan } 271348a8fbcSVasanthakumar Thiagarajan 272bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request)); 273bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command)); 274bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data)); 275bdcd8170SKalle Valo 276d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data); 277bdcd8170SKalle Valo 278bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 279bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 280bdcd8170SKalle Valo 281bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 282bdcd8170SKalle Valo 283bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */ 284bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) { 285bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR) 286bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 287bdcd8170SKalle Valo else 288bdcd8170SKalle Valo /* Uses extended address range */ 289bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 290bdcd8170SKalle Valo } 291bdcd8170SKalle Valo 292bdcd8170SKalle Valo /* set command argument */ 293bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 294bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 295bdcd8170SKalle Valo data.blocks); 296bdcd8170SKalle Valo 297bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED; 298bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo mmc_req.cmd = &cmd; 301bdcd8170SKalle Valo mmc_req.data = &data; 302bdcd8170SKalle Valo 303861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func); 304861dd058SVasanthakumar Thiagarajan 305bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card); 306bdcd8170SKalle Valo /* synchronous call to process request */ 307bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 308bdcd8170SKalle Valo 309861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func); 310861dd058SVasanthakumar Thiagarajan 311bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error; 312348a8fbcSVasanthakumar Thiagarajan 313348a8fbcSVasanthakumar Thiagarajan scat_complete: 314bdcd8170SKalle Valo scat_req->status = status; 315bdcd8170SKalle Valo 316bdcd8170SKalle Valo if (scat_req->status) 317bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n", 318bdcd8170SKalle Valo scat_req->status); 319bdcd8170SKalle Valo 320bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS) 321e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req); 322bdcd8170SKalle Valo 323bdcd8170SKalle Valo return status; 324bdcd8170SKalle Valo } 325bdcd8170SKalle Valo 3263df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 3273df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req, 3283df505adSVasanthakumar Thiagarajan bool virt_scat) 3293df505adSVasanthakumar Thiagarajan { 3303df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req; 3313df505adSVasanthakumar Thiagarajan struct bus_request *bus_req; 332cfeab10bSVasanthakumar Thiagarajan int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz; 333cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf; 3343df505adSVasanthakumar Thiagarajan 3353df505adSVasanthakumar Thiagarajan scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 3363df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz; 3373df505adSVasanthakumar Thiagarajan 3383df505adSVasanthakumar Thiagarajan if (!virt_scat) 3393df505adSVasanthakumar Thiagarajan sg_sz = sizeof(struct scatterlist) * n_scat_entry; 340cfeab10bSVasanthakumar Thiagarajan else 341cfeab10bSVasanthakumar Thiagarajan buf_sz = 2 * L1_CACHE_BYTES + 342cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 3433df505adSVasanthakumar Thiagarajan 3443df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) { 3453df505adSVasanthakumar Thiagarajan /* allocate the scatter request */ 3463df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL); 3473df505adSVasanthakumar Thiagarajan if (!s_req) 3483df505adSVasanthakumar Thiagarajan return -ENOMEM; 3493df505adSVasanthakumar Thiagarajan 350cfeab10bSVasanthakumar Thiagarajan if (virt_scat) { 351cfeab10bSVasanthakumar Thiagarajan virt_buf = kzalloc(buf_sz, GFP_KERNEL); 352cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) { 353cfeab10bSVasanthakumar Thiagarajan kfree(s_req); 354cfeab10bSVasanthakumar Thiagarajan return -ENOMEM; 355cfeab10bSVasanthakumar Thiagarajan } 356cfeab10bSVasanthakumar Thiagarajan 357cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf = 358cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 359cfeab10bSVasanthakumar Thiagarajan } else { 3603df505adSVasanthakumar Thiagarajan /* allocate sglist */ 3613df505adSVasanthakumar Thiagarajan s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL); 3623df505adSVasanthakumar Thiagarajan 3633df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) { 3643df505adSVasanthakumar Thiagarajan kfree(s_req); 3653df505adSVasanthakumar Thiagarajan return -ENOMEM; 3663df505adSVasanthakumar Thiagarajan } 3673df505adSVasanthakumar Thiagarajan } 3683df505adSVasanthakumar Thiagarajan 3693df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */ 3703df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 3713df505adSVasanthakumar Thiagarajan if (!bus_req) { 3723df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries); 373cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 3743df505adSVasanthakumar Thiagarajan kfree(s_req); 3753df505adSVasanthakumar Thiagarajan return -ENOMEM; 3763df505adSVasanthakumar Thiagarajan } 3773df505adSVasanthakumar Thiagarajan 3783df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */ 3793df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req; 3803df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req; 3813df505adSVasanthakumar Thiagarajan 3824a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat; 3834a005c3eSVasanthakumar Thiagarajan 3843df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */ 3853df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req); 3863df505adSVasanthakumar Thiagarajan } 3873df505adSVasanthakumar Thiagarajan 3883df505adSVasanthakumar Thiagarajan return 0; 3893df505adSVasanthakumar Thiagarajan } 3903df505adSVasanthakumar Thiagarajan 391bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 392bdcd8170SKalle Valo u32 len, u32 request) 393bdcd8170SKalle Valo { 394bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 395bdcd8170SKalle Valo u8 *tbuf = NULL; 396bdcd8170SKalle Valo int ret; 397bdcd8170SKalle Valo bool bounced = false; 398bdcd8170SKalle Valo 399bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS) 400bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE); 401bdcd8170SKalle Valo 402bdcd8170SKalle Valo if (buf_needs_bounce(buf)) { 403bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) 404bdcd8170SKalle Valo return -ENOMEM; 405fdb28589SRaja Mani mutex_lock(&ar_sdio->dma_buffer_mutex); 406bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer; 407bdcd8170SKalle Valo memcpy(tbuf, buf, len); 408bdcd8170SKalle Valo bounced = true; 409bdcd8170SKalle Valo } else 410bdcd8170SKalle Valo tbuf = buf; 411bdcd8170SKalle Valo 412da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 413da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced) 414bdcd8170SKalle Valo memcpy(buf, tbuf, len); 415bdcd8170SKalle Valo 416fdb28589SRaja Mani if (bounced) 417fdb28589SRaja Mani mutex_unlock(&ar_sdio->dma_buffer_mutex); 418fdb28589SRaja Mani 419bdcd8170SKalle Valo return ret; 420bdcd8170SKalle Valo } 421bdcd8170SKalle Valo 422bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 423bdcd8170SKalle Valo struct bus_request *req) 424bdcd8170SKalle Valo { 425bdcd8170SKalle Valo if (req->scat_req) 426bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req); 427bdcd8170SKalle Valo else { 428bdcd8170SKalle Valo void *context; 429bdcd8170SKalle Valo int status; 430bdcd8170SKalle Valo 431bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 432bdcd8170SKalle Valo req->buffer, req->length, 433bdcd8170SKalle Valo req->request); 434bdcd8170SKalle Valo context = req->packet; 435bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 4368e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status); 437bdcd8170SKalle Valo } 438bdcd8170SKalle Valo } 439bdcd8170SKalle Valo 440bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work) 441bdcd8170SKalle Valo { 442bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 443bdcd8170SKalle Valo struct bus_request *req, *tmp_req; 444bdcd8170SKalle Valo 445bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 446bdcd8170SKalle Valo 447151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 448bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 449bdcd8170SKalle Valo list_del(&req->list); 450151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 451bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req); 452151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 453bdcd8170SKalle Valo } 454151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 455bdcd8170SKalle Valo } 456bdcd8170SKalle Valo 457bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func) 458bdcd8170SKalle Valo { 459bdcd8170SKalle Valo int status; 460bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 461bdcd8170SKalle Valo 462f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 463f7325b85SKalle Valo 464bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 4659d82682dSVasanthakumar Thiagarajan mutex_lock(&ar_sdio->mtx_irq); 466bdcd8170SKalle Valo /* 467bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when 468bdcd8170SKalle Valo * we process commands. 469bdcd8170SKalle Valo */ 470bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 471bdcd8170SKalle Valo 4728e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 473bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 4749d82682dSVasanthakumar Thiagarajan mutex_unlock(&ar_sdio->mtx_irq); 475bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED); 476bdcd8170SKalle Valo } 477bdcd8170SKalle Valo 478b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar) 479bdcd8170SKalle Valo { 480b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 481bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func; 482bdcd8170SKalle Valo int ret = 0; 483bdcd8170SKalle Valo 484bdcd8170SKalle Valo if (!ar_sdio->is_disabled) 485bdcd8170SKalle Valo return 0; 486bdcd8170SKalle Valo 4873ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 4883ef987beSKalle Valo 489bdcd8170SKalle Valo sdio_claim_host(func); 490bdcd8170SKalle Valo 491bdcd8170SKalle Valo ret = sdio_enable_func(func); 492bdcd8170SKalle Valo if (ret) { 493bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret); 494bdcd8170SKalle Valo sdio_release_host(func); 495bdcd8170SKalle Valo return ret; 496bdcd8170SKalle Valo } 497bdcd8170SKalle Valo 498bdcd8170SKalle Valo sdio_release_host(func); 499bdcd8170SKalle Valo 500bdcd8170SKalle Valo /* 501bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than 502bdcd8170SKalle Valo * 10 ms but let's be conservative here. 503bdcd8170SKalle Valo */ 504bdcd8170SKalle Valo msleep(10); 505bdcd8170SKalle Valo 506bdcd8170SKalle Valo ar_sdio->is_disabled = false; 507bdcd8170SKalle Valo 508bdcd8170SKalle Valo return ret; 509bdcd8170SKalle Valo } 510bdcd8170SKalle Valo 511b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar) 512bdcd8170SKalle Valo { 513b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 514bdcd8170SKalle Valo int ret; 515bdcd8170SKalle Valo 516bdcd8170SKalle Valo if (ar_sdio->is_disabled) 517bdcd8170SKalle Valo return 0; 518bdcd8170SKalle Valo 5193ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 5203ef987beSKalle Valo 521bdcd8170SKalle Valo /* Disable the card */ 522bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 523bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func); 524bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 525bdcd8170SKalle Valo 526bdcd8170SKalle Valo if (ret) 527bdcd8170SKalle Valo return ret; 528bdcd8170SKalle Valo 529bdcd8170SKalle Valo ar_sdio->is_disabled = true; 530bdcd8170SKalle Valo 531bdcd8170SKalle Valo return ret; 532bdcd8170SKalle Valo } 533bdcd8170SKalle Valo 534bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 535bdcd8170SKalle Valo u32 length, u32 request, 536bdcd8170SKalle Valo struct htc_packet *packet) 537bdcd8170SKalle Valo { 538bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 539bdcd8170SKalle Valo struct bus_request *bus_req; 540bdcd8170SKalle Valo 541bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo if (!bus_req) 544bdcd8170SKalle Valo return -ENOMEM; 545bdcd8170SKalle Valo 546bdcd8170SKalle Valo bus_req->address = address; 547bdcd8170SKalle Valo bus_req->buffer = buffer; 548bdcd8170SKalle Valo bus_req->length = length; 549bdcd8170SKalle Valo bus_req->request = request; 550bdcd8170SKalle Valo bus_req->packet = packet; 551bdcd8170SKalle Valo 552151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 553bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 554151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 555bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 556bdcd8170SKalle Valo 557bdcd8170SKalle Valo return 0; 558bdcd8170SKalle Valo } 559bdcd8170SKalle Valo 560bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 561bdcd8170SKalle Valo { 562bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 563bdcd8170SKalle Valo int ret; 564bdcd8170SKalle Valo 565bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 566bdcd8170SKalle Valo 567bdcd8170SKalle Valo /* Register the isr */ 568bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 569bdcd8170SKalle Valo if (ret) 570bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret); 571bdcd8170SKalle Valo 572bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 573bdcd8170SKalle Valo } 574bdcd8170SKalle Valo 575bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 576bdcd8170SKalle Valo { 577bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 578bdcd8170SKalle Valo int ret; 579bdcd8170SKalle Valo 580bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 581bdcd8170SKalle Valo 5829d82682dSVasanthakumar Thiagarajan mutex_lock(&ar_sdio->mtx_irq); 583bdcd8170SKalle Valo 584bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func); 585bdcd8170SKalle Valo if (ret) 586bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret); 587bdcd8170SKalle Valo 5889d82682dSVasanthakumar Thiagarajan mutex_unlock(&ar_sdio->mtx_irq); 5899d82682dSVasanthakumar Thiagarajan 590bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 591bdcd8170SKalle Valo } 592bdcd8170SKalle Valo 593bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 594bdcd8170SKalle Valo { 595bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 596bdcd8170SKalle Valo struct hif_scatter_req *node = NULL; 597bdcd8170SKalle Valo 598151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 599bdcd8170SKalle Valo 600bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) { 601bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req, 602bdcd8170SKalle Valo struct hif_scatter_req, list); 603bdcd8170SKalle Valo list_del(&node->list); 604bdcd8170SKalle Valo } 605bdcd8170SKalle Valo 606151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 607bdcd8170SKalle Valo 608bdcd8170SKalle Valo return node; 609bdcd8170SKalle Valo } 610bdcd8170SKalle Valo 611bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 612bdcd8170SKalle Valo struct hif_scatter_req *s_req) 613bdcd8170SKalle Valo { 614bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 615bdcd8170SKalle Valo 616151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 617bdcd8170SKalle Valo 618bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req); 619bdcd8170SKalle Valo 620151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 621bdcd8170SKalle Valo 622bdcd8170SKalle Valo } 623bdcd8170SKalle Valo 624c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */ 625c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 626c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req) 627c630d18aSVasanthakumar Thiagarajan { 628c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 629c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req; 630c630d18aSVasanthakumar Thiagarajan int status = 0; 631c630d18aSVasanthakumar Thiagarajan 632c630d18aSVasanthakumar Thiagarajan if (!scat_req->len) 633c630d18aSVasanthakumar Thiagarajan return -EINVAL; 634c630d18aSVasanthakumar Thiagarajan 635c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER, 636c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n", 637c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries); 638c630d18aSVasanthakumar Thiagarajan 639861dd058SVasanthakumar Thiagarajan if (request & HIF_SYNCHRONOUS) 640d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 641861dd058SVasanthakumar Thiagarajan else { 642151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 643d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 644151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 645c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 646c630d18aSVasanthakumar Thiagarajan } 647c630d18aSVasanthakumar Thiagarajan 648c630d18aSVasanthakumar Thiagarajan return status; 649c630d18aSVasanthakumar Thiagarajan } 650c630d18aSVasanthakumar Thiagarajan 65118a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */ 65218a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 65318a0f93eSVasanthakumar Thiagarajan { 65418a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 65518a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req; 65618a0f93eSVasanthakumar Thiagarajan 65718a0f93eSVasanthakumar Thiagarajan /* empty the free list */ 658151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 65918a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 66018a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list); 661151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 66218a0f93eSVasanthakumar Thiagarajan 66332a07e44SKalle Valo /* 66432a07e44SKalle Valo * FIXME: should we also call completion handler with 66532a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 66632a07e44SKalle Valo * that the packet is properly freed? 66732a07e44SKalle Valo */ 66818a0f93eSVasanthakumar Thiagarajan if (s_req->busrequest) 66918a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 67018a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 67118a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries); 67218a0f93eSVasanthakumar Thiagarajan kfree(s_req); 67318a0f93eSVasanthakumar Thiagarajan 674151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 67518a0f93eSVasanthakumar Thiagarajan } 676151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 67718a0f93eSVasanthakumar Thiagarajan } 67818a0f93eSVasanthakumar Thiagarajan 67918a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */ 68050745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 68118a0f93eSVasanthakumar Thiagarajan { 68218a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 68350745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target; 684cfeab10bSVasanthakumar Thiagarajan int ret; 685cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false; 68618a0f93eSVasanthakumar Thiagarajan 68732a07e44SKalle Valo if (ar_sdio->scatter_enabled) 68832a07e44SKalle Valo return 0; 68932a07e44SKalle Valo 69032a07e44SKalle Valo ar_sdio->scatter_enabled = true; 69132a07e44SKalle Valo 69218a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */ 69318a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 694cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 69518a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs, 69618a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 697cfeab10bSVasanthakumar Thiagarajan virt_scat = true; 69818a0f93eSVasanthakumar Thiagarajan } 69918a0f93eSVasanthakumar Thiagarajan 700cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) { 70118a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 70218a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ, 703cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat); 704cfeab10bSVasanthakumar Thiagarajan 705cfeab10bSVasanthakumar Thiagarajan if (!ret) { 7063ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7073ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n", 708cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, 709cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 710cfeab10bSVasanthakumar Thiagarajan 71150745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 71250745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 713cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE; 714cfeab10bSVasanthakumar Thiagarajan } else { 715cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 716cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 717cfeab10bSVasanthakumar Thiagarajan } 718cfeab10bSVasanthakumar Thiagarajan } 719cfeab10bSVasanthakumar Thiagarajan 720cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) { 721cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 722cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ, 723cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat); 724cfeab10bSVasanthakumar Thiagarajan 72518a0f93eSVasanthakumar Thiagarajan if (ret) { 726cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n"); 72718a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 72818a0f93eSVasanthakumar Thiagarajan return ret; 72918a0f93eSVasanthakumar Thiagarajan } 73018a0f93eSVasanthakumar Thiagarajan 7313ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7323ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n", 733cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 734cfeab10bSVasanthakumar Thiagarajan 73550745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 73650745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 737cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 738cfeab10bSVasanthakumar Thiagarajan } 739cfeab10bSVasanthakumar Thiagarajan 74018a0f93eSVasanthakumar Thiagarajan return 0; 74118a0f93eSVasanthakumar Thiagarajan } 74218a0f93eSVasanthakumar Thiagarajan 743e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar) 744e28e8104SKalle Valo { 745e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 746e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func; 747e28e8104SKalle Valo int ret; 748e28e8104SKalle Valo 749e28e8104SKalle Valo sdio_claim_host(func); 750e28e8104SKalle Valo 751e28e8104SKalle Valo if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 752e28e8104SKalle Valo MANUFACTURER_ID_AR6003_BASE) { 753e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */ 754e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 755e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG, 756e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 757e28e8104SKalle Valo if (ret) { 758e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 759e28e8104SKalle Valo ret); 760e28e8104SKalle Valo goto out; 761e28e8104SKalle Valo } 762e28e8104SKalle Valo 763e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 764e28e8104SKalle Valo } 765e28e8104SKalle Valo 766e28e8104SKalle Valo /* give us some time to enable, in ms */ 767e28e8104SKalle Valo func->enable_timeout = 100; 768e28e8104SKalle Valo 769e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 770e28e8104SKalle Valo if (ret) { 771e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n", 772e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret); 773e28e8104SKalle Valo goto out; 774e28e8104SKalle Valo } 775e28e8104SKalle Valo 776e28e8104SKalle Valo out: 777e28e8104SKalle Valo sdio_release_host(func); 778e28e8104SKalle Valo 779e28e8104SKalle Valo return ret; 780e28e8104SKalle Valo } 781e28e8104SKalle Valo 782e390af77SRaja Mani static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar) 783abcb344bSKalle Valo { 784abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 785abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func; 786abcb344bSKalle Valo mmc_pm_flag_t flags; 787abcb344bSKalle Valo int ret; 788abcb344bSKalle Valo 789abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func); 790abcb344bSKalle Valo 791b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 792b4b2a0b1SKalle Valo 793e390af77SRaja Mani if (!(flags & MMC_PM_WAKE_SDIO_IRQ) || 794e390af77SRaja Mani !(flags & MMC_PM_KEEP_POWER)) 795e390af77SRaja Mani return -EINVAL; 796abcb344bSKalle Valo 797abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 798abcb344bSKalle Valo if (ret) { 799e390af77SRaja Mani ath6kl_err("set sdio keep pwr flag failed: %d\n", ret); 800abcb344bSKalle Valo return ret; 801abcb344bSKalle Valo } 802abcb344bSKalle Valo 80310509f90SKalle Valo /* sdio irq wakes up host */ 804d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 805d7c44e0bSRaja Mani if (ret) 806d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 807d7c44e0bSRaja Mani 808d7c44e0bSRaja Mani return ret; 809d7c44e0bSRaja Mani } 810d7c44e0bSRaja Mani 811e390af77SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 812e390af77SRaja Mani { 813e390af77SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 814e390af77SRaja Mani struct sdio_func *func = ar_sdio->func; 815e390af77SRaja Mani mmc_pm_flag_t flags; 816e390af77SRaja Mani int ret; 817e390af77SRaja Mani 818e390af77SRaja Mani if (ar->state == ATH6KL_STATE_SCHED_SCAN) { 819e390af77SRaja Mani ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sched scan is in progress\n"); 820e390af77SRaja Mani 821e390af77SRaja Mani ret = ath6kl_set_sdio_pm_caps(ar); 822e390af77SRaja Mani if (ret) 823e390af77SRaja Mani goto cut_pwr; 824e390af77SRaja Mani 825e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, 826e390af77SRaja Mani ATH6KL_CFG_SUSPEND_SCHED_SCAN, 827e390af77SRaja Mani NULL); 828e390af77SRaja Mani if (ret) 829e390af77SRaja Mani goto cut_pwr; 830e390af77SRaja Mani 831e390af77SRaja Mani return 0; 832e390af77SRaja Mani } 833e390af77SRaja Mani 834e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_WOW || 835e390af77SRaja Mani (!ar->suspend_mode && wow)) { 836e390af77SRaja Mani 837e390af77SRaja Mani ret = ath6kl_set_sdio_pm_caps(ar); 838e390af77SRaja Mani if (ret) 839e390af77SRaja Mani goto cut_pwr; 840e390af77SRaja Mani 841e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 842e390af77SRaja Mani if (ret) 843e390af77SRaja Mani goto cut_pwr; 844e390af77SRaja Mani 845e390af77SRaja Mani return 0; 846e390af77SRaja Mani } 847e390af77SRaja Mani 848e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP || 849e390af77SRaja Mani !ar->suspend_mode) { 850e390af77SRaja Mani 851e390af77SRaja Mani flags = sdio_get_host_pm_caps(func); 852e390af77SRaja Mani if (!(flags & MMC_PM_KEEP_POWER)) 853e390af77SRaja Mani goto cut_pwr; 854e390af77SRaja Mani 855e390af77SRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 856e390af77SRaja Mani if (ret) 857e390af77SRaja Mani goto cut_pwr; 858e390af77SRaja Mani 859cca4d5adSSantosh Sajjan /* 860cca4d5adSSantosh Sajjan * Workaround to support Deep Sleep with MSM, set the host pm 861cca4d5adSSantosh Sajjan * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable 862cca4d5adSSantosh Sajjan * the sdc2_clock and internally allows MSM to enter 863cca4d5adSSantosh Sajjan * TCXO shutdown properly. 864cca4d5adSSantosh Sajjan */ 865cca4d5adSSantosh Sajjan if ((flags & MMC_PM_WAKE_SDIO_IRQ)) { 866cca4d5adSSantosh Sajjan ret = sdio_set_host_pm_flags(func, 867cca4d5adSSantosh Sajjan MMC_PM_WAKE_SDIO_IRQ); 868cca4d5adSSantosh Sajjan if (ret) 869cca4d5adSSantosh Sajjan goto cut_pwr; 870cca4d5adSSantosh Sajjan } 871cca4d5adSSantosh Sajjan 872e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, 873e390af77SRaja Mani NULL); 874e390af77SRaja Mani if (ret) 875e390af77SRaja Mani goto cut_pwr; 876e390af77SRaja Mani 877e390af77SRaja Mani return 0; 878e390af77SRaja Mani } 879e390af77SRaja Mani 880e390af77SRaja Mani cut_pwr: 881e390af77SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL); 882abcb344bSKalle Valo } 883abcb344bSKalle Valo 884aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar) 885aa6cffc1SChilam Ng { 886b4b2a0b1SKalle Valo switch (ar->state) { 887b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF: 888b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER: 889b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, 890b4b2a0b1SKalle Valo "sdio resume configuring sdio\n"); 891b4b2a0b1SKalle Valo 892b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */ 893b4b2a0b1SKalle Valo ath6kl_sdio_config(ar); 894b4b2a0b1SKalle Valo break; 895b4b2a0b1SKalle Valo 896b4b2a0b1SKalle Valo case ATH6KL_STATE_ON: 897b4b2a0b1SKalle Valo break; 898b4b2a0b1SKalle Valo 899b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP: 900b4b2a0b1SKalle Valo break; 901d7c44e0bSRaja Mani 902d7c44e0bSRaja Mani case ATH6KL_STATE_WOW: 903d7c44e0bSRaja Mani break; 90410509f90SKalle Valo case ATH6KL_STATE_SCHED_SCAN: 90510509f90SKalle Valo break; 906b4b2a0b1SKalle Valo } 907b4b2a0b1SKalle Valo 90852d81a68SKalle Valo ath6kl_cfg80211_resume(ar); 909aa6cffc1SChilam Ng 910aa6cffc1SChilam Ng return 0; 911aa6cffc1SChilam Ng } 912aa6cffc1SChilam Ng 913c7111495SKalle Valo /* set the window address register (using 4-byte register access ). */ 914c7111495SKalle Valo static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr) 915c7111495SKalle Valo { 916c7111495SKalle Valo int status; 917c7111495SKalle Valo u8 addr_val[4]; 918c7111495SKalle Valo s32 i; 919c7111495SKalle Valo 920c7111495SKalle Valo /* 921c7111495SKalle Valo * Write bytes 1,2,3 of the register to set the upper address bytes, 922c7111495SKalle Valo * the LSB is written last to initiate the access cycle 923c7111495SKalle Valo */ 924c7111495SKalle Valo 925c7111495SKalle Valo for (i = 1; i <= 3; i++) { 926c7111495SKalle Valo /* 927c7111495SKalle Valo * Fill the buffer with the address byte value we want to 928c7111495SKalle Valo * hit 4 times. 929c7111495SKalle Valo */ 930c7111495SKalle Valo memset(addr_val, ((u8 *)&addr)[i], 4); 931c7111495SKalle Valo 932c7111495SKalle Valo /* 933c7111495SKalle Valo * Hit each byte of the register address with a 4-byte 934c7111495SKalle Valo * write operation to the same address, this is a harmless 935c7111495SKalle Valo * operation. 936c7111495SKalle Valo */ 937c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val, 938c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_FIX); 939c7111495SKalle Valo if (status) 940c7111495SKalle Valo break; 941c7111495SKalle Valo } 942c7111495SKalle Valo 943c7111495SKalle Valo if (status) { 944c7111495SKalle Valo ath6kl_err("%s: failed to write initial bytes of 0x%x " 945c7111495SKalle Valo "to window reg: 0x%X\n", __func__, 946c7111495SKalle Valo addr, reg_addr); 947c7111495SKalle Valo return status; 948c7111495SKalle Valo } 949c7111495SKalle Valo 950c7111495SKalle Valo /* 951c7111495SKalle Valo * Write the address register again, this time write the whole 952c7111495SKalle Valo * 4-byte value. The effect here is that the LSB write causes the 953c7111495SKalle Valo * cycle to start, the extra 3 byte write to bytes 1,2,3 has no 954c7111495SKalle Valo * effect since we are writing the same values again 955c7111495SKalle Valo */ 956c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr), 957c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_INC); 958c7111495SKalle Valo 959c7111495SKalle Valo if (status) { 960c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n", 961c7111495SKalle Valo __func__, addr, reg_addr); 962c7111495SKalle Valo return status; 963c7111495SKalle Valo } 964c7111495SKalle Valo 965c7111495SKalle Valo return 0; 966c7111495SKalle Valo } 967c7111495SKalle Valo 968c7111495SKalle Valo static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data) 969c7111495SKalle Valo { 970c7111495SKalle Valo int status; 971c7111495SKalle Valo 972c7111495SKalle Valo /* set window register to start read cycle */ 973c7111495SKalle Valo status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS, 974c7111495SKalle Valo address); 975c7111495SKalle Valo 976c7111495SKalle Valo if (status) 977c7111495SKalle Valo return status; 978c7111495SKalle Valo 979c7111495SKalle Valo /* read the data */ 980c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 981c7111495SKalle Valo (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC); 982c7111495SKalle Valo if (status) { 983c7111495SKalle Valo ath6kl_err("%s: failed to read from window data addr\n", 984c7111495SKalle Valo __func__); 985c7111495SKalle Valo return status; 986c7111495SKalle Valo } 987c7111495SKalle Valo 988c7111495SKalle Valo return status; 989c7111495SKalle Valo } 990c7111495SKalle Valo 991c7111495SKalle Valo static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address, 992c7111495SKalle Valo __le32 data) 993c7111495SKalle Valo { 994c7111495SKalle Valo int status; 995c7111495SKalle Valo u32 val = (__force u32) data; 996c7111495SKalle Valo 997c7111495SKalle Valo /* set write data */ 998c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 999c7111495SKalle Valo (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); 1000c7111495SKalle Valo if (status) { 1001c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window data addr\n", 1002c7111495SKalle Valo __func__, data); 1003c7111495SKalle Valo return status; 1004c7111495SKalle Valo } 1005c7111495SKalle Valo 1006c7111495SKalle Valo /* set window register, which starts the write cycle */ 1007c7111495SKalle Valo return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS, 1008c7111495SKalle Valo address); 1009c7111495SKalle Valo } 1010c7111495SKalle Valo 101166b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 101266b693c3SKalle Valo { 101366b693c3SKalle Valo u32 addr; 101466b693c3SKalle Valo unsigned long timeout; 101566b693c3SKalle Valo int ret; 101666b693c3SKalle Valo 101766b693c3SKalle Valo ar->bmi.cmd_credits = 0; 101866b693c3SKalle Valo 101966b693c3SKalle Valo /* Read the counter register to get the command credits */ 102066b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 102166b693c3SKalle Valo 102266b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 102366b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 102466b693c3SKalle Valo 102566b693c3SKalle Valo /* 102666b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte 102766b693c3SKalle Valo * read will hit the counter and cause a decrement, while the 102866b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this 102966b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned. 103066b693c3SKalle Valo */ 103166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, 103266b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4, 103366b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 103466b693c3SKalle Valo if (ret) { 103566b693c3SKalle Valo ath6kl_err("Unable to decrement the command credit " 103666b693c3SKalle Valo "count register: %d\n", ret); 103766b693c3SKalle Valo return ret; 103866b693c3SKalle Valo } 103966b693c3SKalle Valo 104066b693c3SKalle Valo /* The counter is only 8 bits. 104166b693c3SKalle Valo * Ignore anything in the upper 3 bytes 104266b693c3SKalle Valo */ 104366b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF; 104466b693c3SKalle Valo } 104566b693c3SKalle Valo 104666b693c3SKalle Valo if (!ar->bmi.cmd_credits) { 104766b693c3SKalle Valo ath6kl_err("bmi communication timeout\n"); 104866b693c3SKalle Valo return -ETIMEDOUT; 104966b693c3SKalle Valo } 105066b693c3SKalle Valo 105166b693c3SKalle Valo return 0; 105266b693c3SKalle Valo } 105366b693c3SKalle Valo 105466b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 105566b693c3SKalle Valo { 105666b693c3SKalle Valo unsigned long timeout; 105766b693c3SKalle Valo u32 rx_word = 0; 105866b693c3SKalle Valo int ret = 0; 105966b693c3SKalle Valo 106066b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 106166b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) { 106266b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, 106366b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS, 106466b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word), 106566b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 106666b693c3SKalle Valo if (ret) { 106766b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 106866b693c3SKalle Valo return ret; 106966b693c3SKalle Valo } 107066b693c3SKalle Valo 107166b693c3SKalle Valo /* all we really want is one bit */ 107266b693c3SKalle Valo rx_word &= (1 << ENDPOINT1); 107366b693c3SKalle Valo } 107466b693c3SKalle Valo 107566b693c3SKalle Valo if (!rx_word) { 107666b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n"); 107766b693c3SKalle Valo return -EINVAL; 107866b693c3SKalle Valo } 107966b693c3SKalle Valo 108066b693c3SKalle Valo return ret; 108166b693c3SKalle Valo } 108266b693c3SKalle Valo 108366b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 108466b693c3SKalle Valo { 108566b693c3SKalle Valo int ret; 108666b693c3SKalle Valo u32 addr; 108766b693c3SKalle Valo 108866b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar); 108966b693c3SKalle Valo if (ret) 109066b693c3SKalle Valo return ret; 109166b693c3SKalle Valo 109266b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 109366b693c3SKalle Valo 109466b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 109566b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC); 109666b693c3SKalle Valo if (ret) 109766b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n"); 109866b693c3SKalle Valo 109966b693c3SKalle Valo return ret; 110066b693c3SKalle Valo } 110166b693c3SKalle Valo 110266b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 110366b693c3SKalle Valo { 110466b693c3SKalle Valo int ret; 110566b693c3SKalle Valo u32 addr; 110666b693c3SKalle Valo 110766b693c3SKalle Valo /* 110866b693c3SKalle Valo * During normal bootup, small reads may be required. 110966b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target 111066b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until 111166b693c3SKalle Valo * we know that response data is available. 111266b693c3SKalle Valo * 111366b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected 111466b693c3SKalle Valo * Target failure rather than risk problems at the HIF level. 111566b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage 111666b693c3SKalle Valo * data on some host controllers. And on an interconnect 111766b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which 111866b693c3SKalle Valo * does not provide any indication on data timeout, it avoids 111966b693c3SKalle Valo * a potential hang or garbage response. 112066b693c3SKalle Valo * 112166b693c3SKalle Valo * Synchronization is more difficult for reads larger than the 112266b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable 112366b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an 112466b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the 112566b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is 112666b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do 112766b693c3SKalle Valo * not occur in practice -- they're supported for debug/development. 112866b693c3SKalle Valo * 112966b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases: 113066b693c3SKalle Valo * CASE 1: length < 4 113166b693c3SKalle Valo * Should not happen 113266b693c3SKalle Valo * 113366b693c3SKalle Valo * CASE 2: 4 <= length <= 128 113466b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO 113566b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for 113666b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE 113766b693c3SKalle Valo * response is available in the the FIFO 113866b693c3SKalle Valo * 113966b693c3SKalle Valo * CASE 3: length > 128 114066b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO 114166b693c3SKalle Valo * 114266b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will 114366b693c3SKalle Valo * usually see a response quickly; but there may be some unusual 114466b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout. 114566b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for 114666b693c3SKalle Valo * BMI_EXECUTE. 114766b693c3SKalle Valo * 114866b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution, 114966b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep 115066b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 115166b693c3SKalle Valo * a function of Host processor speed. 115266b693c3SKalle Valo */ 115366b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */ 115466b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar); 115566b693c3SKalle Valo if (ret) 115666b693c3SKalle Valo return ret; 115766b693c3SKalle Valo } 115866b693c3SKalle Valo 115966b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 116066b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 116166b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 116266b693c3SKalle Valo if (ret) { 116366b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n", 116466b693c3SKalle Valo ret); 116566b693c3SKalle Valo return ret; 116666b693c3SKalle Valo } 116766b693c3SKalle Valo 116866b693c3SKalle Valo return 0; 116966b693c3SKalle Valo } 117066b693c3SKalle Valo 117132a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar) 117232a07e44SKalle Valo { 117332a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 117432a07e44SKalle Valo struct bus_request *req, *tmp_req; 117532a07e44SKalle Valo void *context; 117632a07e44SKalle Valo 117732a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */ 117832a07e44SKalle Valo 117932a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 118032a07e44SKalle Valo 118132a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock); 118232a07e44SKalle Valo 118332a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 118432a07e44SKalle Valo list_del(&req->list); 118532a07e44SKalle Valo 118632a07e44SKalle Valo if (req->scat_req) { 118732a07e44SKalle Valo /* this is a scatter gather request */ 118832a07e44SKalle Valo req->scat_req->status = -ECANCELED; 118932a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target, 119032a07e44SKalle Valo req->scat_req); 119132a07e44SKalle Valo } else { 119232a07e44SKalle Valo context = req->packet; 119332a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 119432a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED); 119532a07e44SKalle Valo } 119632a07e44SKalle Valo } 119732a07e44SKalle Valo 119832a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock); 119932a07e44SKalle Valo 120032a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 120132a07e44SKalle Valo } 120232a07e44SKalle Valo 1203bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1204bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync, 1205bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async, 1206bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable, 1207bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable, 1208bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get, 1209bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add, 1210bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter, 1211f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1212bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1213abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend, 1214aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume, 1215c7111495SKalle Valo .diag_read32 = ath6kl_sdio_diag_read32, 1216c7111495SKalle Valo .diag_write32 = ath6kl_sdio_diag_write32, 121766b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read, 121866b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write, 1219b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on, 1220b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off, 122132a07e44SKalle Valo .stop = ath6kl_sdio_stop, 1222bdcd8170SKalle Valo }; 1223bdcd8170SKalle Valo 1224b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP 1225b4b2a0b1SKalle Valo 1226b4b2a0b1SKalle Valo /* 1227b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during 1228b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers. 1229b4b2a0b1SKalle Valo */ 1230b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device) 1231b4b2a0b1SKalle Valo { 1232b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1233b4b2a0b1SKalle Valo 1234b4b2a0b1SKalle Valo return 0; 1235b4b2a0b1SKalle Valo } 1236b4b2a0b1SKalle Valo 1237b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device) 1238b4b2a0b1SKalle Valo { 1239b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1240b4b2a0b1SKalle Valo 1241b4b2a0b1SKalle Valo return 0; 1242b4b2a0b1SKalle Valo } 1243b4b2a0b1SKalle Valo 1244b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1245b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume); 1246b4b2a0b1SKalle Valo 1247b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1248b4b2a0b1SKalle Valo 1249b4b2a0b1SKalle Valo #else 1250b4b2a0b1SKalle Valo 1251b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL 1252b4b2a0b1SKalle Valo 1253b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */ 1254b4b2a0b1SKalle Valo 1255bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func, 1256bdcd8170SKalle Valo const struct sdio_device_id *id) 1257bdcd8170SKalle Valo { 1258bdcd8170SKalle Valo int ret; 1259bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1260bdcd8170SKalle Valo struct ath6kl *ar; 1261bdcd8170SKalle Valo int count; 1262bdcd8170SKalle Valo 12633ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 12643ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1265f7325b85SKalle Valo func->num, func->vendor, func->device, 1266f7325b85SKalle Valo func->max_blksize, func->cur_blksize); 1267bdcd8170SKalle Valo 1268bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1269bdcd8170SKalle Valo if (!ar_sdio) 1270bdcd8170SKalle Valo return -ENOMEM; 1271bdcd8170SKalle Valo 1272bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1273bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) { 1274bdcd8170SKalle Valo ret = -ENOMEM; 1275bdcd8170SKalle Valo goto err_hif; 1276bdcd8170SKalle Valo } 1277bdcd8170SKalle Valo 1278bdcd8170SKalle Valo ar_sdio->func = func; 1279bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio); 1280bdcd8170SKalle Valo 1281bdcd8170SKalle Valo ar_sdio->id = id; 1282bdcd8170SKalle Valo ar_sdio->is_disabled = true; 1283bdcd8170SKalle Valo 1284bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock); 1285bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock); 1286bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock); 1287fdb28589SRaja Mani mutex_init(&ar_sdio->dma_buffer_mutex); 12889d82682dSVasanthakumar Thiagarajan mutex_init(&ar_sdio->mtx_irq); 1289bdcd8170SKalle Valo 1290bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req); 1291bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1292bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1293bdcd8170SKalle Valo 1294bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1295bdcd8170SKalle Valo 1296bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1297bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1298bdcd8170SKalle Valo 129945eaa78fSKalle Valo ar = ath6kl_core_create(&ar_sdio->func->dev); 1300bdcd8170SKalle Valo if (!ar) { 1301bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n"); 1302bdcd8170SKalle Valo ret = -ENOMEM; 1303bdcd8170SKalle Valo goto err_dma; 1304bdcd8170SKalle Valo } 1305bdcd8170SKalle Valo 1306bdcd8170SKalle Valo ar_sdio->ar = ar; 130777eab1e9SKalle Valo ar->hif_type = ATH6KL_HIF_TYPE_SDIO; 1308bdcd8170SKalle Valo ar->hif_priv = ar_sdio; 1309bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops; 13101f4c894dSKalle Valo ar->bmi.max_data_size = 256; 1311bdcd8170SKalle Valo 1312bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar); 1313bdcd8170SKalle Valo 1314e28e8104SKalle Valo ret = ath6kl_sdio_config(ar); 1315bdcd8170SKalle Valo if (ret) { 1316e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret); 13178dafb70eSVasanthakumar Thiagarajan goto err_core_alloc; 1318bdcd8170SKalle Valo } 1319bdcd8170SKalle Valo 1320bdcd8170SKalle Valo ret = ath6kl_core_init(ar); 1321bdcd8170SKalle Valo if (ret) { 1322bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n"); 1323e28e8104SKalle Valo goto err_core_alloc; 1324bdcd8170SKalle Valo } 1325bdcd8170SKalle Valo 1326bdcd8170SKalle Valo return ret; 1327bdcd8170SKalle Valo 13288dafb70eSVasanthakumar Thiagarajan err_core_alloc: 132945eaa78fSKalle Valo ath6kl_core_destroy(ar_sdio->ar); 1330bdcd8170SKalle Valo err_dma: 1331bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1332bdcd8170SKalle Valo err_hif: 1333bdcd8170SKalle Valo kfree(ar_sdio); 1334bdcd8170SKalle Valo 1335bdcd8170SKalle Valo return ret; 1336bdcd8170SKalle Valo } 1337bdcd8170SKalle Valo 1338bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func) 1339bdcd8170SKalle Valo { 1340bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1341bdcd8170SKalle Valo 13423ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 13433ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n", 1344f7325b85SKalle Valo func->num, func->vendor, func->device); 1345f7325b85SKalle Valo 1346bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 1347bdcd8170SKalle Valo 1348bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar); 1349bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 1350bdcd8170SKalle Valo 13516db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar); 13520e7de662SVasanthakumar Thiagarajan ath6kl_core_destroy(ar_sdio->ar); 1353bdcd8170SKalle Valo 1354bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1355bdcd8170SKalle Valo kfree(ar_sdio); 1356bdcd8170SKalle Valo } 1357bdcd8170SKalle Valo 1358bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = { 1359bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1360bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1361d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))}, 1362d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, 1363bdcd8170SKalle Valo {}, 1364bdcd8170SKalle Valo }; 1365bdcd8170SKalle Valo 1366bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1367bdcd8170SKalle Valo 1368bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = { 1369241b128bSKalle Valo .name = "ath6kl_sdio", 1370bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices, 1371bdcd8170SKalle Valo .probe = ath6kl_sdio_probe, 1372bdcd8170SKalle Valo .remove = ath6kl_sdio_remove, 1373b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS, 1374bdcd8170SKalle Valo }; 1375bdcd8170SKalle Valo 1376bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void) 1377bdcd8170SKalle Valo { 1378bdcd8170SKalle Valo int ret; 1379bdcd8170SKalle Valo 1380bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver); 1381bdcd8170SKalle Valo if (ret) 1382bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret); 1383bdcd8170SKalle Valo 1384bdcd8170SKalle Valo return ret; 1385bdcd8170SKalle Valo } 1386bdcd8170SKalle Valo 1387bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void) 1388bdcd8170SKalle Valo { 1389bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver); 1390bdcd8170SKalle Valo } 1391bdcd8170SKalle Valo 1392bdcd8170SKalle Valo module_init(ath6kl_sdio_init); 1393bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit); 1394bdcd8170SKalle Valo 1395bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc."); 1396bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1397bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL"); 1398bdcd8170SKalle Valo 1399c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE); 1400c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE); 1401c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE); 14020d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE); 14030d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE); 1404c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE); 1405c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE); 1406c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE); 14070d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE); 14080d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE); 1409c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE); 1410f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE); 1411f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE); 1412c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE); 1413f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE); 1414f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE); 1415