1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 189d9779e7SPaul Gortmaker #include <linux/module.h> 19bdcd8170SKalle Valo #include <linux/mmc/card.h> 20bdcd8170SKalle Valo #include <linux/mmc/mmc.h> 21bdcd8170SKalle Valo #include <linux/mmc/host.h> 22bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h> 24bdcd8170SKalle Valo #include <linux/mmc/sdio.h> 25bdcd8170SKalle Valo #include <linux/mmc/sd.h> 262e1cb23cSKalle Valo #include "hif.h" 27bdcd8170SKalle Valo #include "hif-ops.h" 28bdcd8170SKalle Valo #include "target.h" 29bdcd8170SKalle Valo #include "debug.h" 309df337a1SVivek Natarajan #include "cfg80211.h" 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo struct ath6kl_sdio { 33bdcd8170SKalle Valo struct sdio_func *func; 34bdcd8170SKalle Valo 3512eb9444SKalle Valo /* protects access to bus_req_freeq */ 36bdcd8170SKalle Valo spinlock_t lock; 37bdcd8170SKalle Valo 38bdcd8170SKalle Valo /* free list */ 39bdcd8170SKalle Valo struct list_head bus_req_freeq; 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo /* available bus requests */ 42bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo struct ath6kl *ar; 45fdb28589SRaja Mani 46bdcd8170SKalle Valo u8 *dma_buffer; 47bdcd8170SKalle Valo 48fdb28589SRaja Mani /* protects access to dma_buffer */ 49fdb28589SRaja Mani struct mutex dma_buffer_mutex; 50fdb28589SRaja Mani 51bdcd8170SKalle Valo /* scatter request list head */ 52bdcd8170SKalle Valo struct list_head scat_req; 53bdcd8170SKalle Valo 54d1f41597SRaja Mani atomic_t irq_handling; 55d1f41597SRaja Mani wait_queue_head_t irq_wq; 569d82682dSVasanthakumar Thiagarajan 5712eb9444SKalle Valo /* protects access to scat_req */ 58bdcd8170SKalle Valo spinlock_t scat_lock; 5912eb9444SKalle Valo 6032a07e44SKalle Valo bool scatter_enabled; 6132a07e44SKalle Valo 62bdcd8170SKalle Valo bool is_disabled; 63bdcd8170SKalle Valo const struct sdio_device_id *id; 64bdcd8170SKalle Valo struct work_struct wr_async_work; 65bdcd8170SKalle Valo struct list_head wr_asyncq; 6612eb9444SKalle Valo 6712eb9444SKalle Valo /* protects access to wr_asyncq */ 68bdcd8170SKalle Valo spinlock_t wr_async_lock; 69bdcd8170SKalle Valo }; 70bdcd8170SKalle Valo 71bdcd8170SKalle Valo #define CMD53_ARG_READ 0 72bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1 73bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1 74bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0 75bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1 76bdcd8170SKalle Valo 77bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 78bdcd8170SKalle Valo { 79bdcd8170SKalle Valo return ar->hif_priv; 80bdcd8170SKalle Valo } 81bdcd8170SKalle Valo 82bdcd8170SKalle Valo /* 83bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able. 84bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will 85bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 86bdcd8170SKalle Valo * check fails on stack memory. 87bdcd8170SKalle Valo */ 88bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf) 89bdcd8170SKalle Valo { 90bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 91bdcd8170SKalle Valo } 92bdcd8170SKalle Valo 93bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 94bdcd8170SKalle Valo { 95bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 96bdcd8170SKalle Valo 97bdcd8170SKalle Valo /* EP1 has an extended range */ 98bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 99bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 100bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 101bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 102bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 103bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 104bdcd8170SKalle Valo } 105bdcd8170SKalle Valo 106bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 107bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr, 108bdcd8170SKalle Valo u16 blksz) 109bdcd8170SKalle Valo { 110bdcd8170SKalle Valo *arg = (((rw & 1) << 31) | 111bdcd8170SKalle Valo ((func & 0x7) << 28) | 112bdcd8170SKalle Valo ((mode & 1) << 27) | 113bdcd8170SKalle Valo ((opcode & 1) << 26) | 114bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) | 115bdcd8170SKalle Valo (blksz & 0x1FF)); 116bdcd8170SKalle Valo } 117bdcd8170SKalle Valo 118bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 119bdcd8170SKalle Valo unsigned int address, 120bdcd8170SKalle Valo unsigned char val) 121bdcd8170SKalle Valo { 122bdcd8170SKalle Valo const u8 func = 0; 123bdcd8170SKalle Valo 124bdcd8170SKalle Valo *arg = ((write & 1) << 31) | 125bdcd8170SKalle Valo ((func & 0x7) << 28) | 126bdcd8170SKalle Valo ((raw & 1) << 27) | 127bdcd8170SKalle Valo (1 << 26) | 128bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) | 129bdcd8170SKalle Valo (1 << 8) | 130bdcd8170SKalle Valo (val & 0xFF); 131bdcd8170SKalle Valo } 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 134bdcd8170SKalle Valo unsigned int address, 135bdcd8170SKalle Valo unsigned char byte) 136bdcd8170SKalle Valo { 137bdcd8170SKalle Valo struct mmc_command io_cmd; 138bdcd8170SKalle Valo 139bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd)); 140bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 141bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT; 142bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 143bdcd8170SKalle Valo 144bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0); 145bdcd8170SKalle Valo } 146bdcd8170SKalle Valo 147da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 148da220695SVasanthakumar Thiagarajan u8 *buf, u32 len) 149da220695SVasanthakumar Thiagarajan { 150da220695SVasanthakumar Thiagarajan int ret = 0; 151da220695SVasanthakumar Thiagarajan 152861dd058SVasanthakumar Thiagarajan sdio_claim_host(func); 153861dd058SVasanthakumar Thiagarajan 154da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) { 155f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */ 156da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR && 157da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR) 158da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len); 159da220695SVasanthakumar Thiagarajan 160f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */ 161da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR) 162da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len; 163da220695SVasanthakumar Thiagarajan 164da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 165da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len); 166da220695SVasanthakumar Thiagarajan else 167da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len); 168da220695SVasanthakumar Thiagarajan } else { 169da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 170da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len); 171da220695SVasanthakumar Thiagarajan else 172da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len); 173da220695SVasanthakumar Thiagarajan } 174da220695SVasanthakumar Thiagarajan 175861dd058SVasanthakumar Thiagarajan sdio_release_host(func); 176861dd058SVasanthakumar Thiagarajan 177f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 178f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr, 179f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 180f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 181f7325b85SKalle Valo 182da220695SVasanthakumar Thiagarajan return ret; 183da220695SVasanthakumar Thiagarajan } 184da220695SVasanthakumar Thiagarajan 185bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 186bdcd8170SKalle Valo { 187bdcd8170SKalle Valo struct bus_request *bus_req; 188bdcd8170SKalle Valo 189151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 190bdcd8170SKalle Valo 191bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) { 192151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 193bdcd8170SKalle Valo return NULL; 194bdcd8170SKalle Valo } 195bdcd8170SKalle Valo 196bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 197bdcd8170SKalle Valo struct bus_request, list); 198bdcd8170SKalle Valo list_del(&bus_req->list); 199bdcd8170SKalle Valo 200151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 201f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 202f7325b85SKalle Valo __func__, bus_req); 203bdcd8170SKalle Valo 204bdcd8170SKalle Valo return bus_req; 205bdcd8170SKalle Valo } 206bdcd8170SKalle Valo 207bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 208bdcd8170SKalle Valo struct bus_request *bus_req) 209bdcd8170SKalle Valo { 210f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 211f7325b85SKalle Valo __func__, bus_req); 212bdcd8170SKalle Valo 213151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 214bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 215151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 216bdcd8170SKalle Valo } 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 219bdcd8170SKalle Valo struct mmc_data *data) 220bdcd8170SKalle Valo { 221bdcd8170SKalle Valo struct scatterlist *sg; 222bdcd8170SKalle Valo int i; 223bdcd8170SKalle Valo 224bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE; 225bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 226bdcd8170SKalle Valo 227bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, 228bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 229bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 230bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len, 231bdcd8170SKalle Valo scat_req->scat_entries); 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 234bdcd8170SKalle Valo MMC_DATA_READ; 235bdcd8170SKalle Valo 236bdcd8170SKalle Valo /* fill SG entries */ 237d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries; 238bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries); 239bdcd8170SKalle Valo 240bdcd8170SKalle Valo /* assemble SG list */ 241bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) { 242bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 243bdcd8170SKalle Valo i, scat_req->scat_list[i].buf, 244bdcd8170SKalle Valo scat_req->scat_list[i].len); 245bdcd8170SKalle Valo 246bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf, 247bdcd8170SKalle Valo scat_req->scat_list[i].len); 248bdcd8170SKalle Valo } 249bdcd8170SKalle Valo 250bdcd8170SKalle Valo /* set scatter-gather table for request */ 251d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries; 252bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries; 253bdcd8170SKalle Valo } 254bdcd8170SKalle Valo 255bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 256bdcd8170SKalle Valo struct bus_request *req) 257bdcd8170SKalle Valo { 258bdcd8170SKalle Valo struct mmc_request mmc_req; 259bdcd8170SKalle Valo struct mmc_command cmd; 260bdcd8170SKalle Valo struct mmc_data data; 261bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 262bdcd8170SKalle Valo u8 opcode, rw; 263348a8fbcSVasanthakumar Thiagarajan int status, len; 264bdcd8170SKalle Valo 265bdcd8170SKalle Valo scat_req = req->scat_req; 266bdcd8170SKalle Valo 267348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) { 268348a8fbcSVasanthakumar Thiagarajan len = scat_req->len; 269348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS) 270348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE); 271348a8fbcSVasanthakumar Thiagarajan 272348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 273348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf, 274348a8fbcSVasanthakumar Thiagarajan len); 275348a8fbcSVasanthakumar Thiagarajan goto scat_complete; 276348a8fbcSVasanthakumar Thiagarajan } 277348a8fbcSVasanthakumar Thiagarajan 278bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request)); 279bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command)); 280bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data)); 281bdcd8170SKalle Valo 282d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data); 283bdcd8170SKalle Valo 284bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 285bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 286bdcd8170SKalle Valo 287bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */ 290bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) { 291bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR) 292bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 293bdcd8170SKalle Valo else 294bdcd8170SKalle Valo /* Uses extended address range */ 295bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 296bdcd8170SKalle Valo } 297bdcd8170SKalle Valo 298bdcd8170SKalle Valo /* set command argument */ 299bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 300bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 301bdcd8170SKalle Valo data.blocks); 302bdcd8170SKalle Valo 303bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED; 304bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo mmc_req.cmd = &cmd; 307bdcd8170SKalle Valo mmc_req.data = &data; 308bdcd8170SKalle Valo 309861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func); 310861dd058SVasanthakumar Thiagarajan 311bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card); 312bdcd8170SKalle Valo /* synchronous call to process request */ 313bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 314bdcd8170SKalle Valo 315861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func); 316861dd058SVasanthakumar Thiagarajan 317bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error; 318348a8fbcSVasanthakumar Thiagarajan 319348a8fbcSVasanthakumar Thiagarajan scat_complete: 320bdcd8170SKalle Valo scat_req->status = status; 321bdcd8170SKalle Valo 322bdcd8170SKalle Valo if (scat_req->status) 323bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n", 324bdcd8170SKalle Valo scat_req->status); 325bdcd8170SKalle Valo 326bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS) 327e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req); 328bdcd8170SKalle Valo 329bdcd8170SKalle Valo return status; 330bdcd8170SKalle Valo } 331bdcd8170SKalle Valo 3323df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 3333df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req, 3343df505adSVasanthakumar Thiagarajan bool virt_scat) 3353df505adSVasanthakumar Thiagarajan { 3363df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req; 3373df505adSVasanthakumar Thiagarajan struct bus_request *bus_req; 338cfeab10bSVasanthakumar Thiagarajan int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz; 339cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf; 3403df505adSVasanthakumar Thiagarajan 3413df505adSVasanthakumar Thiagarajan scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 3423df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz; 3433df505adSVasanthakumar Thiagarajan 3443df505adSVasanthakumar Thiagarajan if (!virt_scat) 3453df505adSVasanthakumar Thiagarajan sg_sz = sizeof(struct scatterlist) * n_scat_entry; 346cfeab10bSVasanthakumar Thiagarajan else 347cfeab10bSVasanthakumar Thiagarajan buf_sz = 2 * L1_CACHE_BYTES + 348cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 3493df505adSVasanthakumar Thiagarajan 3503df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) { 3513df505adSVasanthakumar Thiagarajan /* allocate the scatter request */ 3523df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL); 3533df505adSVasanthakumar Thiagarajan if (!s_req) 3543df505adSVasanthakumar Thiagarajan return -ENOMEM; 3553df505adSVasanthakumar Thiagarajan 356cfeab10bSVasanthakumar Thiagarajan if (virt_scat) { 357cfeab10bSVasanthakumar Thiagarajan virt_buf = kzalloc(buf_sz, GFP_KERNEL); 358cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) { 359cfeab10bSVasanthakumar Thiagarajan kfree(s_req); 360cfeab10bSVasanthakumar Thiagarajan return -ENOMEM; 361cfeab10bSVasanthakumar Thiagarajan } 362cfeab10bSVasanthakumar Thiagarajan 363cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf = 364cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 365cfeab10bSVasanthakumar Thiagarajan } else { 3663df505adSVasanthakumar Thiagarajan /* allocate sglist */ 3673df505adSVasanthakumar Thiagarajan s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL); 3683df505adSVasanthakumar Thiagarajan 3693df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) { 3703df505adSVasanthakumar Thiagarajan kfree(s_req); 3713df505adSVasanthakumar Thiagarajan return -ENOMEM; 3723df505adSVasanthakumar Thiagarajan } 3733df505adSVasanthakumar Thiagarajan } 3743df505adSVasanthakumar Thiagarajan 3753df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */ 3763df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 3773df505adSVasanthakumar Thiagarajan if (!bus_req) { 3783df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries); 379cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 3803df505adSVasanthakumar Thiagarajan kfree(s_req); 3813df505adSVasanthakumar Thiagarajan return -ENOMEM; 3823df505adSVasanthakumar Thiagarajan } 3833df505adSVasanthakumar Thiagarajan 3843df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */ 3853df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req; 3863df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req; 3873df505adSVasanthakumar Thiagarajan 3884a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat; 3894a005c3eSVasanthakumar Thiagarajan 3903df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */ 3913df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req); 3923df505adSVasanthakumar Thiagarajan } 3933df505adSVasanthakumar Thiagarajan 3943df505adSVasanthakumar Thiagarajan return 0; 3953df505adSVasanthakumar Thiagarajan } 3963df505adSVasanthakumar Thiagarajan 397bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 398bdcd8170SKalle Valo u32 len, u32 request) 399bdcd8170SKalle Valo { 400bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 401bdcd8170SKalle Valo u8 *tbuf = NULL; 402bdcd8170SKalle Valo int ret; 403bdcd8170SKalle Valo bool bounced = false; 404bdcd8170SKalle Valo 405bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS) 406bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE); 407bdcd8170SKalle Valo 408bdcd8170SKalle Valo if (buf_needs_bounce(buf)) { 409bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) 410bdcd8170SKalle Valo return -ENOMEM; 411fdb28589SRaja Mani mutex_lock(&ar_sdio->dma_buffer_mutex); 412bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer; 413daa16bc5SRaja Mani 414daa16bc5SRaja Mani if (request & HIF_WRITE) 415bdcd8170SKalle Valo memcpy(tbuf, buf, len); 416daa16bc5SRaja Mani 417bdcd8170SKalle Valo bounced = true; 418bdcd8170SKalle Valo } else 419bdcd8170SKalle Valo tbuf = buf; 420bdcd8170SKalle Valo 421da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 422da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced) 423bdcd8170SKalle Valo memcpy(buf, tbuf, len); 424bdcd8170SKalle Valo 425fdb28589SRaja Mani if (bounced) 426fdb28589SRaja Mani mutex_unlock(&ar_sdio->dma_buffer_mutex); 427fdb28589SRaja Mani 428bdcd8170SKalle Valo return ret; 429bdcd8170SKalle Valo } 430bdcd8170SKalle Valo 431bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 432bdcd8170SKalle Valo struct bus_request *req) 433bdcd8170SKalle Valo { 434bdcd8170SKalle Valo if (req->scat_req) 435bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req); 436bdcd8170SKalle Valo else { 437bdcd8170SKalle Valo void *context; 438bdcd8170SKalle Valo int status; 439bdcd8170SKalle Valo 440bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 441bdcd8170SKalle Valo req->buffer, req->length, 442bdcd8170SKalle Valo req->request); 443bdcd8170SKalle Valo context = req->packet; 444bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 4458e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status); 446bdcd8170SKalle Valo } 447bdcd8170SKalle Valo } 448bdcd8170SKalle Valo 449bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work) 450bdcd8170SKalle Valo { 451bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 452bdcd8170SKalle Valo struct bus_request *req, *tmp_req; 453bdcd8170SKalle Valo 454bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 455bdcd8170SKalle Valo 456151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 457bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 458bdcd8170SKalle Valo list_del(&req->list); 459151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 460bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req); 461151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 462bdcd8170SKalle Valo } 463151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 464bdcd8170SKalle Valo } 465bdcd8170SKalle Valo 466bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func) 467bdcd8170SKalle Valo { 468bdcd8170SKalle Valo int status; 469bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 470bdcd8170SKalle Valo 471f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 472f7325b85SKalle Valo 473bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 474d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 1); 475bdcd8170SKalle Valo /* 476bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when 477bdcd8170SKalle Valo * we process commands. 478bdcd8170SKalle Valo */ 479bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 480bdcd8170SKalle Valo 4818e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 482bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 483d1f41597SRaja Mani 484d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 0); 485d1f41597SRaja Mani wake_up(&ar_sdio->irq_wq); 486d1f41597SRaja Mani 487bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED); 488bdcd8170SKalle Valo } 489bdcd8170SKalle Valo 490b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar) 491bdcd8170SKalle Valo { 492b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 493bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func; 494bdcd8170SKalle Valo int ret = 0; 495bdcd8170SKalle Valo 496bdcd8170SKalle Valo if (!ar_sdio->is_disabled) 497bdcd8170SKalle Valo return 0; 498bdcd8170SKalle Valo 4993ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 5003ef987beSKalle Valo 501bdcd8170SKalle Valo sdio_claim_host(func); 502bdcd8170SKalle Valo 503bdcd8170SKalle Valo ret = sdio_enable_func(func); 504bdcd8170SKalle Valo if (ret) { 505bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret); 506bdcd8170SKalle Valo sdio_release_host(func); 507bdcd8170SKalle Valo return ret; 508bdcd8170SKalle Valo } 509bdcd8170SKalle Valo 510bdcd8170SKalle Valo sdio_release_host(func); 511bdcd8170SKalle Valo 512bdcd8170SKalle Valo /* 513bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than 514bdcd8170SKalle Valo * 10 ms but let's be conservative here. 515bdcd8170SKalle Valo */ 516bdcd8170SKalle Valo msleep(10); 517bdcd8170SKalle Valo 518bdcd8170SKalle Valo ar_sdio->is_disabled = false; 519bdcd8170SKalle Valo 520bdcd8170SKalle Valo return ret; 521bdcd8170SKalle Valo } 522bdcd8170SKalle Valo 523b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar) 524bdcd8170SKalle Valo { 525b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 526bdcd8170SKalle Valo int ret; 527bdcd8170SKalle Valo 528bdcd8170SKalle Valo if (ar_sdio->is_disabled) 529bdcd8170SKalle Valo return 0; 530bdcd8170SKalle Valo 5313ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 5323ef987beSKalle Valo 533bdcd8170SKalle Valo /* Disable the card */ 534bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 535bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func); 536bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 537bdcd8170SKalle Valo 538bdcd8170SKalle Valo if (ret) 539bdcd8170SKalle Valo return ret; 540bdcd8170SKalle Valo 541bdcd8170SKalle Valo ar_sdio->is_disabled = true; 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo return ret; 544bdcd8170SKalle Valo } 545bdcd8170SKalle Valo 546bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 547bdcd8170SKalle Valo u32 length, u32 request, 548bdcd8170SKalle Valo struct htc_packet *packet) 549bdcd8170SKalle Valo { 550bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 551bdcd8170SKalle Valo struct bus_request *bus_req; 552bdcd8170SKalle Valo 553bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 554bdcd8170SKalle Valo 55593b42caeSVasanthakumar Thiagarajan if (WARN_ON_ONCE(!bus_req)) 556bdcd8170SKalle Valo return -ENOMEM; 557bdcd8170SKalle Valo 558bdcd8170SKalle Valo bus_req->address = address; 559bdcd8170SKalle Valo bus_req->buffer = buffer; 560bdcd8170SKalle Valo bus_req->length = length; 561bdcd8170SKalle Valo bus_req->request = request; 562bdcd8170SKalle Valo bus_req->packet = packet; 563bdcd8170SKalle Valo 564151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 565bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 566151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 567bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 568bdcd8170SKalle Valo 569bdcd8170SKalle Valo return 0; 570bdcd8170SKalle Valo } 571bdcd8170SKalle Valo 572bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 573bdcd8170SKalle Valo { 574bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 575bdcd8170SKalle Valo int ret; 576bdcd8170SKalle Valo 577bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 578bdcd8170SKalle Valo 579bdcd8170SKalle Valo /* Register the isr */ 580bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 581bdcd8170SKalle Valo if (ret) 582bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret); 583bdcd8170SKalle Valo 584bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 585bdcd8170SKalle Valo } 586bdcd8170SKalle Valo 587d1f41597SRaja Mani static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar) 588d1f41597SRaja Mani { 589d1f41597SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 590d1f41597SRaja Mani 591d1f41597SRaja Mani return !atomic_read(&ar_sdio->irq_handling); 592d1f41597SRaja Mani } 593d1f41597SRaja Mani 594bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 595bdcd8170SKalle Valo { 596bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 597bdcd8170SKalle Valo int ret; 598bdcd8170SKalle Valo 599bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 600bdcd8170SKalle Valo 601d1f41597SRaja Mani if (atomic_read(&ar_sdio->irq_handling)) { 602d1f41597SRaja Mani sdio_release_host(ar_sdio->func); 603d1f41597SRaja Mani 604d1f41597SRaja Mani ret = wait_event_interruptible(ar_sdio->irq_wq, 605d1f41597SRaja Mani ath6kl_sdio_is_on_irq(ar)); 606d1f41597SRaja Mani if (ret) 607d1f41597SRaja Mani return; 608d1f41597SRaja Mani 609d1f41597SRaja Mani sdio_claim_host(ar_sdio->func); 610d1f41597SRaja Mani } 611bdcd8170SKalle Valo 612bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func); 613bdcd8170SKalle Valo if (ret) 614bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret); 615bdcd8170SKalle Valo 616bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 617bdcd8170SKalle Valo } 618bdcd8170SKalle Valo 619bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 620bdcd8170SKalle Valo { 621bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 622bdcd8170SKalle Valo struct hif_scatter_req *node = NULL; 623bdcd8170SKalle Valo 624151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 625bdcd8170SKalle Valo 626bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) { 627bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req, 628bdcd8170SKalle Valo struct hif_scatter_req, list); 629bdcd8170SKalle Valo list_del(&node->list); 630b29072ccSChilam Ng 631b29072ccSChilam Ng node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req); 632bdcd8170SKalle Valo } 633bdcd8170SKalle Valo 634151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 635bdcd8170SKalle Valo 636bdcd8170SKalle Valo return node; 637bdcd8170SKalle Valo } 638bdcd8170SKalle Valo 639bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 640bdcd8170SKalle Valo struct hif_scatter_req *s_req) 641bdcd8170SKalle Valo { 642bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 643bdcd8170SKalle Valo 644151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 645bdcd8170SKalle Valo 646bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req); 647bdcd8170SKalle Valo 648151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 649bdcd8170SKalle Valo 650bdcd8170SKalle Valo } 651bdcd8170SKalle Valo 652c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */ 653c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 654c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req) 655c630d18aSVasanthakumar Thiagarajan { 656c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 657c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req; 658c630d18aSVasanthakumar Thiagarajan int status = 0; 659c630d18aSVasanthakumar Thiagarajan 660c630d18aSVasanthakumar Thiagarajan if (!scat_req->len) 661c630d18aSVasanthakumar Thiagarajan return -EINVAL; 662c630d18aSVasanthakumar Thiagarajan 663c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER, 664c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n", 665c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries); 666c630d18aSVasanthakumar Thiagarajan 667861dd058SVasanthakumar Thiagarajan if (request & HIF_SYNCHRONOUS) 668d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 669861dd058SVasanthakumar Thiagarajan else { 670151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 671d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 672151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 673c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 674c630d18aSVasanthakumar Thiagarajan } 675c630d18aSVasanthakumar Thiagarajan 676c630d18aSVasanthakumar Thiagarajan return status; 677c630d18aSVasanthakumar Thiagarajan } 678c630d18aSVasanthakumar Thiagarajan 67918a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */ 68018a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 68118a0f93eSVasanthakumar Thiagarajan { 68218a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 68318a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req; 68418a0f93eSVasanthakumar Thiagarajan 68518a0f93eSVasanthakumar Thiagarajan /* empty the free list */ 686151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 68718a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 68818a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list); 689151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 69018a0f93eSVasanthakumar Thiagarajan 69132a07e44SKalle Valo /* 69232a07e44SKalle Valo * FIXME: should we also call completion handler with 69332a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 69432a07e44SKalle Valo * that the packet is properly freed? 69532a07e44SKalle Valo */ 69618a0f93eSVasanthakumar Thiagarajan if (s_req->busrequest) 69718a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 69818a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 69918a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries); 70018a0f93eSVasanthakumar Thiagarajan kfree(s_req); 70118a0f93eSVasanthakumar Thiagarajan 702151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 70318a0f93eSVasanthakumar Thiagarajan } 704151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 70518a0f93eSVasanthakumar Thiagarajan } 70618a0f93eSVasanthakumar Thiagarajan 70718a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */ 70850745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 70918a0f93eSVasanthakumar Thiagarajan { 71018a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 71150745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target; 712527f6570SAndi Kleen int ret = 0; 713cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false; 71418a0f93eSVasanthakumar Thiagarajan 71532a07e44SKalle Valo if (ar_sdio->scatter_enabled) 71632a07e44SKalle Valo return 0; 71732a07e44SKalle Valo 71832a07e44SKalle Valo ar_sdio->scatter_enabled = true; 71932a07e44SKalle Valo 72018a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */ 72118a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 722cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 72318a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs, 72418a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 725cfeab10bSVasanthakumar Thiagarajan virt_scat = true; 72618a0f93eSVasanthakumar Thiagarajan } 72718a0f93eSVasanthakumar Thiagarajan 728cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) { 72918a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 73018a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ, 731cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat); 732cfeab10bSVasanthakumar Thiagarajan 733cfeab10bSVasanthakumar Thiagarajan if (!ret) { 7343ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7353ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n", 736cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, 737cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 738cfeab10bSVasanthakumar Thiagarajan 73950745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 74050745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 741cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE; 742cfeab10bSVasanthakumar Thiagarajan } else { 743cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 744cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 745cfeab10bSVasanthakumar Thiagarajan } 746cfeab10bSVasanthakumar Thiagarajan } 747cfeab10bSVasanthakumar Thiagarajan 748cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) { 749cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 750cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ, 751cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat); 752cfeab10bSVasanthakumar Thiagarajan 75318a0f93eSVasanthakumar Thiagarajan if (ret) { 754cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n"); 75518a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 75618a0f93eSVasanthakumar Thiagarajan return ret; 75718a0f93eSVasanthakumar Thiagarajan } 75818a0f93eSVasanthakumar Thiagarajan 7593ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7603ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n", 761cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 762cfeab10bSVasanthakumar Thiagarajan 76350745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 76450745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 765cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 766cfeab10bSVasanthakumar Thiagarajan } 767cfeab10bSVasanthakumar Thiagarajan 76818a0f93eSVasanthakumar Thiagarajan return 0; 76918a0f93eSVasanthakumar Thiagarajan } 77018a0f93eSVasanthakumar Thiagarajan 771e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar) 772e28e8104SKalle Valo { 773e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 774e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func; 775e28e8104SKalle Valo int ret; 776e28e8104SKalle Valo 777e28e8104SKalle Valo sdio_claim_host(func); 778e28e8104SKalle Valo 779e28e8104SKalle Valo if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 780e28e8104SKalle Valo MANUFACTURER_ID_AR6003_BASE) { 781e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */ 782e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 783e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG, 784e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 785e28e8104SKalle Valo if (ret) { 786e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 787e28e8104SKalle Valo ret); 788e28e8104SKalle Valo goto out; 789e28e8104SKalle Valo } 790e28e8104SKalle Valo 791e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 792e28e8104SKalle Valo } 793e28e8104SKalle Valo 794e28e8104SKalle Valo /* give us some time to enable, in ms */ 795e28e8104SKalle Valo func->enable_timeout = 100; 796e28e8104SKalle Valo 797e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 798e28e8104SKalle Valo if (ret) { 799e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n", 800e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret); 801e28e8104SKalle Valo goto out; 802e28e8104SKalle Valo } 803e28e8104SKalle Valo 804e28e8104SKalle Valo out: 805e28e8104SKalle Valo sdio_release_host(func); 806e28e8104SKalle Valo 807e28e8104SKalle Valo return ret; 808e28e8104SKalle Valo } 809e28e8104SKalle Valo 810e390af77SRaja Mani static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar) 811abcb344bSKalle Valo { 812abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 813abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func; 814abcb344bSKalle Valo mmc_pm_flag_t flags; 815abcb344bSKalle Valo int ret; 816abcb344bSKalle Valo 817abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func); 818abcb344bSKalle Valo 819b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 820b4b2a0b1SKalle Valo 821e390af77SRaja Mani if (!(flags & MMC_PM_WAKE_SDIO_IRQ) || 822e390af77SRaja Mani !(flags & MMC_PM_KEEP_POWER)) 823e390af77SRaja Mani return -EINVAL; 824abcb344bSKalle Valo 825abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 826abcb344bSKalle Valo if (ret) { 827e390af77SRaja Mani ath6kl_err("set sdio keep pwr flag failed: %d\n", ret); 828abcb344bSKalle Valo return ret; 829abcb344bSKalle Valo } 830abcb344bSKalle Valo 83110509f90SKalle Valo /* sdio irq wakes up host */ 832d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 833d7c44e0bSRaja Mani if (ret) 834d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 835d7c44e0bSRaja Mani 836d7c44e0bSRaja Mani return ret; 837d7c44e0bSRaja Mani } 838d7c44e0bSRaja Mani 839e390af77SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 840e390af77SRaja Mani { 841e390af77SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 842e390af77SRaja Mani struct sdio_func *func = ar_sdio->func; 843e390af77SRaja Mani mmc_pm_flag_t flags; 8441e9a905dSRaja Mani bool try_deepsleep = false; 845e390af77SRaja Mani int ret; 846e390af77SRaja Mani 847e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_WOW || 848e390af77SRaja Mani (!ar->suspend_mode && wow)) { 849e390af77SRaja Mani 850e390af77SRaja Mani ret = ath6kl_set_sdio_pm_caps(ar); 851e390af77SRaja Mani if (ret) 852e390af77SRaja Mani goto cut_pwr; 853e390af77SRaja Mani 854e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 8551e9a905dSRaja Mani if (ret && ret != -ENOTCONN) 8561e9a905dSRaja Mani ath6kl_err("wow suspend failed: %d\n", ret); 857e390af77SRaja Mani 8587433a490SKalle Valo if (ret && 8597433a490SKalle Valo (!ar->wow_suspend_mode || 8601e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP)) 8611e9a905dSRaja Mani try_deepsleep = true; 8621e9a905dSRaja Mani else if (ret && 8631e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR) 8641e9a905dSRaja Mani goto cut_pwr; 8651e9a905dSRaja Mani if (!ret) 866e390af77SRaja Mani return 0; 867e390af77SRaja Mani } 868e390af77SRaja Mani 869e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP || 8701e9a905dSRaja Mani !ar->suspend_mode || try_deepsleep) { 871e390af77SRaja Mani 872e390af77SRaja Mani flags = sdio_get_host_pm_caps(func); 873e390af77SRaja Mani if (!(flags & MMC_PM_KEEP_POWER)) 874e390af77SRaja Mani goto cut_pwr; 875e390af77SRaja Mani 876e390af77SRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 877e390af77SRaja Mani if (ret) 878e390af77SRaja Mani goto cut_pwr; 879e390af77SRaja Mani 880cca4d5adSSantosh Sajjan /* 881cca4d5adSSantosh Sajjan * Workaround to support Deep Sleep with MSM, set the host pm 882cca4d5adSSantosh Sajjan * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable 883cca4d5adSSantosh Sajjan * the sdc2_clock and internally allows MSM to enter 884cca4d5adSSantosh Sajjan * TCXO shutdown properly. 885cca4d5adSSantosh Sajjan */ 886cca4d5adSSantosh Sajjan if ((flags & MMC_PM_WAKE_SDIO_IRQ)) { 887cca4d5adSSantosh Sajjan ret = sdio_set_host_pm_flags(func, 888cca4d5adSSantosh Sajjan MMC_PM_WAKE_SDIO_IRQ); 889cca4d5adSSantosh Sajjan if (ret) 890cca4d5adSSantosh Sajjan goto cut_pwr; 891cca4d5adSSantosh Sajjan } 892cca4d5adSSantosh Sajjan 893e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, 894e390af77SRaja Mani NULL); 895e390af77SRaja Mani if (ret) 896e390af77SRaja Mani goto cut_pwr; 897e390af77SRaja Mani 898e390af77SRaja Mani return 0; 899e390af77SRaja Mani } 900e390af77SRaja Mani 901e390af77SRaja Mani cut_pwr: 9025699257fSMing Jiang if (func->card && func->card->host) 9035699257fSMing Jiang func->card->host->pm_flags &= ~MMC_PM_KEEP_POWER; 9045699257fSMing Jiang 905e390af77SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL); 906abcb344bSKalle Valo } 907abcb344bSKalle Valo 908aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar) 909aa6cffc1SChilam Ng { 910b4b2a0b1SKalle Valo switch (ar->state) { 911b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF: 912b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER: 913b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, 914b4b2a0b1SKalle Valo "sdio resume configuring sdio\n"); 915b4b2a0b1SKalle Valo 916b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */ 917b4b2a0b1SKalle Valo ath6kl_sdio_config(ar); 918b4b2a0b1SKalle Valo break; 919b4b2a0b1SKalle Valo 920b4b2a0b1SKalle Valo case ATH6KL_STATE_ON: 921b4b2a0b1SKalle Valo break; 922b4b2a0b1SKalle Valo 923b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP: 924b4b2a0b1SKalle Valo break; 925d7c44e0bSRaja Mani 926d7c44e0bSRaja Mani case ATH6KL_STATE_WOW: 927d7c44e0bSRaja Mani break; 928390a8c8fSRaja Mani 929390a8c8fSRaja Mani case ATH6KL_STATE_SUSPENDING: 930390a8c8fSRaja Mani break; 931390a8c8fSRaja Mani 932390a8c8fSRaja Mani case ATH6KL_STATE_RESUMING: 933390a8c8fSRaja Mani break; 93484caf800SVasanthakumar Thiagarajan 93584caf800SVasanthakumar Thiagarajan case ATH6KL_STATE_RECOVERY: 93684caf800SVasanthakumar Thiagarajan break; 937b4b2a0b1SKalle Valo } 938b4b2a0b1SKalle Valo 93952d81a68SKalle Valo ath6kl_cfg80211_resume(ar); 940aa6cffc1SChilam Ng 941aa6cffc1SChilam Ng return 0; 942aa6cffc1SChilam Ng } 943aa6cffc1SChilam Ng 944c7111495SKalle Valo /* set the window address register (using 4-byte register access ). */ 945c7111495SKalle Valo static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr) 946c7111495SKalle Valo { 947c7111495SKalle Valo int status; 948c7111495SKalle Valo u8 addr_val[4]; 949c7111495SKalle Valo s32 i; 950c7111495SKalle Valo 951c7111495SKalle Valo /* 952c7111495SKalle Valo * Write bytes 1,2,3 of the register to set the upper address bytes, 953c7111495SKalle Valo * the LSB is written last to initiate the access cycle 954c7111495SKalle Valo */ 955c7111495SKalle Valo 956c7111495SKalle Valo for (i = 1; i <= 3; i++) { 957c7111495SKalle Valo /* 958c7111495SKalle Valo * Fill the buffer with the address byte value we want to 959c7111495SKalle Valo * hit 4 times. 960c7111495SKalle Valo */ 961c7111495SKalle Valo memset(addr_val, ((u8 *)&addr)[i], 4); 962c7111495SKalle Valo 963c7111495SKalle Valo /* 964c7111495SKalle Valo * Hit each byte of the register address with a 4-byte 965c7111495SKalle Valo * write operation to the same address, this is a harmless 966c7111495SKalle Valo * operation. 967c7111495SKalle Valo */ 968c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val, 969c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_FIX); 970c7111495SKalle Valo if (status) 971c7111495SKalle Valo break; 972c7111495SKalle Valo } 973c7111495SKalle Valo 974c7111495SKalle Valo if (status) { 975cdeb8602SKalle Valo ath6kl_err("%s: failed to write initial bytes of 0x%x to window reg: 0x%X\n", 976cdeb8602SKalle Valo __func__, addr, reg_addr); 977c7111495SKalle Valo return status; 978c7111495SKalle Valo } 979c7111495SKalle Valo 980c7111495SKalle Valo /* 981c7111495SKalle Valo * Write the address register again, this time write the whole 982c7111495SKalle Valo * 4-byte value. The effect here is that the LSB write causes the 983c7111495SKalle Valo * cycle to start, the extra 3 byte write to bytes 1,2,3 has no 984c7111495SKalle Valo * effect since we are writing the same values again 985c7111495SKalle Valo */ 986c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr), 987c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_INC); 988c7111495SKalle Valo 989c7111495SKalle Valo if (status) { 990c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n", 991c7111495SKalle Valo __func__, addr, reg_addr); 992c7111495SKalle Valo return status; 993c7111495SKalle Valo } 994c7111495SKalle Valo 995c7111495SKalle Valo return 0; 996c7111495SKalle Valo } 997c7111495SKalle Valo 998c7111495SKalle Valo static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data) 999c7111495SKalle Valo { 1000c7111495SKalle Valo int status; 1001c7111495SKalle Valo 1002c7111495SKalle Valo /* set window register to start read cycle */ 1003c7111495SKalle Valo status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS, 1004c7111495SKalle Valo address); 1005c7111495SKalle Valo 1006c7111495SKalle Valo if (status) 1007c7111495SKalle Valo return status; 1008c7111495SKalle Valo 1009c7111495SKalle Valo /* read the data */ 1010c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1011c7111495SKalle Valo (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC); 1012c7111495SKalle Valo if (status) { 1013c7111495SKalle Valo ath6kl_err("%s: failed to read from window data addr\n", 1014c7111495SKalle Valo __func__); 1015c7111495SKalle Valo return status; 1016c7111495SKalle Valo } 1017c7111495SKalle Valo 1018c7111495SKalle Valo return status; 1019c7111495SKalle Valo } 1020c7111495SKalle Valo 1021c7111495SKalle Valo static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address, 1022c7111495SKalle Valo __le32 data) 1023c7111495SKalle Valo { 1024c7111495SKalle Valo int status; 1025c7111495SKalle Valo u32 val = (__force u32) data; 1026c7111495SKalle Valo 1027c7111495SKalle Valo /* set write data */ 1028c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1029c7111495SKalle Valo (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); 1030c7111495SKalle Valo if (status) { 1031c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window data addr\n", 1032c7111495SKalle Valo __func__, data); 1033c7111495SKalle Valo return status; 1034c7111495SKalle Valo } 1035c7111495SKalle Valo 1036c7111495SKalle Valo /* set window register, which starts the write cycle */ 1037c7111495SKalle Valo return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS, 1038c7111495SKalle Valo address); 1039c7111495SKalle Valo } 1040c7111495SKalle Valo 104166b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 104266b693c3SKalle Valo { 104366b693c3SKalle Valo u32 addr; 104466b693c3SKalle Valo unsigned long timeout; 104566b693c3SKalle Valo int ret; 104666b693c3SKalle Valo 104766b693c3SKalle Valo ar->bmi.cmd_credits = 0; 104866b693c3SKalle Valo 104966b693c3SKalle Valo /* Read the counter register to get the command credits */ 105066b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 105166b693c3SKalle Valo 105266b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 105366b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 105466b693c3SKalle Valo 105566b693c3SKalle Valo /* 105666b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte 105766b693c3SKalle Valo * read will hit the counter and cause a decrement, while the 105866b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this 105966b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned. 106066b693c3SKalle Valo */ 106166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, 106266b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4, 106366b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 106466b693c3SKalle Valo if (ret) { 1065cdeb8602SKalle Valo ath6kl_err("Unable to decrement the command credit count register: %d\n", 1066cdeb8602SKalle Valo ret); 106766b693c3SKalle Valo return ret; 106866b693c3SKalle Valo } 106966b693c3SKalle Valo 107066b693c3SKalle Valo /* The counter is only 8 bits. 107166b693c3SKalle Valo * Ignore anything in the upper 3 bytes 107266b693c3SKalle Valo */ 107366b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF; 107466b693c3SKalle Valo } 107566b693c3SKalle Valo 107666b693c3SKalle Valo if (!ar->bmi.cmd_credits) { 107766b693c3SKalle Valo ath6kl_err("bmi communication timeout\n"); 107866b693c3SKalle Valo return -ETIMEDOUT; 107966b693c3SKalle Valo } 108066b693c3SKalle Valo 108166b693c3SKalle Valo return 0; 108266b693c3SKalle Valo } 108366b693c3SKalle Valo 108466b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 108566b693c3SKalle Valo { 108666b693c3SKalle Valo unsigned long timeout; 108766b693c3SKalle Valo u32 rx_word = 0; 108866b693c3SKalle Valo int ret = 0; 108966b693c3SKalle Valo 109066b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 109166b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) { 109266b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, 109366b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS, 109466b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word), 109566b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 109666b693c3SKalle Valo if (ret) { 109766b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 109866b693c3SKalle Valo return ret; 109966b693c3SKalle Valo } 110066b693c3SKalle Valo 110166b693c3SKalle Valo /* all we really want is one bit */ 110266b693c3SKalle Valo rx_word &= (1 << ENDPOINT1); 110366b693c3SKalle Valo } 110466b693c3SKalle Valo 110566b693c3SKalle Valo if (!rx_word) { 110666b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n"); 110766b693c3SKalle Valo return -EINVAL; 110866b693c3SKalle Valo } 110966b693c3SKalle Valo 111066b693c3SKalle Valo return ret; 111166b693c3SKalle Valo } 111266b693c3SKalle Valo 111366b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 111466b693c3SKalle Valo { 111566b693c3SKalle Valo int ret; 111666b693c3SKalle Valo u32 addr; 111766b693c3SKalle Valo 111866b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar); 111966b693c3SKalle Valo if (ret) 112066b693c3SKalle Valo return ret; 112166b693c3SKalle Valo 112266b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 112366b693c3SKalle Valo 112466b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 112566b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC); 112666b693c3SKalle Valo if (ret) 112766b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n"); 112866b693c3SKalle Valo 112966b693c3SKalle Valo return ret; 113066b693c3SKalle Valo } 113166b693c3SKalle Valo 113266b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 113366b693c3SKalle Valo { 113466b693c3SKalle Valo int ret; 113566b693c3SKalle Valo u32 addr; 113666b693c3SKalle Valo 113766b693c3SKalle Valo /* 113866b693c3SKalle Valo * During normal bootup, small reads may be required. 113966b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target 114066b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until 114166b693c3SKalle Valo * we know that response data is available. 114266b693c3SKalle Valo * 114366b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected 114466b693c3SKalle Valo * Target failure rather than risk problems at the HIF level. 114566b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage 114666b693c3SKalle Valo * data on some host controllers. And on an interconnect 114766b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which 114866b693c3SKalle Valo * does not provide any indication on data timeout, it avoids 114966b693c3SKalle Valo * a potential hang or garbage response. 115066b693c3SKalle Valo * 115166b693c3SKalle Valo * Synchronization is more difficult for reads larger than the 115266b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable 115366b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an 115466b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the 115566b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is 115666b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do 115766b693c3SKalle Valo * not occur in practice -- they're supported for debug/development. 115866b693c3SKalle Valo * 115966b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases: 116066b693c3SKalle Valo * CASE 1: length < 4 116166b693c3SKalle Valo * Should not happen 116266b693c3SKalle Valo * 116366b693c3SKalle Valo * CASE 2: 4 <= length <= 128 116466b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO 116566b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for 116666b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE 116766b693c3SKalle Valo * response is available in the the FIFO 116866b693c3SKalle Valo * 116966b693c3SKalle Valo * CASE 3: length > 128 117066b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO 117166b693c3SKalle Valo * 117266b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will 117366b693c3SKalle Valo * usually see a response quickly; but there may be some unusual 117466b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout. 117566b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for 117666b693c3SKalle Valo * BMI_EXECUTE. 117766b693c3SKalle Valo * 117866b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution, 117966b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep 118066b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 118166b693c3SKalle Valo * a function of Host processor speed. 118266b693c3SKalle Valo */ 118366b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */ 118466b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar); 118566b693c3SKalle Valo if (ret) 118666b693c3SKalle Valo return ret; 118766b693c3SKalle Valo } 118866b693c3SKalle Valo 118966b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 119066b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 119166b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 119266b693c3SKalle Valo if (ret) { 119366b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n", 119466b693c3SKalle Valo ret); 119566b693c3SKalle Valo return ret; 119666b693c3SKalle Valo } 119766b693c3SKalle Valo 119866b693c3SKalle Valo return 0; 119966b693c3SKalle Valo } 120066b693c3SKalle Valo 120132a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar) 120232a07e44SKalle Valo { 120332a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 120432a07e44SKalle Valo struct bus_request *req, *tmp_req; 120532a07e44SKalle Valo void *context; 120632a07e44SKalle Valo 120732a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */ 120832a07e44SKalle Valo 120932a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 121032a07e44SKalle Valo 121132a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock); 121232a07e44SKalle Valo 121332a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 121432a07e44SKalle Valo list_del(&req->list); 121532a07e44SKalle Valo 121632a07e44SKalle Valo if (req->scat_req) { 121732a07e44SKalle Valo /* this is a scatter gather request */ 121832a07e44SKalle Valo req->scat_req->status = -ECANCELED; 121932a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target, 122032a07e44SKalle Valo req->scat_req); 122132a07e44SKalle Valo } else { 122232a07e44SKalle Valo context = req->packet; 122332a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 122432a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED); 122532a07e44SKalle Valo } 122632a07e44SKalle Valo } 122732a07e44SKalle Valo 122832a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock); 122932a07e44SKalle Valo 123032a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 123132a07e44SKalle Valo } 123232a07e44SKalle Valo 1233bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1234bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync, 1235bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async, 1236bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable, 1237bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable, 1238bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get, 1239bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add, 1240bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter, 1241f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1242bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1243abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend, 1244aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume, 1245c7111495SKalle Valo .diag_read32 = ath6kl_sdio_diag_read32, 1246c7111495SKalle Valo .diag_write32 = ath6kl_sdio_diag_write32, 124766b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read, 124866b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write, 1249b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on, 1250b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off, 125132a07e44SKalle Valo .stop = ath6kl_sdio_stop, 1252bdcd8170SKalle Valo }; 1253bdcd8170SKalle Valo 1254b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP 1255b4b2a0b1SKalle Valo 1256b4b2a0b1SKalle Valo /* 1257b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during 1258b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers. 1259b4b2a0b1SKalle Valo */ 1260b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device) 1261b4b2a0b1SKalle Valo { 1262b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1263b4b2a0b1SKalle Valo 1264b4b2a0b1SKalle Valo return 0; 1265b4b2a0b1SKalle Valo } 1266b4b2a0b1SKalle Valo 1267b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device) 1268b4b2a0b1SKalle Valo { 1269b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1270b4b2a0b1SKalle Valo 1271b4b2a0b1SKalle Valo return 0; 1272b4b2a0b1SKalle Valo } 1273b4b2a0b1SKalle Valo 1274b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1275b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume); 1276b4b2a0b1SKalle Valo 1277b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1278b4b2a0b1SKalle Valo 1279b4b2a0b1SKalle Valo #else 1280b4b2a0b1SKalle Valo 1281b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL 1282b4b2a0b1SKalle Valo 1283b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */ 1284b4b2a0b1SKalle Valo 1285bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func, 1286bdcd8170SKalle Valo const struct sdio_device_id *id) 1287bdcd8170SKalle Valo { 1288bdcd8170SKalle Valo int ret; 1289bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1290bdcd8170SKalle Valo struct ath6kl *ar; 1291bdcd8170SKalle Valo int count; 1292bdcd8170SKalle Valo 12933ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 12943ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1295f7325b85SKalle Valo func->num, func->vendor, func->device, 1296f7325b85SKalle Valo func->max_blksize, func->cur_blksize); 1297bdcd8170SKalle Valo 1298bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1299bdcd8170SKalle Valo if (!ar_sdio) 1300bdcd8170SKalle Valo return -ENOMEM; 1301bdcd8170SKalle Valo 1302bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1303bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) { 1304bdcd8170SKalle Valo ret = -ENOMEM; 1305bdcd8170SKalle Valo goto err_hif; 1306bdcd8170SKalle Valo } 1307bdcd8170SKalle Valo 1308bdcd8170SKalle Valo ar_sdio->func = func; 1309bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio); 1310bdcd8170SKalle Valo 1311bdcd8170SKalle Valo ar_sdio->id = id; 1312bdcd8170SKalle Valo ar_sdio->is_disabled = true; 1313bdcd8170SKalle Valo 1314bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock); 1315bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock); 1316bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock); 1317fdb28589SRaja Mani mutex_init(&ar_sdio->dma_buffer_mutex); 1318bdcd8170SKalle Valo 1319bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req); 1320bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1321bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1322bdcd8170SKalle Valo 1323bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1324bdcd8170SKalle Valo 1325d1f41597SRaja Mani init_waitqueue_head(&ar_sdio->irq_wq); 1326d1f41597SRaja Mani 1327bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1328bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1329bdcd8170SKalle Valo 133045eaa78fSKalle Valo ar = ath6kl_core_create(&ar_sdio->func->dev); 1331bdcd8170SKalle Valo if (!ar) { 1332bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n"); 1333bdcd8170SKalle Valo ret = -ENOMEM; 1334bdcd8170SKalle Valo goto err_dma; 1335bdcd8170SKalle Valo } 1336bdcd8170SKalle Valo 1337bdcd8170SKalle Valo ar_sdio->ar = ar; 133877eab1e9SKalle Valo ar->hif_type = ATH6KL_HIF_TYPE_SDIO; 1339bdcd8170SKalle Valo ar->hif_priv = ar_sdio; 1340bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops; 13411f4c894dSKalle Valo ar->bmi.max_data_size = 256; 1342bdcd8170SKalle Valo 1343bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar); 1344bdcd8170SKalle Valo 1345e28e8104SKalle Valo ret = ath6kl_sdio_config(ar); 1346bdcd8170SKalle Valo if (ret) { 1347e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret); 13488dafb70eSVasanthakumar Thiagarajan goto err_core_alloc; 1349bdcd8170SKalle Valo } 1350bdcd8170SKalle Valo 1351e76ac2bfSKalle Valo ret = ath6kl_core_init(ar, ATH6KL_HTC_TYPE_MBOX); 1352bdcd8170SKalle Valo if (ret) { 1353bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n"); 1354e28e8104SKalle Valo goto err_core_alloc; 1355bdcd8170SKalle Valo } 1356bdcd8170SKalle Valo 1357bdcd8170SKalle Valo return ret; 1358bdcd8170SKalle Valo 13598dafb70eSVasanthakumar Thiagarajan err_core_alloc: 136045eaa78fSKalle Valo ath6kl_core_destroy(ar_sdio->ar); 1361bdcd8170SKalle Valo err_dma: 1362bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1363bdcd8170SKalle Valo err_hif: 1364bdcd8170SKalle Valo kfree(ar_sdio); 1365bdcd8170SKalle Valo 1366bdcd8170SKalle Valo return ret; 1367bdcd8170SKalle Valo } 1368bdcd8170SKalle Valo 1369bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func) 1370bdcd8170SKalle Valo { 1371bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1372bdcd8170SKalle Valo 13733ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 13743ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n", 1375f7325b85SKalle Valo func->num, func->vendor, func->device); 1376f7325b85SKalle Valo 1377bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 1378bdcd8170SKalle Valo 1379bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar); 1380bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 1381bdcd8170SKalle Valo 13826db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar); 13830e7de662SVasanthakumar Thiagarajan ath6kl_core_destroy(ar_sdio->ar); 1384bdcd8170SKalle Valo 1385bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1386bdcd8170SKalle Valo kfree(ar_sdio); 1387bdcd8170SKalle Valo } 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = { 1390bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1391bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1392d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))}, 1393d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, 1394bdcd8170SKalle Valo {}, 1395bdcd8170SKalle Valo }; 1396bdcd8170SKalle Valo 1397bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1398bdcd8170SKalle Valo 1399bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = { 1400241b128bSKalle Valo .name = "ath6kl_sdio", 1401bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices, 1402bdcd8170SKalle Valo .probe = ath6kl_sdio_probe, 1403bdcd8170SKalle Valo .remove = ath6kl_sdio_remove, 1404b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS, 1405bdcd8170SKalle Valo }; 1406bdcd8170SKalle Valo 1407bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void) 1408bdcd8170SKalle Valo { 1409bdcd8170SKalle Valo int ret; 1410bdcd8170SKalle Valo 1411bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver); 1412bdcd8170SKalle Valo if (ret) 1413bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret); 1414bdcd8170SKalle Valo 1415bdcd8170SKalle Valo return ret; 1416bdcd8170SKalle Valo } 1417bdcd8170SKalle Valo 1418bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void) 1419bdcd8170SKalle Valo { 1420bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver); 1421bdcd8170SKalle Valo } 1422bdcd8170SKalle Valo 1423bdcd8170SKalle Valo module_init(ath6kl_sdio_init); 1424bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit); 1425bdcd8170SKalle Valo 1426bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc."); 1427bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1428bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL"); 1429bdcd8170SKalle Valo 1430c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE); 1431c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE); 1432c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE); 14330d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE); 14340d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE); 1435c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE); 1436c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE); 1437c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE); 14380d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE); 14390d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE); 1440c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE); 1441f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE); 1442f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE); 1443c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE); 1444f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE); 1445f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE); 14466146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_FW_DIR "/" AR6004_HW_1_2_FIRMWARE_FILE); 14476146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_BOARD_DATA_FILE); 14486146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE); 1449bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_FW_DIR "/" AR6004_HW_1_3_FIRMWARE_FILE); 1450bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_BOARD_DATA_FILE); 1451bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE); 1452