1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 189d9779e7SPaul Gortmaker #include <linux/module.h> 19bdcd8170SKalle Valo #include <linux/mmc/card.h> 20bdcd8170SKalle Valo #include <linux/mmc/mmc.h> 21bdcd8170SKalle Valo #include <linux/mmc/host.h> 22bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 23bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h> 24bdcd8170SKalle Valo #include <linux/mmc/sdio.h> 25bdcd8170SKalle Valo #include <linux/mmc/sd.h> 262e1cb23cSKalle Valo #include "hif.h" 27bdcd8170SKalle Valo #include "hif-ops.h" 28bdcd8170SKalle Valo #include "target.h" 29bdcd8170SKalle Valo #include "debug.h" 309df337a1SVivek Natarajan #include "cfg80211.h" 31e60c8154SKalle Valo #include "trace.h" 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo struct ath6kl_sdio { 34bdcd8170SKalle Valo struct sdio_func *func; 35bdcd8170SKalle Valo 3612eb9444SKalle Valo /* protects access to bus_req_freeq */ 37bdcd8170SKalle Valo spinlock_t lock; 38bdcd8170SKalle Valo 39bdcd8170SKalle Valo /* free list */ 40bdcd8170SKalle Valo struct list_head bus_req_freeq; 41bdcd8170SKalle Valo 42bdcd8170SKalle Valo /* available bus requests */ 43bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 44bdcd8170SKalle Valo 45bdcd8170SKalle Valo struct ath6kl *ar; 46fdb28589SRaja Mani 47bdcd8170SKalle Valo u8 *dma_buffer; 48bdcd8170SKalle Valo 49fdb28589SRaja Mani /* protects access to dma_buffer */ 50fdb28589SRaja Mani struct mutex dma_buffer_mutex; 51fdb28589SRaja Mani 52bdcd8170SKalle Valo /* scatter request list head */ 53bdcd8170SKalle Valo struct list_head scat_req; 54bdcd8170SKalle Valo 55d1f41597SRaja Mani atomic_t irq_handling; 56d1f41597SRaja Mani wait_queue_head_t irq_wq; 579d82682dSVasanthakumar Thiagarajan 5812eb9444SKalle Valo /* protects access to scat_req */ 59bdcd8170SKalle Valo spinlock_t scat_lock; 6012eb9444SKalle Valo 6132a07e44SKalle Valo bool scatter_enabled; 6232a07e44SKalle Valo 63bdcd8170SKalle Valo bool is_disabled; 64bdcd8170SKalle Valo const struct sdio_device_id *id; 65bdcd8170SKalle Valo struct work_struct wr_async_work; 66bdcd8170SKalle Valo struct list_head wr_asyncq; 6712eb9444SKalle Valo 6812eb9444SKalle Valo /* protects access to wr_asyncq */ 69bdcd8170SKalle Valo spinlock_t wr_async_lock; 70bdcd8170SKalle Valo }; 71bdcd8170SKalle Valo 72bdcd8170SKalle Valo #define CMD53_ARG_READ 0 73bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1 74bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1 75bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0 76bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1 77bdcd8170SKalle Valo 78bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 79bdcd8170SKalle Valo { 80bdcd8170SKalle Valo return ar->hif_priv; 81bdcd8170SKalle Valo } 82bdcd8170SKalle Valo 83bdcd8170SKalle Valo /* 84bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able. 85bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will 86bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 87bdcd8170SKalle Valo * check fails on stack memory. 88bdcd8170SKalle Valo */ 89bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf) 90bdcd8170SKalle Valo { 91bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 92bdcd8170SKalle Valo } 93bdcd8170SKalle Valo 94bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 95bdcd8170SKalle Valo { 96bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 97bdcd8170SKalle Valo 98bdcd8170SKalle Valo /* EP1 has an extended range */ 99bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 100bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 101bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 102bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 103bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 104bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 105bdcd8170SKalle Valo } 106bdcd8170SKalle Valo 107bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 108bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr, 109bdcd8170SKalle Valo u16 blksz) 110bdcd8170SKalle Valo { 111bdcd8170SKalle Valo *arg = (((rw & 1) << 31) | 112bdcd8170SKalle Valo ((func & 0x7) << 28) | 113bdcd8170SKalle Valo ((mode & 1) << 27) | 114bdcd8170SKalle Valo ((opcode & 1) << 26) | 115bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) | 116bdcd8170SKalle Valo (blksz & 0x1FF)); 117bdcd8170SKalle Valo } 118bdcd8170SKalle Valo 119bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 120bdcd8170SKalle Valo unsigned int address, 121bdcd8170SKalle Valo unsigned char val) 122bdcd8170SKalle Valo { 123bdcd8170SKalle Valo const u8 func = 0; 124bdcd8170SKalle Valo 125bdcd8170SKalle Valo *arg = ((write & 1) << 31) | 126bdcd8170SKalle Valo ((func & 0x7) << 28) | 127bdcd8170SKalle Valo ((raw & 1) << 27) | 128bdcd8170SKalle Valo (1 << 26) | 129bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) | 130bdcd8170SKalle Valo (1 << 8) | 131bdcd8170SKalle Valo (val & 0xFF); 132bdcd8170SKalle Valo } 133bdcd8170SKalle Valo 134bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 135bdcd8170SKalle Valo unsigned int address, 136bdcd8170SKalle Valo unsigned char byte) 137bdcd8170SKalle Valo { 138bdcd8170SKalle Valo struct mmc_command io_cmd; 139bdcd8170SKalle Valo 140bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd)); 141bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 142bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT; 143bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 144bdcd8170SKalle Valo 145bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0); 146bdcd8170SKalle Valo } 147bdcd8170SKalle Valo 148da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 149da220695SVasanthakumar Thiagarajan u8 *buf, u32 len) 150da220695SVasanthakumar Thiagarajan { 151da220695SVasanthakumar Thiagarajan int ret = 0; 152da220695SVasanthakumar Thiagarajan 153861dd058SVasanthakumar Thiagarajan sdio_claim_host(func); 154861dd058SVasanthakumar Thiagarajan 155da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) { 156f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */ 157da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR && 158da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR) 159da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len); 160da220695SVasanthakumar Thiagarajan 161f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */ 162da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR) 163da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len; 164da220695SVasanthakumar Thiagarajan 165da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 166da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len); 167da220695SVasanthakumar Thiagarajan else 168da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len); 169da220695SVasanthakumar Thiagarajan } else { 170da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 171da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len); 172da220695SVasanthakumar Thiagarajan else 173da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len); 174da220695SVasanthakumar Thiagarajan } 175da220695SVasanthakumar Thiagarajan 176861dd058SVasanthakumar Thiagarajan sdio_release_host(func); 177861dd058SVasanthakumar Thiagarajan 178f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 179f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr, 180f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 181f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 182f7325b85SKalle Valo 183e60c8154SKalle Valo trace_ath6kl_sdio(addr, request, buf, len); 184e60c8154SKalle Valo 185da220695SVasanthakumar Thiagarajan return ret; 186da220695SVasanthakumar Thiagarajan } 187da220695SVasanthakumar Thiagarajan 188bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 189bdcd8170SKalle Valo { 190bdcd8170SKalle Valo struct bus_request *bus_req; 191bdcd8170SKalle Valo 192151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 193bdcd8170SKalle Valo 194bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) { 195151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 196bdcd8170SKalle Valo return NULL; 197bdcd8170SKalle Valo } 198bdcd8170SKalle Valo 199bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 200bdcd8170SKalle Valo struct bus_request, list); 201bdcd8170SKalle Valo list_del(&bus_req->list); 202bdcd8170SKalle Valo 203151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 204f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 205f7325b85SKalle Valo __func__, bus_req); 206bdcd8170SKalle Valo 207bdcd8170SKalle Valo return bus_req; 208bdcd8170SKalle Valo } 209bdcd8170SKalle Valo 210bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 211bdcd8170SKalle Valo struct bus_request *bus_req) 212bdcd8170SKalle Valo { 213f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 214f7325b85SKalle Valo __func__, bus_req); 215bdcd8170SKalle Valo 216151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 217bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 218151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 219bdcd8170SKalle Valo } 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 222bdcd8170SKalle Valo struct mmc_data *data) 223bdcd8170SKalle Valo { 224bdcd8170SKalle Valo struct scatterlist *sg; 225bdcd8170SKalle Valo int i; 226bdcd8170SKalle Valo 227bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE; 228bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 229bdcd8170SKalle Valo 230bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, 231bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 232bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 233bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len, 234bdcd8170SKalle Valo scat_req->scat_entries); 235bdcd8170SKalle Valo 236bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 237bdcd8170SKalle Valo MMC_DATA_READ; 238bdcd8170SKalle Valo 239bdcd8170SKalle Valo /* fill SG entries */ 240d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries; 241bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries); 242bdcd8170SKalle Valo 243bdcd8170SKalle Valo /* assemble SG list */ 244bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) { 245bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 246bdcd8170SKalle Valo i, scat_req->scat_list[i].buf, 247bdcd8170SKalle Valo scat_req->scat_list[i].len); 248bdcd8170SKalle Valo 249bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf, 250bdcd8170SKalle Valo scat_req->scat_list[i].len); 251bdcd8170SKalle Valo } 252bdcd8170SKalle Valo 253bdcd8170SKalle Valo /* set scatter-gather table for request */ 254d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries; 255bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries; 256bdcd8170SKalle Valo } 257bdcd8170SKalle Valo 258bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 259bdcd8170SKalle Valo struct bus_request *req) 260bdcd8170SKalle Valo { 261bdcd8170SKalle Valo struct mmc_request mmc_req; 262bdcd8170SKalle Valo struct mmc_command cmd; 263bdcd8170SKalle Valo struct mmc_data data; 264bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 265bdcd8170SKalle Valo u8 opcode, rw; 266348a8fbcSVasanthakumar Thiagarajan int status, len; 267bdcd8170SKalle Valo 268bdcd8170SKalle Valo scat_req = req->scat_req; 269bdcd8170SKalle Valo 270348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) { 271348a8fbcSVasanthakumar Thiagarajan len = scat_req->len; 272348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS) 273348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE); 274348a8fbcSVasanthakumar Thiagarajan 275348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 276348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf, 277348a8fbcSVasanthakumar Thiagarajan len); 278348a8fbcSVasanthakumar Thiagarajan goto scat_complete; 279348a8fbcSVasanthakumar Thiagarajan } 280348a8fbcSVasanthakumar Thiagarajan 281bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request)); 282bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command)); 283bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data)); 284bdcd8170SKalle Valo 285d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data); 286bdcd8170SKalle Valo 287bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 288bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 289bdcd8170SKalle Valo 290bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 291bdcd8170SKalle Valo 292bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */ 293bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) { 294bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR) 295bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 296bdcd8170SKalle Valo else 297bdcd8170SKalle Valo /* Uses extended address range */ 298bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 299bdcd8170SKalle Valo } 300bdcd8170SKalle Valo 301bdcd8170SKalle Valo /* set command argument */ 302bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 303bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 304bdcd8170SKalle Valo data.blocks); 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED; 307bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo mmc_req.cmd = &cmd; 310bdcd8170SKalle Valo mmc_req.data = &data; 311bdcd8170SKalle Valo 312861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func); 313861dd058SVasanthakumar Thiagarajan 314bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card); 315e60c8154SKalle Valo 316e60c8154SKalle Valo trace_ath6kl_sdio_scat(scat_req->addr, 317e60c8154SKalle Valo scat_req->req, 318e60c8154SKalle Valo scat_req->len, 319e60c8154SKalle Valo scat_req->scat_entries, 320e60c8154SKalle Valo scat_req->scat_list); 321e60c8154SKalle Valo 322bdcd8170SKalle Valo /* synchronous call to process request */ 323bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 324bdcd8170SKalle Valo 325861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func); 326861dd058SVasanthakumar Thiagarajan 327bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error; 328348a8fbcSVasanthakumar Thiagarajan 329348a8fbcSVasanthakumar Thiagarajan scat_complete: 330bdcd8170SKalle Valo scat_req->status = status; 331bdcd8170SKalle Valo 332bdcd8170SKalle Valo if (scat_req->status) 333bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n", 334bdcd8170SKalle Valo scat_req->status); 335bdcd8170SKalle Valo 336bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS) 337e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req); 338bdcd8170SKalle Valo 339bdcd8170SKalle Valo return status; 340bdcd8170SKalle Valo } 341bdcd8170SKalle Valo 3423df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 3433df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req, 3443df505adSVasanthakumar Thiagarajan bool virt_scat) 3453df505adSVasanthakumar Thiagarajan { 3463df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req; 3473df505adSVasanthakumar Thiagarajan struct bus_request *bus_req; 34837291fc6SGeert Uytterhoeven int i, scat_req_sz, scat_list_sz, size; 349cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf; 3503df505adSVasanthakumar Thiagarajan 3513df505adSVasanthakumar Thiagarajan scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 3523df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz; 3533df505adSVasanthakumar Thiagarajan 3543df505adSVasanthakumar Thiagarajan if (!virt_scat) 35537291fc6SGeert Uytterhoeven size = sizeof(struct scatterlist) * n_scat_entry; 356cfeab10bSVasanthakumar Thiagarajan else 35737291fc6SGeert Uytterhoeven size = 2 * L1_CACHE_BYTES + 358cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 3593df505adSVasanthakumar Thiagarajan 3603df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) { 3613df505adSVasanthakumar Thiagarajan /* allocate the scatter request */ 3623df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL); 3633df505adSVasanthakumar Thiagarajan if (!s_req) 3643df505adSVasanthakumar Thiagarajan return -ENOMEM; 3653df505adSVasanthakumar Thiagarajan 366cfeab10bSVasanthakumar Thiagarajan if (virt_scat) { 36737291fc6SGeert Uytterhoeven virt_buf = kzalloc(size, GFP_KERNEL); 368cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) { 369cfeab10bSVasanthakumar Thiagarajan kfree(s_req); 370cfeab10bSVasanthakumar Thiagarajan return -ENOMEM; 371cfeab10bSVasanthakumar Thiagarajan } 372cfeab10bSVasanthakumar Thiagarajan 373cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf = 374cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 375cfeab10bSVasanthakumar Thiagarajan } else { 3763df505adSVasanthakumar Thiagarajan /* allocate sglist */ 37737291fc6SGeert Uytterhoeven s_req->sgentries = kzalloc(size, GFP_KERNEL); 3783df505adSVasanthakumar Thiagarajan 3793df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) { 3803df505adSVasanthakumar Thiagarajan kfree(s_req); 3813df505adSVasanthakumar Thiagarajan return -ENOMEM; 3823df505adSVasanthakumar Thiagarajan } 3833df505adSVasanthakumar Thiagarajan } 3843df505adSVasanthakumar Thiagarajan 3853df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */ 3863df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 3873df505adSVasanthakumar Thiagarajan if (!bus_req) { 3883df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries); 389cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 3903df505adSVasanthakumar Thiagarajan kfree(s_req); 3913df505adSVasanthakumar Thiagarajan return -ENOMEM; 3923df505adSVasanthakumar Thiagarajan } 3933df505adSVasanthakumar Thiagarajan 3943df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */ 3953df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req; 3963df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req; 3973df505adSVasanthakumar Thiagarajan 3984a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat; 3994a005c3eSVasanthakumar Thiagarajan 4003df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */ 4013df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req); 4023df505adSVasanthakumar Thiagarajan } 4033df505adSVasanthakumar Thiagarajan 4043df505adSVasanthakumar Thiagarajan return 0; 4053df505adSVasanthakumar Thiagarajan } 4063df505adSVasanthakumar Thiagarajan 407bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 408bdcd8170SKalle Valo u32 len, u32 request) 409bdcd8170SKalle Valo { 410bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 411bdcd8170SKalle Valo u8 *tbuf = NULL; 412bdcd8170SKalle Valo int ret; 413bdcd8170SKalle Valo bool bounced = false; 414bdcd8170SKalle Valo 415bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS) 416bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE); 417bdcd8170SKalle Valo 418bdcd8170SKalle Valo if (buf_needs_bounce(buf)) { 419bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) 420bdcd8170SKalle Valo return -ENOMEM; 421fdb28589SRaja Mani mutex_lock(&ar_sdio->dma_buffer_mutex); 422bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer; 423daa16bc5SRaja Mani 424daa16bc5SRaja Mani if (request & HIF_WRITE) 425bdcd8170SKalle Valo memcpy(tbuf, buf, len); 426daa16bc5SRaja Mani 427bdcd8170SKalle Valo bounced = true; 428bdcd8170SKalle Valo } else 429bdcd8170SKalle Valo tbuf = buf; 430bdcd8170SKalle Valo 431da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 432da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced) 433bdcd8170SKalle Valo memcpy(buf, tbuf, len); 434bdcd8170SKalle Valo 435fdb28589SRaja Mani if (bounced) 436fdb28589SRaja Mani mutex_unlock(&ar_sdio->dma_buffer_mutex); 437fdb28589SRaja Mani 438bdcd8170SKalle Valo return ret; 439bdcd8170SKalle Valo } 440bdcd8170SKalle Valo 441bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 442bdcd8170SKalle Valo struct bus_request *req) 443bdcd8170SKalle Valo { 444bdcd8170SKalle Valo if (req->scat_req) 445bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req); 446bdcd8170SKalle Valo else { 447bdcd8170SKalle Valo void *context; 448bdcd8170SKalle Valo int status; 449bdcd8170SKalle Valo 450bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 451bdcd8170SKalle Valo req->buffer, req->length, 452bdcd8170SKalle Valo req->request); 453bdcd8170SKalle Valo context = req->packet; 454bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 4558e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status); 456bdcd8170SKalle Valo } 457bdcd8170SKalle Valo } 458bdcd8170SKalle Valo 459bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work) 460bdcd8170SKalle Valo { 461bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 462bdcd8170SKalle Valo struct bus_request *req, *tmp_req; 463bdcd8170SKalle Valo 464bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 465bdcd8170SKalle Valo 466151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 467bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 468bdcd8170SKalle Valo list_del(&req->list); 469151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 470bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req); 471151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 472bdcd8170SKalle Valo } 473151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 474bdcd8170SKalle Valo } 475bdcd8170SKalle Valo 476bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func) 477bdcd8170SKalle Valo { 478bdcd8170SKalle Valo int status; 479bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 480bdcd8170SKalle Valo 481f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 482f7325b85SKalle Valo 483bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 484d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 1); 485bdcd8170SKalle Valo /* 486bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when 487bdcd8170SKalle Valo * we process commands. 488bdcd8170SKalle Valo */ 489bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 490bdcd8170SKalle Valo 4918e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 492bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 493d1f41597SRaja Mani 494d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 0); 495d1f41597SRaja Mani wake_up(&ar_sdio->irq_wq); 496d1f41597SRaja Mani 497bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED); 498bdcd8170SKalle Valo } 499bdcd8170SKalle Valo 500b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar) 501bdcd8170SKalle Valo { 502b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 503bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func; 504bdcd8170SKalle Valo int ret = 0; 505bdcd8170SKalle Valo 506bdcd8170SKalle Valo if (!ar_sdio->is_disabled) 507bdcd8170SKalle Valo return 0; 508bdcd8170SKalle Valo 5093ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 5103ef987beSKalle Valo 511bdcd8170SKalle Valo sdio_claim_host(func); 512bdcd8170SKalle Valo 513bdcd8170SKalle Valo ret = sdio_enable_func(func); 514bdcd8170SKalle Valo if (ret) { 515bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret); 516bdcd8170SKalle Valo sdio_release_host(func); 517bdcd8170SKalle Valo return ret; 518bdcd8170SKalle Valo } 519bdcd8170SKalle Valo 520bdcd8170SKalle Valo sdio_release_host(func); 521bdcd8170SKalle Valo 522bdcd8170SKalle Valo /* 523bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than 524bdcd8170SKalle Valo * 10 ms but let's be conservative here. 525bdcd8170SKalle Valo */ 526bdcd8170SKalle Valo msleep(10); 527bdcd8170SKalle Valo 528bdcd8170SKalle Valo ar_sdio->is_disabled = false; 529bdcd8170SKalle Valo 530bdcd8170SKalle Valo return ret; 531bdcd8170SKalle Valo } 532bdcd8170SKalle Valo 533b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar) 534bdcd8170SKalle Valo { 535b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 536bdcd8170SKalle Valo int ret; 537bdcd8170SKalle Valo 538bdcd8170SKalle Valo if (ar_sdio->is_disabled) 539bdcd8170SKalle Valo return 0; 540bdcd8170SKalle Valo 5413ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 5423ef987beSKalle Valo 543bdcd8170SKalle Valo /* Disable the card */ 544bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 545bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func); 546bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 547bdcd8170SKalle Valo 548bdcd8170SKalle Valo if (ret) 549bdcd8170SKalle Valo return ret; 550bdcd8170SKalle Valo 551bdcd8170SKalle Valo ar_sdio->is_disabled = true; 552bdcd8170SKalle Valo 553bdcd8170SKalle Valo return ret; 554bdcd8170SKalle Valo } 555bdcd8170SKalle Valo 556bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 557bdcd8170SKalle Valo u32 length, u32 request, 558bdcd8170SKalle Valo struct htc_packet *packet) 559bdcd8170SKalle Valo { 560bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 561bdcd8170SKalle Valo struct bus_request *bus_req; 562bdcd8170SKalle Valo 563bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 564bdcd8170SKalle Valo 56593b42caeSVasanthakumar Thiagarajan if (WARN_ON_ONCE(!bus_req)) 566bdcd8170SKalle Valo return -ENOMEM; 567bdcd8170SKalle Valo 568bdcd8170SKalle Valo bus_req->address = address; 569bdcd8170SKalle Valo bus_req->buffer = buffer; 570bdcd8170SKalle Valo bus_req->length = length; 571bdcd8170SKalle Valo bus_req->request = request; 572bdcd8170SKalle Valo bus_req->packet = packet; 573bdcd8170SKalle Valo 574151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 575bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 576151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 577bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 578bdcd8170SKalle Valo 579bdcd8170SKalle Valo return 0; 580bdcd8170SKalle Valo } 581bdcd8170SKalle Valo 582bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 583bdcd8170SKalle Valo { 584bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 585bdcd8170SKalle Valo int ret; 586bdcd8170SKalle Valo 587bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 588bdcd8170SKalle Valo 589bdcd8170SKalle Valo /* Register the isr */ 590bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 591bdcd8170SKalle Valo if (ret) 592bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret); 593bdcd8170SKalle Valo 594bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 595bdcd8170SKalle Valo } 596bdcd8170SKalle Valo 597d1f41597SRaja Mani static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar) 598d1f41597SRaja Mani { 599d1f41597SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 600d1f41597SRaja Mani 601d1f41597SRaja Mani return !atomic_read(&ar_sdio->irq_handling); 602d1f41597SRaja Mani } 603d1f41597SRaja Mani 604bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 605bdcd8170SKalle Valo { 606bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 607bdcd8170SKalle Valo int ret; 608bdcd8170SKalle Valo 609bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 610bdcd8170SKalle Valo 611d1f41597SRaja Mani if (atomic_read(&ar_sdio->irq_handling)) { 612d1f41597SRaja Mani sdio_release_host(ar_sdio->func); 613d1f41597SRaja Mani 614d1f41597SRaja Mani ret = wait_event_interruptible(ar_sdio->irq_wq, 615d1f41597SRaja Mani ath6kl_sdio_is_on_irq(ar)); 616d1f41597SRaja Mani if (ret) 617d1f41597SRaja Mani return; 618d1f41597SRaja Mani 619d1f41597SRaja Mani sdio_claim_host(ar_sdio->func); 620d1f41597SRaja Mani } 621bdcd8170SKalle Valo 622bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func); 623bdcd8170SKalle Valo if (ret) 624bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret); 625bdcd8170SKalle Valo 626bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 627bdcd8170SKalle Valo } 628bdcd8170SKalle Valo 629bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 630bdcd8170SKalle Valo { 631bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 632bdcd8170SKalle Valo struct hif_scatter_req *node = NULL; 633bdcd8170SKalle Valo 634151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 635bdcd8170SKalle Valo 636bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) { 637bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req, 638bdcd8170SKalle Valo struct hif_scatter_req, list); 639bdcd8170SKalle Valo list_del(&node->list); 640b29072ccSChilam Ng 641b29072ccSChilam Ng node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req); 642bdcd8170SKalle Valo } 643bdcd8170SKalle Valo 644151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 645bdcd8170SKalle Valo 646bdcd8170SKalle Valo return node; 647bdcd8170SKalle Valo } 648bdcd8170SKalle Valo 649bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 650bdcd8170SKalle Valo struct hif_scatter_req *s_req) 651bdcd8170SKalle Valo { 652bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 653bdcd8170SKalle Valo 654151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 655bdcd8170SKalle Valo 656bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req); 657bdcd8170SKalle Valo 658151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 659bdcd8170SKalle Valo 660bdcd8170SKalle Valo } 661bdcd8170SKalle Valo 662c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */ 663c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 664c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req) 665c630d18aSVasanthakumar Thiagarajan { 666c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 667c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req; 668c630d18aSVasanthakumar Thiagarajan int status = 0; 669c630d18aSVasanthakumar Thiagarajan 670c630d18aSVasanthakumar Thiagarajan if (!scat_req->len) 671c630d18aSVasanthakumar Thiagarajan return -EINVAL; 672c630d18aSVasanthakumar Thiagarajan 673c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER, 674c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n", 675c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries); 676c630d18aSVasanthakumar Thiagarajan 677861dd058SVasanthakumar Thiagarajan if (request & HIF_SYNCHRONOUS) 678d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 679861dd058SVasanthakumar Thiagarajan else { 680151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 681d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 682151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 683c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 684c630d18aSVasanthakumar Thiagarajan } 685c630d18aSVasanthakumar Thiagarajan 686c630d18aSVasanthakumar Thiagarajan return status; 687c630d18aSVasanthakumar Thiagarajan } 688c630d18aSVasanthakumar Thiagarajan 68918a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */ 69018a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 69118a0f93eSVasanthakumar Thiagarajan { 69218a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 69318a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req; 69418a0f93eSVasanthakumar Thiagarajan 69518a0f93eSVasanthakumar Thiagarajan /* empty the free list */ 696151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 69718a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 69818a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list); 699151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 70018a0f93eSVasanthakumar Thiagarajan 70132a07e44SKalle Valo /* 70232a07e44SKalle Valo * FIXME: should we also call completion handler with 70332a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 70432a07e44SKalle Valo * that the packet is properly freed? 70532a07e44SKalle Valo */ 70618a0f93eSVasanthakumar Thiagarajan if (s_req->busrequest) 70718a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 70818a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 70918a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries); 71018a0f93eSVasanthakumar Thiagarajan kfree(s_req); 71118a0f93eSVasanthakumar Thiagarajan 712151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 71318a0f93eSVasanthakumar Thiagarajan } 714151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 71518a0f93eSVasanthakumar Thiagarajan } 71618a0f93eSVasanthakumar Thiagarajan 71718a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */ 71850745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 71918a0f93eSVasanthakumar Thiagarajan { 72018a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 72150745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target; 722527f6570SAndi Kleen int ret = 0; 723cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false; 72418a0f93eSVasanthakumar Thiagarajan 72532a07e44SKalle Valo if (ar_sdio->scatter_enabled) 72632a07e44SKalle Valo return 0; 72732a07e44SKalle Valo 72832a07e44SKalle Valo ar_sdio->scatter_enabled = true; 72932a07e44SKalle Valo 73018a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */ 73118a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 732cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 73318a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs, 73418a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 735cfeab10bSVasanthakumar Thiagarajan virt_scat = true; 73618a0f93eSVasanthakumar Thiagarajan } 73718a0f93eSVasanthakumar Thiagarajan 738cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) { 73918a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 74018a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ, 741cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat); 742cfeab10bSVasanthakumar Thiagarajan 743cfeab10bSVasanthakumar Thiagarajan if (!ret) { 7443ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7453ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n", 746cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, 747cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 748cfeab10bSVasanthakumar Thiagarajan 74950745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 75050745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 751cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE; 752cfeab10bSVasanthakumar Thiagarajan } else { 753cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 754cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 755cfeab10bSVasanthakumar Thiagarajan } 756cfeab10bSVasanthakumar Thiagarajan } 757cfeab10bSVasanthakumar Thiagarajan 758cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) { 759cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 760cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ, 761cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat); 762cfeab10bSVasanthakumar Thiagarajan 76318a0f93eSVasanthakumar Thiagarajan if (ret) { 764cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n"); 76518a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 76618a0f93eSVasanthakumar Thiagarajan return ret; 76718a0f93eSVasanthakumar Thiagarajan } 76818a0f93eSVasanthakumar Thiagarajan 7693ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7703ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n", 771cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 772cfeab10bSVasanthakumar Thiagarajan 77350745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 77450745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 775cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 776cfeab10bSVasanthakumar Thiagarajan } 777cfeab10bSVasanthakumar Thiagarajan 77818a0f93eSVasanthakumar Thiagarajan return 0; 77918a0f93eSVasanthakumar Thiagarajan } 78018a0f93eSVasanthakumar Thiagarajan 781e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar) 782e28e8104SKalle Valo { 783e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 784e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func; 785e28e8104SKalle Valo int ret; 786e28e8104SKalle Valo 787e28e8104SKalle Valo sdio_claim_host(func); 788e28e8104SKalle Valo 789e28e8104SKalle Valo if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 790e28e8104SKalle Valo MANUFACTURER_ID_AR6003_BASE) { 791e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */ 792e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 793e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG, 794e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 795e28e8104SKalle Valo if (ret) { 796e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 797e28e8104SKalle Valo ret); 798e28e8104SKalle Valo goto out; 799e28e8104SKalle Valo } 800e28e8104SKalle Valo 801e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 802e28e8104SKalle Valo } 803e28e8104SKalle Valo 804e28e8104SKalle Valo /* give us some time to enable, in ms */ 805e28e8104SKalle Valo func->enable_timeout = 100; 806e28e8104SKalle Valo 807e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 808e28e8104SKalle Valo if (ret) { 809e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n", 810e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret); 811e28e8104SKalle Valo goto out; 812e28e8104SKalle Valo } 813e28e8104SKalle Valo 814e28e8104SKalle Valo out: 815e28e8104SKalle Valo sdio_release_host(func); 816e28e8104SKalle Valo 817e28e8104SKalle Valo return ret; 818e28e8104SKalle Valo } 819e28e8104SKalle Valo 820e390af77SRaja Mani static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar) 821abcb344bSKalle Valo { 822abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 823abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func; 824abcb344bSKalle Valo mmc_pm_flag_t flags; 825abcb344bSKalle Valo int ret; 826abcb344bSKalle Valo 827abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func); 828abcb344bSKalle Valo 829b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 830b4b2a0b1SKalle Valo 831e390af77SRaja Mani if (!(flags & MMC_PM_WAKE_SDIO_IRQ) || 832e390af77SRaja Mani !(flags & MMC_PM_KEEP_POWER)) 833e390af77SRaja Mani return -EINVAL; 834abcb344bSKalle Valo 835abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 836abcb344bSKalle Valo if (ret) { 837e390af77SRaja Mani ath6kl_err("set sdio keep pwr flag failed: %d\n", ret); 838abcb344bSKalle Valo return ret; 839abcb344bSKalle Valo } 840abcb344bSKalle Valo 84110509f90SKalle Valo /* sdio irq wakes up host */ 842d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 843d7c44e0bSRaja Mani if (ret) 844d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 845d7c44e0bSRaja Mani 846d7c44e0bSRaja Mani return ret; 847d7c44e0bSRaja Mani } 848d7c44e0bSRaja Mani 849e390af77SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 850e390af77SRaja Mani { 851e390af77SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 852e390af77SRaja Mani struct sdio_func *func = ar_sdio->func; 853e390af77SRaja Mani mmc_pm_flag_t flags; 8541e9a905dSRaja Mani bool try_deepsleep = false; 855e390af77SRaja Mani int ret; 856e390af77SRaja Mani 857e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_WOW || 858e390af77SRaja Mani (!ar->suspend_mode && wow)) { 859e390af77SRaja Mani 860e390af77SRaja Mani ret = ath6kl_set_sdio_pm_caps(ar); 861e390af77SRaja Mani if (ret) 862e390af77SRaja Mani goto cut_pwr; 863e390af77SRaja Mani 864e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 8651e9a905dSRaja Mani if (ret && ret != -ENOTCONN) 8661e9a905dSRaja Mani ath6kl_err("wow suspend failed: %d\n", ret); 867e390af77SRaja Mani 8687433a490SKalle Valo if (ret && 8697433a490SKalle Valo (!ar->wow_suspend_mode || 8701e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP)) 8711e9a905dSRaja Mani try_deepsleep = true; 8721e9a905dSRaja Mani else if (ret && 8731e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR) 8741e9a905dSRaja Mani goto cut_pwr; 8751e9a905dSRaja Mani if (!ret) 876e390af77SRaja Mani return 0; 877e390af77SRaja Mani } 878e390af77SRaja Mani 879e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP || 8801e9a905dSRaja Mani !ar->suspend_mode || try_deepsleep) { 881e390af77SRaja Mani 882e390af77SRaja Mani flags = sdio_get_host_pm_caps(func); 883e390af77SRaja Mani if (!(flags & MMC_PM_KEEP_POWER)) 884e390af77SRaja Mani goto cut_pwr; 885e390af77SRaja Mani 886e390af77SRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 887e390af77SRaja Mani if (ret) 888e390af77SRaja Mani goto cut_pwr; 889e390af77SRaja Mani 890cca4d5adSSantosh Sajjan /* 891cca4d5adSSantosh Sajjan * Workaround to support Deep Sleep with MSM, set the host pm 892cca4d5adSSantosh Sajjan * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable 893cca4d5adSSantosh Sajjan * the sdc2_clock and internally allows MSM to enter 894cca4d5adSSantosh Sajjan * TCXO shutdown properly. 895cca4d5adSSantosh Sajjan */ 896cca4d5adSSantosh Sajjan if ((flags & MMC_PM_WAKE_SDIO_IRQ)) { 897cca4d5adSSantosh Sajjan ret = sdio_set_host_pm_flags(func, 898cca4d5adSSantosh Sajjan MMC_PM_WAKE_SDIO_IRQ); 899cca4d5adSSantosh Sajjan if (ret) 900cca4d5adSSantosh Sajjan goto cut_pwr; 901cca4d5adSSantosh Sajjan } 902cca4d5adSSantosh Sajjan 903e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, 904e390af77SRaja Mani NULL); 905e390af77SRaja Mani if (ret) 906e390af77SRaja Mani goto cut_pwr; 907e390af77SRaja Mani 908e390af77SRaja Mani return 0; 909e390af77SRaja Mani } 910e390af77SRaja Mani 911e390af77SRaja Mani cut_pwr: 9125699257fSMing Jiang if (func->card && func->card->host) 9135699257fSMing Jiang func->card->host->pm_flags &= ~MMC_PM_KEEP_POWER; 9145699257fSMing Jiang 915e390af77SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL); 916abcb344bSKalle Valo } 917abcb344bSKalle Valo 918aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar) 919aa6cffc1SChilam Ng { 920b4b2a0b1SKalle Valo switch (ar->state) { 921b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF: 922b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER: 923b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, 924b4b2a0b1SKalle Valo "sdio resume configuring sdio\n"); 925b4b2a0b1SKalle Valo 926b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */ 927b4b2a0b1SKalle Valo ath6kl_sdio_config(ar); 928b4b2a0b1SKalle Valo break; 929b4b2a0b1SKalle Valo 930b4b2a0b1SKalle Valo case ATH6KL_STATE_ON: 931b4b2a0b1SKalle Valo break; 932b4b2a0b1SKalle Valo 933b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP: 934b4b2a0b1SKalle Valo break; 935d7c44e0bSRaja Mani 936d7c44e0bSRaja Mani case ATH6KL_STATE_WOW: 937d7c44e0bSRaja Mani break; 938390a8c8fSRaja Mani 939390a8c8fSRaja Mani case ATH6KL_STATE_SUSPENDING: 940390a8c8fSRaja Mani break; 941390a8c8fSRaja Mani 942390a8c8fSRaja Mani case ATH6KL_STATE_RESUMING: 943390a8c8fSRaja Mani break; 94484caf800SVasanthakumar Thiagarajan 94584caf800SVasanthakumar Thiagarajan case ATH6KL_STATE_RECOVERY: 94684caf800SVasanthakumar Thiagarajan break; 947b4b2a0b1SKalle Valo } 948b4b2a0b1SKalle Valo 94952d81a68SKalle Valo ath6kl_cfg80211_resume(ar); 950aa6cffc1SChilam Ng 951aa6cffc1SChilam Ng return 0; 952aa6cffc1SChilam Ng } 953aa6cffc1SChilam Ng 954c7111495SKalle Valo /* set the window address register (using 4-byte register access ). */ 955c7111495SKalle Valo static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr) 956c7111495SKalle Valo { 957c7111495SKalle Valo int status; 958c7111495SKalle Valo u8 addr_val[4]; 959c7111495SKalle Valo s32 i; 960c7111495SKalle Valo 961c7111495SKalle Valo /* 962c7111495SKalle Valo * Write bytes 1,2,3 of the register to set the upper address bytes, 963c7111495SKalle Valo * the LSB is written last to initiate the access cycle 964c7111495SKalle Valo */ 965c7111495SKalle Valo 966c7111495SKalle Valo for (i = 1; i <= 3; i++) { 967c7111495SKalle Valo /* 968c7111495SKalle Valo * Fill the buffer with the address byte value we want to 969c7111495SKalle Valo * hit 4 times. 970c7111495SKalle Valo */ 971c7111495SKalle Valo memset(addr_val, ((u8 *)&addr)[i], 4); 972c7111495SKalle Valo 973c7111495SKalle Valo /* 974c7111495SKalle Valo * Hit each byte of the register address with a 4-byte 975c7111495SKalle Valo * write operation to the same address, this is a harmless 976c7111495SKalle Valo * operation. 977c7111495SKalle Valo */ 978c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val, 979c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_FIX); 980c7111495SKalle Valo if (status) 981c7111495SKalle Valo break; 982c7111495SKalle Valo } 983c7111495SKalle Valo 984c7111495SKalle Valo if (status) { 985cdeb8602SKalle Valo ath6kl_err("%s: failed to write initial bytes of 0x%x to window reg: 0x%X\n", 986cdeb8602SKalle Valo __func__, addr, reg_addr); 987c7111495SKalle Valo return status; 988c7111495SKalle Valo } 989c7111495SKalle Valo 990c7111495SKalle Valo /* 991c7111495SKalle Valo * Write the address register again, this time write the whole 992c7111495SKalle Valo * 4-byte value. The effect here is that the LSB write causes the 993c7111495SKalle Valo * cycle to start, the extra 3 byte write to bytes 1,2,3 has no 994c7111495SKalle Valo * effect since we are writing the same values again 995c7111495SKalle Valo */ 996c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr), 997c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_INC); 998c7111495SKalle Valo 999c7111495SKalle Valo if (status) { 1000c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n", 1001c7111495SKalle Valo __func__, addr, reg_addr); 1002c7111495SKalle Valo return status; 1003c7111495SKalle Valo } 1004c7111495SKalle Valo 1005c7111495SKalle Valo return 0; 1006c7111495SKalle Valo } 1007c7111495SKalle Valo 1008c7111495SKalle Valo static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data) 1009c7111495SKalle Valo { 1010c7111495SKalle Valo int status; 1011c7111495SKalle Valo 1012c7111495SKalle Valo /* set window register to start read cycle */ 1013c7111495SKalle Valo status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS, 1014c7111495SKalle Valo address); 1015c7111495SKalle Valo 1016c7111495SKalle Valo if (status) 1017c7111495SKalle Valo return status; 1018c7111495SKalle Valo 1019c7111495SKalle Valo /* read the data */ 1020c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1021c7111495SKalle Valo (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC); 1022c7111495SKalle Valo if (status) { 1023c7111495SKalle Valo ath6kl_err("%s: failed to read from window data addr\n", 1024c7111495SKalle Valo __func__); 1025c7111495SKalle Valo return status; 1026c7111495SKalle Valo } 1027c7111495SKalle Valo 1028c7111495SKalle Valo return status; 1029c7111495SKalle Valo } 1030c7111495SKalle Valo 1031c7111495SKalle Valo static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address, 1032c7111495SKalle Valo __le32 data) 1033c7111495SKalle Valo { 1034c7111495SKalle Valo int status; 1035c7111495SKalle Valo u32 val = (__force u32) data; 1036c7111495SKalle Valo 1037c7111495SKalle Valo /* set write data */ 1038c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 1039c7111495SKalle Valo (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); 1040c7111495SKalle Valo if (status) { 1041c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window data addr\n", 1042c7111495SKalle Valo __func__, data); 1043c7111495SKalle Valo return status; 1044c7111495SKalle Valo } 1045c7111495SKalle Valo 1046c7111495SKalle Valo /* set window register, which starts the write cycle */ 1047c7111495SKalle Valo return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS, 1048c7111495SKalle Valo address); 1049c7111495SKalle Valo } 1050c7111495SKalle Valo 105166b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 105266b693c3SKalle Valo { 105366b693c3SKalle Valo u32 addr; 105466b693c3SKalle Valo unsigned long timeout; 105566b693c3SKalle Valo int ret; 105666b693c3SKalle Valo 105766b693c3SKalle Valo ar->bmi.cmd_credits = 0; 105866b693c3SKalle Valo 105966b693c3SKalle Valo /* Read the counter register to get the command credits */ 106066b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 106166b693c3SKalle Valo 106266b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 106366b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 106466b693c3SKalle Valo 106566b693c3SKalle Valo /* 106666b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte 106766b693c3SKalle Valo * read will hit the counter and cause a decrement, while the 106866b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this 106966b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned. 107066b693c3SKalle Valo */ 107166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, 107266b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4, 107366b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 107466b693c3SKalle Valo if (ret) { 1075cdeb8602SKalle Valo ath6kl_err("Unable to decrement the command credit count register: %d\n", 1076cdeb8602SKalle Valo ret); 107766b693c3SKalle Valo return ret; 107866b693c3SKalle Valo } 107966b693c3SKalle Valo 108066b693c3SKalle Valo /* The counter is only 8 bits. 108166b693c3SKalle Valo * Ignore anything in the upper 3 bytes 108266b693c3SKalle Valo */ 108366b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF; 108466b693c3SKalle Valo } 108566b693c3SKalle Valo 108666b693c3SKalle Valo if (!ar->bmi.cmd_credits) { 108766b693c3SKalle Valo ath6kl_err("bmi communication timeout\n"); 108866b693c3SKalle Valo return -ETIMEDOUT; 108966b693c3SKalle Valo } 109066b693c3SKalle Valo 109166b693c3SKalle Valo return 0; 109266b693c3SKalle Valo } 109366b693c3SKalle Valo 109466b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 109566b693c3SKalle Valo { 109666b693c3SKalle Valo unsigned long timeout; 109766b693c3SKalle Valo u32 rx_word = 0; 109866b693c3SKalle Valo int ret = 0; 109966b693c3SKalle Valo 110066b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 110166b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) { 110266b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, 110366b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS, 110466b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word), 110566b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 110666b693c3SKalle Valo if (ret) { 110766b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 110866b693c3SKalle Valo return ret; 110966b693c3SKalle Valo } 111066b693c3SKalle Valo 111166b693c3SKalle Valo /* all we really want is one bit */ 111266b693c3SKalle Valo rx_word &= (1 << ENDPOINT1); 111366b693c3SKalle Valo } 111466b693c3SKalle Valo 111566b693c3SKalle Valo if (!rx_word) { 111666b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n"); 111766b693c3SKalle Valo return -EINVAL; 111866b693c3SKalle Valo } 111966b693c3SKalle Valo 112066b693c3SKalle Valo return ret; 112166b693c3SKalle Valo } 112266b693c3SKalle Valo 112366b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 112466b693c3SKalle Valo { 112566b693c3SKalle Valo int ret; 112666b693c3SKalle Valo u32 addr; 112766b693c3SKalle Valo 112866b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar); 112966b693c3SKalle Valo if (ret) 113066b693c3SKalle Valo return ret; 113166b693c3SKalle Valo 113266b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 113366b693c3SKalle Valo 113466b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 113566b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC); 1136bf978145SMohammed Shafi Shajakhan if (ret) { 113766b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n"); 113866b693c3SKalle Valo return ret; 113966b693c3SKalle Valo } 114066b693c3SKalle Valo 1141bf978145SMohammed Shafi Shajakhan return 0; 1142bf978145SMohammed Shafi Shajakhan } 1143bf978145SMohammed Shafi Shajakhan 114466b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 114566b693c3SKalle Valo { 114666b693c3SKalle Valo int ret; 114766b693c3SKalle Valo u32 addr; 114866b693c3SKalle Valo 114966b693c3SKalle Valo /* 115066b693c3SKalle Valo * During normal bootup, small reads may be required. 115166b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target 115266b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until 115366b693c3SKalle Valo * we know that response data is available. 115466b693c3SKalle Valo * 115566b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected 115666b693c3SKalle Valo * Target failure rather than risk problems at the HIF level. 115766b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage 115866b693c3SKalle Valo * data on some host controllers. And on an interconnect 115966b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which 116066b693c3SKalle Valo * does not provide any indication on data timeout, it avoids 116166b693c3SKalle Valo * a potential hang or garbage response. 116266b693c3SKalle Valo * 116366b693c3SKalle Valo * Synchronization is more difficult for reads larger than the 116466b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable 116566b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an 116666b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the 116766b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is 116866b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do 116966b693c3SKalle Valo * not occur in practice -- they're supported for debug/development. 117066b693c3SKalle Valo * 117166b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases: 117266b693c3SKalle Valo * CASE 1: length < 4 117366b693c3SKalle Valo * Should not happen 117466b693c3SKalle Valo * 117566b693c3SKalle Valo * CASE 2: 4 <= length <= 128 117666b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO 117766b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for 117866b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE 117966b693c3SKalle Valo * response is available in the the FIFO 118066b693c3SKalle Valo * 118166b693c3SKalle Valo * CASE 3: length > 128 118266b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO 118366b693c3SKalle Valo * 118466b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will 118566b693c3SKalle Valo * usually see a response quickly; but there may be some unusual 118666b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout. 118766b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for 118866b693c3SKalle Valo * BMI_EXECUTE. 118966b693c3SKalle Valo * 119066b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution, 119166b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep 119266b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 119366b693c3SKalle Valo * a function of Host processor speed. 119466b693c3SKalle Valo */ 119566b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */ 119666b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar); 119766b693c3SKalle Valo if (ret) 119866b693c3SKalle Valo return ret; 119966b693c3SKalle Valo } 120066b693c3SKalle Valo 120166b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 120266b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 120366b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 120466b693c3SKalle Valo if (ret) { 120566b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n", 120666b693c3SKalle Valo ret); 120766b693c3SKalle Valo return ret; 120866b693c3SKalle Valo } 120966b693c3SKalle Valo 121066b693c3SKalle Valo return 0; 121166b693c3SKalle Valo } 121266b693c3SKalle Valo 121332a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar) 121432a07e44SKalle Valo { 121532a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 121632a07e44SKalle Valo struct bus_request *req, *tmp_req; 121732a07e44SKalle Valo void *context; 121832a07e44SKalle Valo 121932a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */ 122032a07e44SKalle Valo 122132a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 122232a07e44SKalle Valo 122332a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock); 122432a07e44SKalle Valo 122532a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 122632a07e44SKalle Valo list_del(&req->list); 122732a07e44SKalle Valo 122832a07e44SKalle Valo if (req->scat_req) { 122932a07e44SKalle Valo /* this is a scatter gather request */ 123032a07e44SKalle Valo req->scat_req->status = -ECANCELED; 123132a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target, 123232a07e44SKalle Valo req->scat_req); 123332a07e44SKalle Valo } else { 123432a07e44SKalle Valo context = req->packet; 123532a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 123632a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED); 123732a07e44SKalle Valo } 123832a07e44SKalle Valo } 123932a07e44SKalle Valo 124032a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock); 124132a07e44SKalle Valo 124232a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 124332a07e44SKalle Valo } 124432a07e44SKalle Valo 1245bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1246bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync, 1247bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async, 1248bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable, 1249bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable, 1250bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get, 1251bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add, 1252bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter, 1253f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1254bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1255abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend, 1256aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume, 1257c7111495SKalle Valo .diag_read32 = ath6kl_sdio_diag_read32, 1258c7111495SKalle Valo .diag_write32 = ath6kl_sdio_diag_write32, 125966b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read, 126066b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write, 1261b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on, 1262b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off, 126332a07e44SKalle Valo .stop = ath6kl_sdio_stop, 1264bdcd8170SKalle Valo }; 1265bdcd8170SKalle Valo 1266b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP 1267b4b2a0b1SKalle Valo 1268b4b2a0b1SKalle Valo /* 1269b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during 1270b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers. 1271b4b2a0b1SKalle Valo */ 1272b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device) 1273b4b2a0b1SKalle Valo { 1274b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1275b4b2a0b1SKalle Valo 1276b4b2a0b1SKalle Valo return 0; 1277b4b2a0b1SKalle Valo } 1278b4b2a0b1SKalle Valo 1279b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device) 1280b4b2a0b1SKalle Valo { 1281b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1282b4b2a0b1SKalle Valo 1283b4b2a0b1SKalle Valo return 0; 1284b4b2a0b1SKalle Valo } 1285b4b2a0b1SKalle Valo 1286b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1287b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume); 1288b4b2a0b1SKalle Valo 1289b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1290b4b2a0b1SKalle Valo 1291b4b2a0b1SKalle Valo #else 1292b4b2a0b1SKalle Valo 1293b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL 1294b4b2a0b1SKalle Valo 1295b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */ 1296b4b2a0b1SKalle Valo 1297bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func, 1298bdcd8170SKalle Valo const struct sdio_device_id *id) 1299bdcd8170SKalle Valo { 1300bdcd8170SKalle Valo int ret; 1301bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1302bdcd8170SKalle Valo struct ath6kl *ar; 1303bdcd8170SKalle Valo int count; 1304bdcd8170SKalle Valo 13053ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 13063ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1307f7325b85SKalle Valo func->num, func->vendor, func->device, 1308f7325b85SKalle Valo func->max_blksize, func->cur_blksize); 1309bdcd8170SKalle Valo 1310bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1311bdcd8170SKalle Valo if (!ar_sdio) 1312bdcd8170SKalle Valo return -ENOMEM; 1313bdcd8170SKalle Valo 1314bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1315bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) { 1316bdcd8170SKalle Valo ret = -ENOMEM; 1317bdcd8170SKalle Valo goto err_hif; 1318bdcd8170SKalle Valo } 1319bdcd8170SKalle Valo 1320bdcd8170SKalle Valo ar_sdio->func = func; 1321bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio); 1322bdcd8170SKalle Valo 1323bdcd8170SKalle Valo ar_sdio->id = id; 1324bdcd8170SKalle Valo ar_sdio->is_disabled = true; 1325bdcd8170SKalle Valo 1326bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock); 1327bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock); 1328bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock); 1329fdb28589SRaja Mani mutex_init(&ar_sdio->dma_buffer_mutex); 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req); 1332bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1333bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1334bdcd8170SKalle Valo 1335bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1336bdcd8170SKalle Valo 1337d1f41597SRaja Mani init_waitqueue_head(&ar_sdio->irq_wq); 1338d1f41597SRaja Mani 1339bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1340bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1341bdcd8170SKalle Valo 134245eaa78fSKalle Valo ar = ath6kl_core_create(&ar_sdio->func->dev); 1343bdcd8170SKalle Valo if (!ar) { 1344bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n"); 1345bdcd8170SKalle Valo ret = -ENOMEM; 1346bdcd8170SKalle Valo goto err_dma; 1347bdcd8170SKalle Valo } 1348bdcd8170SKalle Valo 1349bdcd8170SKalle Valo ar_sdio->ar = ar; 135077eab1e9SKalle Valo ar->hif_type = ATH6KL_HIF_TYPE_SDIO; 1351bdcd8170SKalle Valo ar->hif_priv = ar_sdio; 1352bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops; 13531f4c894dSKalle Valo ar->bmi.max_data_size = 256; 1354bdcd8170SKalle Valo 1355bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar); 1356bdcd8170SKalle Valo 1357e28e8104SKalle Valo ret = ath6kl_sdio_config(ar); 1358bdcd8170SKalle Valo if (ret) { 1359e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret); 13608dafb70eSVasanthakumar Thiagarajan goto err_core_alloc; 1361bdcd8170SKalle Valo } 1362bdcd8170SKalle Valo 1363e76ac2bfSKalle Valo ret = ath6kl_core_init(ar, ATH6KL_HTC_TYPE_MBOX); 1364bdcd8170SKalle Valo if (ret) { 1365bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n"); 1366e28e8104SKalle Valo goto err_core_alloc; 1367bdcd8170SKalle Valo } 1368bdcd8170SKalle Valo 1369bdcd8170SKalle Valo return ret; 1370bdcd8170SKalle Valo 13718dafb70eSVasanthakumar Thiagarajan err_core_alloc: 137245eaa78fSKalle Valo ath6kl_core_destroy(ar_sdio->ar); 1373bdcd8170SKalle Valo err_dma: 1374bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1375bdcd8170SKalle Valo err_hif: 1376bdcd8170SKalle Valo kfree(ar_sdio); 1377bdcd8170SKalle Valo 1378bdcd8170SKalle Valo return ret; 1379bdcd8170SKalle Valo } 1380bdcd8170SKalle Valo 1381bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func) 1382bdcd8170SKalle Valo { 1383bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1384bdcd8170SKalle Valo 13853ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 13863ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n", 1387f7325b85SKalle Valo func->num, func->vendor, func->device); 1388f7325b85SKalle Valo 1389bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 1390bdcd8170SKalle Valo 1391bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar); 1392bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 1393bdcd8170SKalle Valo 13946db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar); 13950e7de662SVasanthakumar Thiagarajan ath6kl_core_destroy(ar_sdio->ar); 1396bdcd8170SKalle Valo 1397bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1398bdcd8170SKalle Valo kfree(ar_sdio); 1399bdcd8170SKalle Valo } 1400bdcd8170SKalle Valo 1401bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = { 1402bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1403bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1404d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))}, 1405d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, 1406bdcd8170SKalle Valo {}, 1407bdcd8170SKalle Valo }; 1408bdcd8170SKalle Valo 1409bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1410bdcd8170SKalle Valo 1411bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = { 1412241b128bSKalle Valo .name = "ath6kl_sdio", 1413bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices, 1414bdcd8170SKalle Valo .probe = ath6kl_sdio_probe, 1415bdcd8170SKalle Valo .remove = ath6kl_sdio_remove, 1416b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS, 1417bdcd8170SKalle Valo }; 1418bdcd8170SKalle Valo 1419bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void) 1420bdcd8170SKalle Valo { 1421bdcd8170SKalle Valo int ret; 1422bdcd8170SKalle Valo 1423bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver); 1424bdcd8170SKalle Valo if (ret) 1425bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret); 1426bdcd8170SKalle Valo 1427bdcd8170SKalle Valo return ret; 1428bdcd8170SKalle Valo } 1429bdcd8170SKalle Valo 1430bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void) 1431bdcd8170SKalle Valo { 1432bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver); 1433bdcd8170SKalle Valo } 1434bdcd8170SKalle Valo 1435bdcd8170SKalle Valo module_init(ath6kl_sdio_init); 1436bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit); 1437bdcd8170SKalle Valo 1438bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc."); 1439bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1440bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL"); 1441bdcd8170SKalle Valo 1442c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE); 1443c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE); 1444c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE); 14450d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE); 14460d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE); 1447c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE); 1448c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE); 1449c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE); 14500d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE); 14510d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE); 1452c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE); 1453f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE); 1454f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE); 1455c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE); 1456f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE); 1457f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE); 14586146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_FW_DIR "/" AR6004_HW_1_2_FIRMWARE_FILE); 14596146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_BOARD_DATA_FILE); 14606146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE); 1461bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_FW_DIR "/" AR6004_HW_1_3_FIRMWARE_FILE); 1462bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_BOARD_DATA_FILE); 1463bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE); 1464