1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #include <linux/mmc/card.h> 18bdcd8170SKalle Valo #include <linux/mmc/mmc.h> 19bdcd8170SKalle Valo #include <linux/mmc/host.h> 20bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 21bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h> 22bdcd8170SKalle Valo #include <linux/mmc/sdio.h> 23bdcd8170SKalle Valo #include <linux/mmc/sd.h> 242e1cb23cSKalle Valo #include "hif.h" 25bdcd8170SKalle Valo #include "hif-ops.h" 26bdcd8170SKalle Valo #include "target.h" 27bdcd8170SKalle Valo #include "debug.h" 289df337a1SVivek Natarajan #include "cfg80211.h" 29bdcd8170SKalle Valo 30bdcd8170SKalle Valo struct ath6kl_sdio { 31bdcd8170SKalle Valo struct sdio_func *func; 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo spinlock_t lock; 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo /* free list */ 36bdcd8170SKalle Valo struct list_head bus_req_freeq; 37bdcd8170SKalle Valo 38bdcd8170SKalle Valo /* available bus requests */ 39bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo struct ath6kl *ar; 42bdcd8170SKalle Valo u8 *dma_buffer; 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo /* scatter request list head */ 45bdcd8170SKalle Valo struct list_head scat_req; 46bdcd8170SKalle Valo 47bdcd8170SKalle Valo spinlock_t scat_lock; 4832a07e44SKalle Valo bool scatter_enabled; 4932a07e44SKalle Valo 50bdcd8170SKalle Valo bool is_disabled; 51bdcd8170SKalle Valo atomic_t irq_handling; 52bdcd8170SKalle Valo const struct sdio_device_id *id; 53bdcd8170SKalle Valo struct work_struct wr_async_work; 54bdcd8170SKalle Valo struct list_head wr_asyncq; 55bdcd8170SKalle Valo spinlock_t wr_async_lock; 56bdcd8170SKalle Valo }; 57bdcd8170SKalle Valo 58bdcd8170SKalle Valo #define CMD53_ARG_READ 0 59bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1 60bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1 61bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0 62bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1 63bdcd8170SKalle Valo 64bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 65bdcd8170SKalle Valo { 66bdcd8170SKalle Valo return ar->hif_priv; 67bdcd8170SKalle Valo } 68bdcd8170SKalle Valo 69bdcd8170SKalle Valo /* 70bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able. 71bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will 72bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 73bdcd8170SKalle Valo * check fails on stack memory. 74bdcd8170SKalle Valo */ 75bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf) 76bdcd8170SKalle Valo { 77bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 78bdcd8170SKalle Valo } 79bdcd8170SKalle Valo 80bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 81bdcd8170SKalle Valo { 82bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 83bdcd8170SKalle Valo 84bdcd8170SKalle Valo /* EP1 has an extended range */ 85bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 86bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 87bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 88bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 89bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 90bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 91bdcd8170SKalle Valo } 92bdcd8170SKalle Valo 93bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 94bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr, 95bdcd8170SKalle Valo u16 blksz) 96bdcd8170SKalle Valo { 97bdcd8170SKalle Valo *arg = (((rw & 1) << 31) | 98bdcd8170SKalle Valo ((func & 0x7) << 28) | 99bdcd8170SKalle Valo ((mode & 1) << 27) | 100bdcd8170SKalle Valo ((opcode & 1) << 26) | 101bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) | 102bdcd8170SKalle Valo (blksz & 0x1FF)); 103bdcd8170SKalle Valo } 104bdcd8170SKalle Valo 105bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 106bdcd8170SKalle Valo unsigned int address, 107bdcd8170SKalle Valo unsigned char val) 108bdcd8170SKalle Valo { 109bdcd8170SKalle Valo const u8 func = 0; 110bdcd8170SKalle Valo 111bdcd8170SKalle Valo *arg = ((write & 1) << 31) | 112bdcd8170SKalle Valo ((func & 0x7) << 28) | 113bdcd8170SKalle Valo ((raw & 1) << 27) | 114bdcd8170SKalle Valo (1 << 26) | 115bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) | 116bdcd8170SKalle Valo (1 << 8) | 117bdcd8170SKalle Valo (val & 0xFF); 118bdcd8170SKalle Valo } 119bdcd8170SKalle Valo 120bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 121bdcd8170SKalle Valo unsigned int address, 122bdcd8170SKalle Valo unsigned char byte) 123bdcd8170SKalle Valo { 124bdcd8170SKalle Valo struct mmc_command io_cmd; 125bdcd8170SKalle Valo 126bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd)); 127bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 128bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT; 129bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 130bdcd8170SKalle Valo 131bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0); 132bdcd8170SKalle Valo } 133bdcd8170SKalle Valo 134da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 135da220695SVasanthakumar Thiagarajan u8 *buf, u32 len) 136da220695SVasanthakumar Thiagarajan { 137da220695SVasanthakumar Thiagarajan int ret = 0; 138da220695SVasanthakumar Thiagarajan 139861dd058SVasanthakumar Thiagarajan sdio_claim_host(func); 140861dd058SVasanthakumar Thiagarajan 141da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) { 142f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */ 143da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR && 144da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR) 145da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len); 146da220695SVasanthakumar Thiagarajan 147f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */ 148da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR) 149da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len; 150da220695SVasanthakumar Thiagarajan 151da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 152da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len); 153da220695SVasanthakumar Thiagarajan else 154da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len); 155da220695SVasanthakumar Thiagarajan } else { 156da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 157da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len); 158da220695SVasanthakumar Thiagarajan else 159da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len); 160da220695SVasanthakumar Thiagarajan } 161da220695SVasanthakumar Thiagarajan 162861dd058SVasanthakumar Thiagarajan sdio_release_host(func); 163861dd058SVasanthakumar Thiagarajan 164f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 165f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr, 166f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 167f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 168f7325b85SKalle Valo 169da220695SVasanthakumar Thiagarajan return ret; 170da220695SVasanthakumar Thiagarajan } 171da220695SVasanthakumar Thiagarajan 172bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 173bdcd8170SKalle Valo { 174bdcd8170SKalle Valo struct bus_request *bus_req; 175bdcd8170SKalle Valo 176151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 177bdcd8170SKalle Valo 178bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) { 179151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 180bdcd8170SKalle Valo return NULL; 181bdcd8170SKalle Valo } 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 184bdcd8170SKalle Valo struct bus_request, list); 185bdcd8170SKalle Valo list_del(&bus_req->list); 186bdcd8170SKalle Valo 187151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 188f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 189f7325b85SKalle Valo __func__, bus_req); 190bdcd8170SKalle Valo 191bdcd8170SKalle Valo return bus_req; 192bdcd8170SKalle Valo } 193bdcd8170SKalle Valo 194bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 195bdcd8170SKalle Valo struct bus_request *bus_req) 196bdcd8170SKalle Valo { 197f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 198f7325b85SKalle Valo __func__, bus_req); 199bdcd8170SKalle Valo 200151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 201bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 202151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 203bdcd8170SKalle Valo } 204bdcd8170SKalle Valo 205bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 206bdcd8170SKalle Valo struct mmc_data *data) 207bdcd8170SKalle Valo { 208bdcd8170SKalle Valo struct scatterlist *sg; 209bdcd8170SKalle Valo int i; 210bdcd8170SKalle Valo 211bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE; 212bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 213bdcd8170SKalle Valo 214bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, 215bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 216bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 217bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len, 218bdcd8170SKalle Valo scat_req->scat_entries); 219bdcd8170SKalle Valo 220bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 221bdcd8170SKalle Valo MMC_DATA_READ; 222bdcd8170SKalle Valo 223bdcd8170SKalle Valo /* fill SG entries */ 224d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries; 225bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries); 226bdcd8170SKalle Valo 227bdcd8170SKalle Valo /* assemble SG list */ 228bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) { 229bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 230bdcd8170SKalle Valo i, scat_req->scat_list[i].buf, 231bdcd8170SKalle Valo scat_req->scat_list[i].len); 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf, 234bdcd8170SKalle Valo scat_req->scat_list[i].len); 235bdcd8170SKalle Valo } 236bdcd8170SKalle Valo 237bdcd8170SKalle Valo /* set scatter-gather table for request */ 238d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries; 239bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries; 240bdcd8170SKalle Valo } 241bdcd8170SKalle Valo 242bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 243bdcd8170SKalle Valo struct bus_request *req) 244bdcd8170SKalle Valo { 245bdcd8170SKalle Valo struct mmc_request mmc_req; 246bdcd8170SKalle Valo struct mmc_command cmd; 247bdcd8170SKalle Valo struct mmc_data data; 248bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 249bdcd8170SKalle Valo u8 opcode, rw; 250348a8fbcSVasanthakumar Thiagarajan int status, len; 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo scat_req = req->scat_req; 253bdcd8170SKalle Valo 254348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) { 255348a8fbcSVasanthakumar Thiagarajan len = scat_req->len; 256348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS) 257348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE); 258348a8fbcSVasanthakumar Thiagarajan 259348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 260348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf, 261348a8fbcSVasanthakumar Thiagarajan len); 262348a8fbcSVasanthakumar Thiagarajan goto scat_complete; 263348a8fbcSVasanthakumar Thiagarajan } 264348a8fbcSVasanthakumar Thiagarajan 265bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request)); 266bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command)); 267bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data)); 268bdcd8170SKalle Valo 269d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data); 270bdcd8170SKalle Valo 271bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 272bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */ 277bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) { 278bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR) 279bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 280bdcd8170SKalle Valo else 281bdcd8170SKalle Valo /* Uses extended address range */ 282bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 283bdcd8170SKalle Valo } 284bdcd8170SKalle Valo 285bdcd8170SKalle Valo /* set command argument */ 286bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 287bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 288bdcd8170SKalle Valo data.blocks); 289bdcd8170SKalle Valo 290bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED; 291bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 292bdcd8170SKalle Valo 293bdcd8170SKalle Valo mmc_req.cmd = &cmd; 294bdcd8170SKalle Valo mmc_req.data = &data; 295bdcd8170SKalle Valo 296861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func); 297861dd058SVasanthakumar Thiagarajan 298bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card); 299bdcd8170SKalle Valo /* synchronous call to process request */ 300bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 301bdcd8170SKalle Valo 302861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func); 303861dd058SVasanthakumar Thiagarajan 304bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error; 305348a8fbcSVasanthakumar Thiagarajan 306348a8fbcSVasanthakumar Thiagarajan scat_complete: 307bdcd8170SKalle Valo scat_req->status = status; 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo if (scat_req->status) 310bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n", 311bdcd8170SKalle Valo scat_req->status); 312bdcd8170SKalle Valo 313bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS) 314e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req); 315bdcd8170SKalle Valo 316bdcd8170SKalle Valo return status; 317bdcd8170SKalle Valo } 318bdcd8170SKalle Valo 3193df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 3203df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req, 3213df505adSVasanthakumar Thiagarajan bool virt_scat) 3223df505adSVasanthakumar Thiagarajan { 3233df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req; 3243df505adSVasanthakumar Thiagarajan struct bus_request *bus_req; 325cfeab10bSVasanthakumar Thiagarajan int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz; 326cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf; 3273df505adSVasanthakumar Thiagarajan 3283df505adSVasanthakumar Thiagarajan scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 3293df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz; 3303df505adSVasanthakumar Thiagarajan 3313df505adSVasanthakumar Thiagarajan if (!virt_scat) 3323df505adSVasanthakumar Thiagarajan sg_sz = sizeof(struct scatterlist) * n_scat_entry; 333cfeab10bSVasanthakumar Thiagarajan else 334cfeab10bSVasanthakumar Thiagarajan buf_sz = 2 * L1_CACHE_BYTES + 335cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 3363df505adSVasanthakumar Thiagarajan 3373df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) { 3383df505adSVasanthakumar Thiagarajan /* allocate the scatter request */ 3393df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL); 3403df505adSVasanthakumar Thiagarajan if (!s_req) 3413df505adSVasanthakumar Thiagarajan return -ENOMEM; 3423df505adSVasanthakumar Thiagarajan 343cfeab10bSVasanthakumar Thiagarajan if (virt_scat) { 344cfeab10bSVasanthakumar Thiagarajan virt_buf = kzalloc(buf_sz, GFP_KERNEL); 345cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) { 346cfeab10bSVasanthakumar Thiagarajan kfree(s_req); 347cfeab10bSVasanthakumar Thiagarajan return -ENOMEM; 348cfeab10bSVasanthakumar Thiagarajan } 349cfeab10bSVasanthakumar Thiagarajan 350cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf = 351cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 352cfeab10bSVasanthakumar Thiagarajan } else { 3533df505adSVasanthakumar Thiagarajan /* allocate sglist */ 3543df505adSVasanthakumar Thiagarajan s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL); 3553df505adSVasanthakumar Thiagarajan 3563df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) { 3573df505adSVasanthakumar Thiagarajan kfree(s_req); 3583df505adSVasanthakumar Thiagarajan return -ENOMEM; 3593df505adSVasanthakumar Thiagarajan } 3603df505adSVasanthakumar Thiagarajan } 3613df505adSVasanthakumar Thiagarajan 3623df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */ 3633df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 3643df505adSVasanthakumar Thiagarajan if (!bus_req) { 3653df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries); 366cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 3673df505adSVasanthakumar Thiagarajan kfree(s_req); 3683df505adSVasanthakumar Thiagarajan return -ENOMEM; 3693df505adSVasanthakumar Thiagarajan } 3703df505adSVasanthakumar Thiagarajan 3713df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */ 3723df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req; 3733df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req; 3743df505adSVasanthakumar Thiagarajan 3754a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat; 3764a005c3eSVasanthakumar Thiagarajan 3773df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */ 3783df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req); 3793df505adSVasanthakumar Thiagarajan } 3803df505adSVasanthakumar Thiagarajan 3813df505adSVasanthakumar Thiagarajan return 0; 3823df505adSVasanthakumar Thiagarajan } 3833df505adSVasanthakumar Thiagarajan 384bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 385bdcd8170SKalle Valo u32 len, u32 request) 386bdcd8170SKalle Valo { 387bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 388bdcd8170SKalle Valo u8 *tbuf = NULL; 389bdcd8170SKalle Valo int ret; 390bdcd8170SKalle Valo bool bounced = false; 391bdcd8170SKalle Valo 392bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS) 393bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE); 394bdcd8170SKalle Valo 395bdcd8170SKalle Valo if (buf_needs_bounce(buf)) { 396bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) 397bdcd8170SKalle Valo return -ENOMEM; 398bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer; 399bdcd8170SKalle Valo memcpy(tbuf, buf, len); 400bdcd8170SKalle Valo bounced = true; 401bdcd8170SKalle Valo } else 402bdcd8170SKalle Valo tbuf = buf; 403bdcd8170SKalle Valo 404da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 405da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced) 406bdcd8170SKalle Valo memcpy(buf, tbuf, len); 407bdcd8170SKalle Valo 408bdcd8170SKalle Valo return ret; 409bdcd8170SKalle Valo } 410bdcd8170SKalle Valo 411bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 412bdcd8170SKalle Valo struct bus_request *req) 413bdcd8170SKalle Valo { 414bdcd8170SKalle Valo if (req->scat_req) 415bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req); 416bdcd8170SKalle Valo else { 417bdcd8170SKalle Valo void *context; 418bdcd8170SKalle Valo int status; 419bdcd8170SKalle Valo 420bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 421bdcd8170SKalle Valo req->buffer, req->length, 422bdcd8170SKalle Valo req->request); 423bdcd8170SKalle Valo context = req->packet; 424bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 4258e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status); 426bdcd8170SKalle Valo } 427bdcd8170SKalle Valo } 428bdcd8170SKalle Valo 429bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work) 430bdcd8170SKalle Valo { 431bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 432bdcd8170SKalle Valo struct bus_request *req, *tmp_req; 433bdcd8170SKalle Valo 434bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 435bdcd8170SKalle Valo 436151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 437bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 438bdcd8170SKalle Valo list_del(&req->list); 439151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 440bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req); 441151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 442bdcd8170SKalle Valo } 443151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 444bdcd8170SKalle Valo } 445bdcd8170SKalle Valo 446bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func) 447bdcd8170SKalle Valo { 448bdcd8170SKalle Valo int status; 449bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 450bdcd8170SKalle Valo 451f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 452f7325b85SKalle Valo 453bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 454bdcd8170SKalle Valo atomic_set(&ar_sdio->irq_handling, 1); 455bdcd8170SKalle Valo 456bdcd8170SKalle Valo /* 457bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when 458bdcd8170SKalle Valo * we process commands. 459bdcd8170SKalle Valo */ 460bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 461bdcd8170SKalle Valo 4628e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 463bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 464bdcd8170SKalle Valo atomic_set(&ar_sdio->irq_handling, 0); 465bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED); 466bdcd8170SKalle Valo } 467bdcd8170SKalle Valo 468b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar) 469bdcd8170SKalle Valo { 470b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 471bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func; 472bdcd8170SKalle Valo int ret = 0; 473bdcd8170SKalle Valo 474bdcd8170SKalle Valo if (!ar_sdio->is_disabled) 475bdcd8170SKalle Valo return 0; 476bdcd8170SKalle Valo 4773ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 4783ef987beSKalle Valo 479bdcd8170SKalle Valo sdio_claim_host(func); 480bdcd8170SKalle Valo 481bdcd8170SKalle Valo ret = sdio_enable_func(func); 482bdcd8170SKalle Valo if (ret) { 483bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret); 484bdcd8170SKalle Valo sdio_release_host(func); 485bdcd8170SKalle Valo return ret; 486bdcd8170SKalle Valo } 487bdcd8170SKalle Valo 488bdcd8170SKalle Valo sdio_release_host(func); 489bdcd8170SKalle Valo 490bdcd8170SKalle Valo /* 491bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than 492bdcd8170SKalle Valo * 10 ms but let's be conservative here. 493bdcd8170SKalle Valo */ 494bdcd8170SKalle Valo msleep(10); 495bdcd8170SKalle Valo 496bdcd8170SKalle Valo ar_sdio->is_disabled = false; 497bdcd8170SKalle Valo 498bdcd8170SKalle Valo return ret; 499bdcd8170SKalle Valo } 500bdcd8170SKalle Valo 501b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar) 502bdcd8170SKalle Valo { 503b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 504bdcd8170SKalle Valo int ret; 505bdcd8170SKalle Valo 506bdcd8170SKalle Valo if (ar_sdio->is_disabled) 507bdcd8170SKalle Valo return 0; 508bdcd8170SKalle Valo 5093ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 5103ef987beSKalle Valo 511bdcd8170SKalle Valo /* Disable the card */ 512bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 513bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func); 514bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 515bdcd8170SKalle Valo 516bdcd8170SKalle Valo if (ret) 517bdcd8170SKalle Valo return ret; 518bdcd8170SKalle Valo 519bdcd8170SKalle Valo ar_sdio->is_disabled = true; 520bdcd8170SKalle Valo 521bdcd8170SKalle Valo return ret; 522bdcd8170SKalle Valo } 523bdcd8170SKalle Valo 524bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 525bdcd8170SKalle Valo u32 length, u32 request, 526bdcd8170SKalle Valo struct htc_packet *packet) 527bdcd8170SKalle Valo { 528bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 529bdcd8170SKalle Valo struct bus_request *bus_req; 530bdcd8170SKalle Valo 531bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 532bdcd8170SKalle Valo 533bdcd8170SKalle Valo if (!bus_req) 534bdcd8170SKalle Valo return -ENOMEM; 535bdcd8170SKalle Valo 536bdcd8170SKalle Valo bus_req->address = address; 537bdcd8170SKalle Valo bus_req->buffer = buffer; 538bdcd8170SKalle Valo bus_req->length = length; 539bdcd8170SKalle Valo bus_req->request = request; 540bdcd8170SKalle Valo bus_req->packet = packet; 541bdcd8170SKalle Valo 542151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 543bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 544151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 545bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 546bdcd8170SKalle Valo 547bdcd8170SKalle Valo return 0; 548bdcd8170SKalle Valo } 549bdcd8170SKalle Valo 550bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 551bdcd8170SKalle Valo { 552bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 553bdcd8170SKalle Valo int ret; 554bdcd8170SKalle Valo 555bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 556bdcd8170SKalle Valo 557bdcd8170SKalle Valo /* Register the isr */ 558bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 559bdcd8170SKalle Valo if (ret) 560bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret); 561bdcd8170SKalle Valo 562bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 563bdcd8170SKalle Valo } 564bdcd8170SKalle Valo 565bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 566bdcd8170SKalle Valo { 567bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 568bdcd8170SKalle Valo int ret; 569bdcd8170SKalle Valo 570bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 571bdcd8170SKalle Valo 572bdcd8170SKalle Valo /* Mask our function IRQ */ 573bdcd8170SKalle Valo while (atomic_read(&ar_sdio->irq_handling)) { 574bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 575bdcd8170SKalle Valo schedule_timeout(HZ / 10); 576bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 577bdcd8170SKalle Valo } 578bdcd8170SKalle Valo 579bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func); 580bdcd8170SKalle Valo if (ret) 581bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret); 582bdcd8170SKalle Valo 583bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 584bdcd8170SKalle Valo } 585bdcd8170SKalle Valo 586bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 587bdcd8170SKalle Valo { 588bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 589bdcd8170SKalle Valo struct hif_scatter_req *node = NULL; 590bdcd8170SKalle Valo 591151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 592bdcd8170SKalle Valo 593bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) { 594bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req, 595bdcd8170SKalle Valo struct hif_scatter_req, list); 596bdcd8170SKalle Valo list_del(&node->list); 597bdcd8170SKalle Valo } 598bdcd8170SKalle Valo 599151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 600bdcd8170SKalle Valo 601bdcd8170SKalle Valo return node; 602bdcd8170SKalle Valo } 603bdcd8170SKalle Valo 604bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 605bdcd8170SKalle Valo struct hif_scatter_req *s_req) 606bdcd8170SKalle Valo { 607bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 608bdcd8170SKalle Valo 609151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 610bdcd8170SKalle Valo 611bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req); 612bdcd8170SKalle Valo 613151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 614bdcd8170SKalle Valo 615bdcd8170SKalle Valo } 616bdcd8170SKalle Valo 617c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */ 618c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 619c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req) 620c630d18aSVasanthakumar Thiagarajan { 621c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 622c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req; 623c630d18aSVasanthakumar Thiagarajan int status = 0; 624c630d18aSVasanthakumar Thiagarajan 625c630d18aSVasanthakumar Thiagarajan if (!scat_req->len) 626c630d18aSVasanthakumar Thiagarajan return -EINVAL; 627c630d18aSVasanthakumar Thiagarajan 628c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER, 629c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n", 630c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries); 631c630d18aSVasanthakumar Thiagarajan 632861dd058SVasanthakumar Thiagarajan if (request & HIF_SYNCHRONOUS) 633d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 634861dd058SVasanthakumar Thiagarajan else { 635151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 636d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 637151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 638c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 639c630d18aSVasanthakumar Thiagarajan } 640c630d18aSVasanthakumar Thiagarajan 641c630d18aSVasanthakumar Thiagarajan return status; 642c630d18aSVasanthakumar Thiagarajan } 643c630d18aSVasanthakumar Thiagarajan 64418a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */ 64518a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 64618a0f93eSVasanthakumar Thiagarajan { 64718a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 64818a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req; 64918a0f93eSVasanthakumar Thiagarajan 65018a0f93eSVasanthakumar Thiagarajan /* empty the free list */ 651151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 65218a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 65318a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list); 654151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 65518a0f93eSVasanthakumar Thiagarajan 65632a07e44SKalle Valo /* 65732a07e44SKalle Valo * FIXME: should we also call completion handler with 65832a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 65932a07e44SKalle Valo * that the packet is properly freed? 66032a07e44SKalle Valo */ 66118a0f93eSVasanthakumar Thiagarajan if (s_req->busrequest) 66218a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 66318a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 66418a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries); 66518a0f93eSVasanthakumar Thiagarajan kfree(s_req); 66618a0f93eSVasanthakumar Thiagarajan 667151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 66818a0f93eSVasanthakumar Thiagarajan } 669151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 67018a0f93eSVasanthakumar Thiagarajan } 67118a0f93eSVasanthakumar Thiagarajan 67218a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */ 67350745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 67418a0f93eSVasanthakumar Thiagarajan { 67518a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 67650745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target; 677cfeab10bSVasanthakumar Thiagarajan int ret; 678cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false; 67918a0f93eSVasanthakumar Thiagarajan 68032a07e44SKalle Valo if (ar_sdio->scatter_enabled) 68132a07e44SKalle Valo return 0; 68232a07e44SKalle Valo 68332a07e44SKalle Valo ar_sdio->scatter_enabled = true; 68432a07e44SKalle Valo 68518a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */ 68618a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 687cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 68818a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs, 68918a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 690cfeab10bSVasanthakumar Thiagarajan virt_scat = true; 69118a0f93eSVasanthakumar Thiagarajan } 69218a0f93eSVasanthakumar Thiagarajan 693cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) { 69418a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 69518a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ, 696cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat); 697cfeab10bSVasanthakumar Thiagarajan 698cfeab10bSVasanthakumar Thiagarajan if (!ret) { 6993ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7003ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n", 701cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, 702cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 703cfeab10bSVasanthakumar Thiagarajan 70450745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 70550745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 706cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE; 707cfeab10bSVasanthakumar Thiagarajan } else { 708cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 709cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 710cfeab10bSVasanthakumar Thiagarajan } 711cfeab10bSVasanthakumar Thiagarajan } 712cfeab10bSVasanthakumar Thiagarajan 713cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) { 714cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 715cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ, 716cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat); 717cfeab10bSVasanthakumar Thiagarajan 71818a0f93eSVasanthakumar Thiagarajan if (ret) { 719cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n"); 72018a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 72118a0f93eSVasanthakumar Thiagarajan return ret; 72218a0f93eSVasanthakumar Thiagarajan } 72318a0f93eSVasanthakumar Thiagarajan 7243ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7253ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n", 726cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 727cfeab10bSVasanthakumar Thiagarajan 72850745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 72950745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 730cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 731cfeab10bSVasanthakumar Thiagarajan } 732cfeab10bSVasanthakumar Thiagarajan 73318a0f93eSVasanthakumar Thiagarajan return 0; 73418a0f93eSVasanthakumar Thiagarajan } 73518a0f93eSVasanthakumar Thiagarajan 736e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar) 737e28e8104SKalle Valo { 738e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 739e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func; 740e28e8104SKalle Valo int ret; 741e28e8104SKalle Valo 742e28e8104SKalle Valo sdio_claim_host(func); 743e28e8104SKalle Valo 744e28e8104SKalle Valo if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 745e28e8104SKalle Valo MANUFACTURER_ID_AR6003_BASE) { 746e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */ 747e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 748e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG, 749e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 750e28e8104SKalle Valo if (ret) { 751e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 752e28e8104SKalle Valo ret); 753e28e8104SKalle Valo goto out; 754e28e8104SKalle Valo } 755e28e8104SKalle Valo 756e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 757e28e8104SKalle Valo } 758e28e8104SKalle Valo 759e28e8104SKalle Valo /* give us some time to enable, in ms */ 760e28e8104SKalle Valo func->enable_timeout = 100; 761e28e8104SKalle Valo 762e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 763e28e8104SKalle Valo if (ret) { 764e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n", 765e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret); 766e28e8104SKalle Valo sdio_release_host(func); 767e28e8104SKalle Valo goto out; 768e28e8104SKalle Valo } 769e28e8104SKalle Valo 770e28e8104SKalle Valo out: 771e28e8104SKalle Valo sdio_release_host(func); 772e28e8104SKalle Valo 773e28e8104SKalle Valo return ret; 774e28e8104SKalle Valo } 775e28e8104SKalle Valo 7760f60e9f4SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 777abcb344bSKalle Valo { 778abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 779abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func; 780abcb344bSKalle Valo mmc_pm_flag_t flags; 781abcb344bSKalle Valo int ret; 782abcb344bSKalle Valo 783abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func); 784abcb344bSKalle Valo 785b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 786b4b2a0b1SKalle Valo 7878277de15SKalle Valo if (!(flags & MMC_PM_KEEP_POWER) || 7888277de15SKalle Valo (ar->conf_flags & ATH6KL_CONF_SUSPEND_CUTPOWER)) { 789b4b2a0b1SKalle Valo /* as host doesn't support keep power we need to cut power */ 7900f60e9f4SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, 7910f60e9f4SRaja Mani NULL); 79217380859SSam Leffler } 793abcb344bSKalle Valo 794abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 795abcb344bSKalle Valo if (ret) { 796abcb344bSKalle Valo printk(KERN_ERR "ath6kl: set sdio pm flags failed: %d\n", 797abcb344bSKalle Valo ret); 798abcb344bSKalle Valo return ret; 799abcb344bSKalle Valo } 800abcb344bSKalle Valo 801d7c44e0bSRaja Mani if ((flags & MMC_PM_WAKE_SDIO_IRQ) && wow) { 802d7c44e0bSRaja Mani /* 803d7c44e0bSRaja Mani * The host sdio controller is capable of keep power and 804d7c44e0bSRaja Mani * sdio irq wake up at this point. It's fine to continue 805d7c44e0bSRaja Mani * wow suspend operation. 806d7c44e0bSRaja Mani */ 807d7c44e0bSRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 808d7c44e0bSRaja Mani if (ret) 809d7c44e0bSRaja Mani return ret; 810d7c44e0bSRaja Mani 811d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 812d7c44e0bSRaja Mani if (ret) 813d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 814d7c44e0bSRaja Mani 815d7c44e0bSRaja Mani return ret; 816d7c44e0bSRaja Mani } 817d7c44e0bSRaja Mani 8180f60e9f4SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, NULL); 819abcb344bSKalle Valo } 820abcb344bSKalle Valo 821aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar) 822aa6cffc1SChilam Ng { 823b4b2a0b1SKalle Valo switch (ar->state) { 824b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF: 825b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER: 826b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, 827b4b2a0b1SKalle Valo "sdio resume configuring sdio\n"); 828b4b2a0b1SKalle Valo 829b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */ 830b4b2a0b1SKalle Valo ath6kl_sdio_config(ar); 831b4b2a0b1SKalle Valo break; 832b4b2a0b1SKalle Valo 833b4b2a0b1SKalle Valo case ATH6KL_STATE_ON: 834b4b2a0b1SKalle Valo break; 835b4b2a0b1SKalle Valo 836b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP: 837b4b2a0b1SKalle Valo break; 838d7c44e0bSRaja Mani 839d7c44e0bSRaja Mani case ATH6KL_STATE_WOW: 840d7c44e0bSRaja Mani break; 841b4b2a0b1SKalle Valo } 842b4b2a0b1SKalle Valo 84352d81a68SKalle Valo ath6kl_cfg80211_resume(ar); 844aa6cffc1SChilam Ng 845aa6cffc1SChilam Ng return 0; 846aa6cffc1SChilam Ng } 847aa6cffc1SChilam Ng 84866b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 84966b693c3SKalle Valo { 85066b693c3SKalle Valo u32 addr; 85166b693c3SKalle Valo unsigned long timeout; 85266b693c3SKalle Valo int ret; 85366b693c3SKalle Valo 85466b693c3SKalle Valo ar->bmi.cmd_credits = 0; 85566b693c3SKalle Valo 85666b693c3SKalle Valo /* Read the counter register to get the command credits */ 85766b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 85866b693c3SKalle Valo 85966b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 86066b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 86166b693c3SKalle Valo 86266b693c3SKalle Valo /* 86366b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte 86466b693c3SKalle Valo * read will hit the counter and cause a decrement, while the 86566b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this 86666b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned. 86766b693c3SKalle Valo */ 86866b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, 86966b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4, 87066b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 87166b693c3SKalle Valo if (ret) { 87266b693c3SKalle Valo ath6kl_err("Unable to decrement the command credit " 87366b693c3SKalle Valo "count register: %d\n", ret); 87466b693c3SKalle Valo return ret; 87566b693c3SKalle Valo } 87666b693c3SKalle Valo 87766b693c3SKalle Valo /* The counter is only 8 bits. 87866b693c3SKalle Valo * Ignore anything in the upper 3 bytes 87966b693c3SKalle Valo */ 88066b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF; 88166b693c3SKalle Valo } 88266b693c3SKalle Valo 88366b693c3SKalle Valo if (!ar->bmi.cmd_credits) { 88466b693c3SKalle Valo ath6kl_err("bmi communication timeout\n"); 88566b693c3SKalle Valo return -ETIMEDOUT; 88666b693c3SKalle Valo } 88766b693c3SKalle Valo 88866b693c3SKalle Valo return 0; 88966b693c3SKalle Valo } 89066b693c3SKalle Valo 89166b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 89266b693c3SKalle Valo { 89366b693c3SKalle Valo unsigned long timeout; 89466b693c3SKalle Valo u32 rx_word = 0; 89566b693c3SKalle Valo int ret = 0; 89666b693c3SKalle Valo 89766b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 89866b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) { 89966b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, 90066b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS, 90166b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word), 90266b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 90366b693c3SKalle Valo if (ret) { 90466b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 90566b693c3SKalle Valo return ret; 90666b693c3SKalle Valo } 90766b693c3SKalle Valo 90866b693c3SKalle Valo /* all we really want is one bit */ 90966b693c3SKalle Valo rx_word &= (1 << ENDPOINT1); 91066b693c3SKalle Valo } 91166b693c3SKalle Valo 91266b693c3SKalle Valo if (!rx_word) { 91366b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n"); 91466b693c3SKalle Valo return -EINVAL; 91566b693c3SKalle Valo } 91666b693c3SKalle Valo 91766b693c3SKalle Valo return ret; 91866b693c3SKalle Valo } 91966b693c3SKalle Valo 92066b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 92166b693c3SKalle Valo { 92266b693c3SKalle Valo int ret; 92366b693c3SKalle Valo u32 addr; 92466b693c3SKalle Valo 92566b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar); 92666b693c3SKalle Valo if (ret) 92766b693c3SKalle Valo return ret; 92866b693c3SKalle Valo 92966b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 93066b693c3SKalle Valo 93166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 93266b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC); 93366b693c3SKalle Valo if (ret) 93466b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n"); 93566b693c3SKalle Valo 93666b693c3SKalle Valo return ret; 93766b693c3SKalle Valo } 93866b693c3SKalle Valo 93966b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 94066b693c3SKalle Valo { 94166b693c3SKalle Valo int ret; 94266b693c3SKalle Valo u32 addr; 94366b693c3SKalle Valo 94466b693c3SKalle Valo /* 94566b693c3SKalle Valo * During normal bootup, small reads may be required. 94666b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target 94766b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until 94866b693c3SKalle Valo * we know that response data is available. 94966b693c3SKalle Valo * 95066b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected 95166b693c3SKalle Valo * Target failure rather than risk problems at the HIF level. 95266b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage 95366b693c3SKalle Valo * data on some host controllers. And on an interconnect 95466b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which 95566b693c3SKalle Valo * does not provide any indication on data timeout, it avoids 95666b693c3SKalle Valo * a potential hang or garbage response. 95766b693c3SKalle Valo * 95866b693c3SKalle Valo * Synchronization is more difficult for reads larger than the 95966b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable 96066b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an 96166b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the 96266b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is 96366b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do 96466b693c3SKalle Valo * not occur in practice -- they're supported for debug/development. 96566b693c3SKalle Valo * 96666b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases: 96766b693c3SKalle Valo * CASE 1: length < 4 96866b693c3SKalle Valo * Should not happen 96966b693c3SKalle Valo * 97066b693c3SKalle Valo * CASE 2: 4 <= length <= 128 97166b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO 97266b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for 97366b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE 97466b693c3SKalle Valo * response is available in the the FIFO 97566b693c3SKalle Valo * 97666b693c3SKalle Valo * CASE 3: length > 128 97766b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO 97866b693c3SKalle Valo * 97966b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will 98066b693c3SKalle Valo * usually see a response quickly; but there may be some unusual 98166b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout. 98266b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for 98366b693c3SKalle Valo * BMI_EXECUTE. 98466b693c3SKalle Valo * 98566b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution, 98666b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep 98766b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 98866b693c3SKalle Valo * a function of Host processor speed. 98966b693c3SKalle Valo */ 99066b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */ 99166b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar); 99266b693c3SKalle Valo if (ret) 99366b693c3SKalle Valo return ret; 99466b693c3SKalle Valo } 99566b693c3SKalle Valo 99666b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 99766b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 99866b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 99966b693c3SKalle Valo if (ret) { 100066b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n", 100166b693c3SKalle Valo ret); 100266b693c3SKalle Valo return ret; 100366b693c3SKalle Valo } 100466b693c3SKalle Valo 100566b693c3SKalle Valo return 0; 100666b693c3SKalle Valo } 100766b693c3SKalle Valo 100832a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar) 100932a07e44SKalle Valo { 101032a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 101132a07e44SKalle Valo struct bus_request *req, *tmp_req; 101232a07e44SKalle Valo void *context; 101332a07e44SKalle Valo 101432a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */ 101532a07e44SKalle Valo 101632a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 101732a07e44SKalle Valo 101832a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock); 101932a07e44SKalle Valo 102032a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 102132a07e44SKalle Valo list_del(&req->list); 102232a07e44SKalle Valo 102332a07e44SKalle Valo if (req->scat_req) { 102432a07e44SKalle Valo /* this is a scatter gather request */ 102532a07e44SKalle Valo req->scat_req->status = -ECANCELED; 102632a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target, 102732a07e44SKalle Valo req->scat_req); 102832a07e44SKalle Valo } else { 102932a07e44SKalle Valo context = req->packet; 103032a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 103132a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED); 103232a07e44SKalle Valo } 103332a07e44SKalle Valo } 103432a07e44SKalle Valo 103532a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock); 103632a07e44SKalle Valo 103732a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 103832a07e44SKalle Valo } 103932a07e44SKalle Valo 1040bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1041bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync, 1042bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async, 1043bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable, 1044bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable, 1045bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get, 1046bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add, 1047bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter, 1048f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1049bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1050abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend, 1051aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume, 105266b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read, 105366b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write, 1054b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on, 1055b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off, 105632a07e44SKalle Valo .stop = ath6kl_sdio_stop, 1057bdcd8170SKalle Valo }; 1058bdcd8170SKalle Valo 1059b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP 1060b4b2a0b1SKalle Valo 1061b4b2a0b1SKalle Valo /* 1062b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during 1063b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers. 1064b4b2a0b1SKalle Valo */ 1065b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device) 1066b4b2a0b1SKalle Valo { 1067b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1068b4b2a0b1SKalle Valo 1069b4b2a0b1SKalle Valo return 0; 1070b4b2a0b1SKalle Valo } 1071b4b2a0b1SKalle Valo 1072b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device) 1073b4b2a0b1SKalle Valo { 1074b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1075b4b2a0b1SKalle Valo 1076b4b2a0b1SKalle Valo return 0; 1077b4b2a0b1SKalle Valo } 1078b4b2a0b1SKalle Valo 1079b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1080b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume); 1081b4b2a0b1SKalle Valo 1082b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1083b4b2a0b1SKalle Valo 1084b4b2a0b1SKalle Valo #else 1085b4b2a0b1SKalle Valo 1086b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL 1087b4b2a0b1SKalle Valo 1088b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */ 1089b4b2a0b1SKalle Valo 1090bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func, 1091bdcd8170SKalle Valo const struct sdio_device_id *id) 1092bdcd8170SKalle Valo { 1093bdcd8170SKalle Valo int ret; 1094bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1095bdcd8170SKalle Valo struct ath6kl *ar; 1096bdcd8170SKalle Valo int count; 1097bdcd8170SKalle Valo 10983ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 10993ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1100f7325b85SKalle Valo func->num, func->vendor, func->device, 1101f7325b85SKalle Valo func->max_blksize, func->cur_blksize); 1102bdcd8170SKalle Valo 1103bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1104bdcd8170SKalle Valo if (!ar_sdio) 1105bdcd8170SKalle Valo return -ENOMEM; 1106bdcd8170SKalle Valo 1107bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1108bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) { 1109bdcd8170SKalle Valo ret = -ENOMEM; 1110bdcd8170SKalle Valo goto err_hif; 1111bdcd8170SKalle Valo } 1112bdcd8170SKalle Valo 1113bdcd8170SKalle Valo ar_sdio->func = func; 1114bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio); 1115bdcd8170SKalle Valo 1116bdcd8170SKalle Valo ar_sdio->id = id; 1117bdcd8170SKalle Valo ar_sdio->is_disabled = true; 1118bdcd8170SKalle Valo 1119bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock); 1120bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock); 1121bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock); 1122bdcd8170SKalle Valo 1123bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req); 1124bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1125bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1126bdcd8170SKalle Valo 1127bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1128bdcd8170SKalle Valo 1129bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1130bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1131bdcd8170SKalle Valo 1132bdcd8170SKalle Valo ar = ath6kl_core_alloc(&ar_sdio->func->dev); 1133bdcd8170SKalle Valo if (!ar) { 1134bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n"); 1135bdcd8170SKalle Valo ret = -ENOMEM; 1136bdcd8170SKalle Valo goto err_dma; 1137bdcd8170SKalle Valo } 1138bdcd8170SKalle Valo 1139bdcd8170SKalle Valo ar_sdio->ar = ar; 1140bdcd8170SKalle Valo ar->hif_priv = ar_sdio; 1141bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops; 11421f4c894dSKalle Valo ar->bmi.max_data_size = 256; 1143bdcd8170SKalle Valo 1144bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar); 1145bdcd8170SKalle Valo 1146e28e8104SKalle Valo ret = ath6kl_sdio_config(ar); 1147bdcd8170SKalle Valo if (ret) { 1148e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret); 11498dafb70eSVasanthakumar Thiagarajan goto err_core_alloc; 1150bdcd8170SKalle Valo } 1151bdcd8170SKalle Valo 1152bdcd8170SKalle Valo ret = ath6kl_core_init(ar); 1153bdcd8170SKalle Valo if (ret) { 1154bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n"); 1155e28e8104SKalle Valo goto err_core_alloc; 1156bdcd8170SKalle Valo } 1157bdcd8170SKalle Valo 1158bdcd8170SKalle Valo return ret; 1159bdcd8170SKalle Valo 11608dafb70eSVasanthakumar Thiagarajan err_core_alloc: 11618dafb70eSVasanthakumar Thiagarajan ath6kl_core_free(ar_sdio->ar); 1162bdcd8170SKalle Valo err_dma: 1163bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1164bdcd8170SKalle Valo err_hif: 1165bdcd8170SKalle Valo kfree(ar_sdio); 1166bdcd8170SKalle Valo 1167bdcd8170SKalle Valo return ret; 1168bdcd8170SKalle Valo } 1169bdcd8170SKalle Valo 1170bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func) 1171bdcd8170SKalle Valo { 1172bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1173bdcd8170SKalle Valo 11743ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11753ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n", 1176f7325b85SKalle Valo func->num, func->vendor, func->device); 1177f7325b85SKalle Valo 1178bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 1179bdcd8170SKalle Valo 1180bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar); 1181bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 1182bdcd8170SKalle Valo 11836db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar); 1184bdcd8170SKalle Valo 1185bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1186bdcd8170SKalle Valo kfree(ar_sdio); 1187bdcd8170SKalle Valo } 1188bdcd8170SKalle Valo 1189bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = { 1190bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1191bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1192bdcd8170SKalle Valo {}, 1193bdcd8170SKalle Valo }; 1194bdcd8170SKalle Valo 1195bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1196bdcd8170SKalle Valo 1197bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = { 1198cd4b8b85SKalle Valo .name = "ath6kl", 1199bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices, 1200bdcd8170SKalle Valo .probe = ath6kl_sdio_probe, 1201bdcd8170SKalle Valo .remove = ath6kl_sdio_remove, 1202b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS, 1203bdcd8170SKalle Valo }; 1204bdcd8170SKalle Valo 1205bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void) 1206bdcd8170SKalle Valo { 1207bdcd8170SKalle Valo int ret; 1208bdcd8170SKalle Valo 1209bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver); 1210bdcd8170SKalle Valo if (ret) 1211bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret); 1212bdcd8170SKalle Valo 1213bdcd8170SKalle Valo return ret; 1214bdcd8170SKalle Valo } 1215bdcd8170SKalle Valo 1216bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void) 1217bdcd8170SKalle Valo { 1218bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver); 1219bdcd8170SKalle Valo } 1220bdcd8170SKalle Valo 1221bdcd8170SKalle Valo module_init(ath6kl_sdio_init); 1222bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit); 1223bdcd8170SKalle Valo 1224bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc."); 1225bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1226bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL"); 1227bdcd8170SKalle Valo 1228bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV2_OTP_FILE); 1229bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV2_FIRMWARE_FILE); 1230bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV2_PATCH_FILE); 1231bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV2_BOARD_DATA_FILE); 1232bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV2_DEFAULT_BOARD_DATA_FILE); 1233bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV3_OTP_FILE); 1234bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV3_FIRMWARE_FILE); 1235bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV3_PATCH_FILE); 1236bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV3_BOARD_DATA_FILE); 1237bdcd8170SKalle Valo MODULE_FIRMWARE(AR6003_REV3_DEFAULT_BOARD_DATA_FILE); 1238