1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #include <linux/mmc/card.h> 18bdcd8170SKalle Valo #include <linux/mmc/mmc.h> 19bdcd8170SKalle Valo #include <linux/mmc/host.h> 20bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 21bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h> 22bdcd8170SKalle Valo #include <linux/mmc/sdio.h> 23bdcd8170SKalle Valo #include <linux/mmc/sd.h> 242e1cb23cSKalle Valo #include "hif.h" 25bdcd8170SKalle Valo #include "hif-ops.h" 26bdcd8170SKalle Valo #include "target.h" 27bdcd8170SKalle Valo #include "debug.h" 289df337a1SVivek Natarajan #include "cfg80211.h" 29bdcd8170SKalle Valo 30bdcd8170SKalle Valo struct ath6kl_sdio { 31bdcd8170SKalle Valo struct sdio_func *func; 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo spinlock_t lock; 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo /* free list */ 36bdcd8170SKalle Valo struct list_head bus_req_freeq; 37bdcd8170SKalle Valo 38bdcd8170SKalle Valo /* available bus requests */ 39bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM]; 40bdcd8170SKalle Valo 41bdcd8170SKalle Valo struct ath6kl *ar; 42fdb28589SRaja Mani 43bdcd8170SKalle Valo u8 *dma_buffer; 44bdcd8170SKalle Valo 45fdb28589SRaja Mani /* protects access to dma_buffer */ 46fdb28589SRaja Mani struct mutex dma_buffer_mutex; 47fdb28589SRaja Mani 48bdcd8170SKalle Valo /* scatter request list head */ 49bdcd8170SKalle Valo struct list_head scat_req; 50bdcd8170SKalle Valo 51bdcd8170SKalle Valo spinlock_t scat_lock; 5232a07e44SKalle Valo bool scatter_enabled; 5332a07e44SKalle Valo 54bdcd8170SKalle Valo bool is_disabled; 55bdcd8170SKalle Valo atomic_t irq_handling; 56bdcd8170SKalle Valo const struct sdio_device_id *id; 57bdcd8170SKalle Valo struct work_struct wr_async_work; 58bdcd8170SKalle Valo struct list_head wr_asyncq; 59bdcd8170SKalle Valo spinlock_t wr_async_lock; 60bdcd8170SKalle Valo }; 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo #define CMD53_ARG_READ 0 63bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1 64bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1 65bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0 66bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1 67bdcd8170SKalle Valo 68bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar) 69bdcd8170SKalle Valo { 70bdcd8170SKalle Valo return ar->hif_priv; 71bdcd8170SKalle Valo } 72bdcd8170SKalle Valo 73bdcd8170SKalle Valo /* 74bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able. 75bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will 76bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid 77bdcd8170SKalle Valo * check fails on stack memory. 78bdcd8170SKalle Valo */ 79bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf) 80bdcd8170SKalle Valo { 81bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf); 82bdcd8170SKalle Valo } 83bdcd8170SKalle Valo 84bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar) 85bdcd8170SKalle Valo { 86bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info; 87bdcd8170SKalle Valo 88bdcd8170SKalle Valo /* EP1 has an extended range */ 89bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR; 90bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR; 91bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH; 92bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE; 93bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR; 94bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH; 95bdcd8170SKalle Valo } 96bdcd8170SKalle Valo 97bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func, 98bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr, 99bdcd8170SKalle Valo u16 blksz) 100bdcd8170SKalle Valo { 101bdcd8170SKalle Valo *arg = (((rw & 1) << 31) | 102bdcd8170SKalle Valo ((func & 0x7) << 28) | 103bdcd8170SKalle Valo ((mode & 1) << 27) | 104bdcd8170SKalle Valo ((opcode & 1) << 26) | 105bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) | 106bdcd8170SKalle Valo (blksz & 0x1FF)); 107bdcd8170SKalle Valo } 108bdcd8170SKalle Valo 109bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 110bdcd8170SKalle Valo unsigned int address, 111bdcd8170SKalle Valo unsigned char val) 112bdcd8170SKalle Valo { 113bdcd8170SKalle Valo const u8 func = 0; 114bdcd8170SKalle Valo 115bdcd8170SKalle Valo *arg = ((write & 1) << 31) | 116bdcd8170SKalle Valo ((func & 0x7) << 28) | 117bdcd8170SKalle Valo ((raw & 1) << 27) | 118bdcd8170SKalle Valo (1 << 26) | 119bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) | 120bdcd8170SKalle Valo (1 << 8) | 121bdcd8170SKalle Valo (val & 0xFF); 122bdcd8170SKalle Valo } 123bdcd8170SKalle Valo 124bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 125bdcd8170SKalle Valo unsigned int address, 126bdcd8170SKalle Valo unsigned char byte) 127bdcd8170SKalle Valo { 128bdcd8170SKalle Valo struct mmc_command io_cmd; 129bdcd8170SKalle Valo 130bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd)); 131bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 132bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT; 133bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 134bdcd8170SKalle Valo 135bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0); 136bdcd8170SKalle Valo } 137bdcd8170SKalle Valo 138da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr, 139da220695SVasanthakumar Thiagarajan u8 *buf, u32 len) 140da220695SVasanthakumar Thiagarajan { 141da220695SVasanthakumar Thiagarajan int ret = 0; 142da220695SVasanthakumar Thiagarajan 143861dd058SVasanthakumar Thiagarajan sdio_claim_host(func); 144861dd058SVasanthakumar Thiagarajan 145da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) { 146f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */ 147da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR && 148da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR) 149da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len); 150da220695SVasanthakumar Thiagarajan 151f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */ 152da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR) 153da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len; 154da220695SVasanthakumar Thiagarajan 155da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 156da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len); 157da220695SVasanthakumar Thiagarajan else 158da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len); 159da220695SVasanthakumar Thiagarajan } else { 160da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS) 161da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len); 162da220695SVasanthakumar Thiagarajan else 163da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len); 164da220695SVasanthakumar Thiagarajan } 165da220695SVasanthakumar Thiagarajan 166861dd058SVasanthakumar Thiagarajan sdio_release_host(func); 167861dd058SVasanthakumar Thiagarajan 168f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n", 169f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr, 170f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len); 171f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len); 172f7325b85SKalle Valo 173da220695SVasanthakumar Thiagarajan return ret; 174da220695SVasanthakumar Thiagarajan } 175da220695SVasanthakumar Thiagarajan 176bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio) 177bdcd8170SKalle Valo { 178bdcd8170SKalle Valo struct bus_request *bus_req; 179bdcd8170SKalle Valo 180151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 181bdcd8170SKalle Valo 182bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) { 183151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 184bdcd8170SKalle Valo return NULL; 185bdcd8170SKalle Valo } 186bdcd8170SKalle Valo 187bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 188bdcd8170SKalle Valo struct bus_request, list); 189bdcd8170SKalle Valo list_del(&bus_req->list); 190bdcd8170SKalle Valo 191151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 192f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 193f7325b85SKalle Valo __func__, bus_req); 194bdcd8170SKalle Valo 195bdcd8170SKalle Valo return bus_req; 196bdcd8170SKalle Valo } 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio, 199bdcd8170SKalle Valo struct bus_request *bus_req) 200bdcd8170SKalle Valo { 201f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n", 202f7325b85SKalle Valo __func__, bus_req); 203bdcd8170SKalle Valo 204151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock); 205bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 206151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock); 207bdcd8170SKalle Valo } 208bdcd8170SKalle Valo 209bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req, 210bdcd8170SKalle Valo struct mmc_data *data) 211bdcd8170SKalle Valo { 212bdcd8170SKalle Valo struct scatterlist *sg; 213bdcd8170SKalle Valo int i; 214bdcd8170SKalle Valo 215bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE; 216bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE; 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, 219bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n", 220bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, 221bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len, 222bdcd8170SKalle Valo scat_req->scat_entries); 223bdcd8170SKalle Valo 224bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE : 225bdcd8170SKalle Valo MMC_DATA_READ; 226bdcd8170SKalle Valo 227bdcd8170SKalle Valo /* fill SG entries */ 228d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries; 229bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries); 230bdcd8170SKalle Valo 231bdcd8170SKalle Valo /* assemble SG list */ 232bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) { 233bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n", 234bdcd8170SKalle Valo i, scat_req->scat_list[i].buf, 235bdcd8170SKalle Valo scat_req->scat_list[i].len); 236bdcd8170SKalle Valo 237bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf, 238bdcd8170SKalle Valo scat_req->scat_list[i].len); 239bdcd8170SKalle Valo } 240bdcd8170SKalle Valo 241bdcd8170SKalle Valo /* set scatter-gather table for request */ 242d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries; 243bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries; 244bdcd8170SKalle Valo } 245bdcd8170SKalle Valo 246bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio, 247bdcd8170SKalle Valo struct bus_request *req) 248bdcd8170SKalle Valo { 249bdcd8170SKalle Valo struct mmc_request mmc_req; 250bdcd8170SKalle Valo struct mmc_command cmd; 251bdcd8170SKalle Valo struct mmc_data data; 252bdcd8170SKalle Valo struct hif_scatter_req *scat_req; 253bdcd8170SKalle Valo u8 opcode, rw; 254348a8fbcSVasanthakumar Thiagarajan int status, len; 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo scat_req = req->scat_req; 257bdcd8170SKalle Valo 258348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) { 259348a8fbcSVasanthakumar Thiagarajan len = scat_req->len; 260348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS) 261348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE); 262348a8fbcSVasanthakumar Thiagarajan 263348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req, 264348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf, 265348a8fbcSVasanthakumar Thiagarajan len); 266348a8fbcSVasanthakumar Thiagarajan goto scat_complete; 267348a8fbcSVasanthakumar Thiagarajan } 268348a8fbcSVasanthakumar Thiagarajan 269bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request)); 270bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command)); 271bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data)); 272bdcd8170SKalle Valo 273d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data); 274bdcd8170SKalle Valo 275bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ? 276bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS; 277bdcd8170SKalle Valo 278bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ; 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */ 281bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) { 282bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR) 283bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len; 284bdcd8170SKalle Valo else 285bdcd8170SKalle Valo /* Uses extended address range */ 286bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len; 287bdcd8170SKalle Valo } 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo /* set command argument */ 290bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num, 291bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr, 292bdcd8170SKalle Valo data.blocks); 293bdcd8170SKalle Valo 294bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED; 295bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; 296bdcd8170SKalle Valo 297bdcd8170SKalle Valo mmc_req.cmd = &cmd; 298bdcd8170SKalle Valo mmc_req.data = &data; 299bdcd8170SKalle Valo 300861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func); 301861dd058SVasanthakumar Thiagarajan 302bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card); 303bdcd8170SKalle Valo /* synchronous call to process request */ 304bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req); 305bdcd8170SKalle Valo 306861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func); 307861dd058SVasanthakumar Thiagarajan 308bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error; 309348a8fbcSVasanthakumar Thiagarajan 310348a8fbcSVasanthakumar Thiagarajan scat_complete: 311bdcd8170SKalle Valo scat_req->status = status; 312bdcd8170SKalle Valo 313bdcd8170SKalle Valo if (scat_req->status) 314bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n", 315bdcd8170SKalle Valo scat_req->status); 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS) 318e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req); 319bdcd8170SKalle Valo 320bdcd8170SKalle Valo return status; 321bdcd8170SKalle Valo } 322bdcd8170SKalle Valo 3233df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio, 3243df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req, 3253df505adSVasanthakumar Thiagarajan bool virt_scat) 3263df505adSVasanthakumar Thiagarajan { 3273df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req; 3283df505adSVasanthakumar Thiagarajan struct bus_request *bus_req; 329cfeab10bSVasanthakumar Thiagarajan int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz; 330cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf; 3313df505adSVasanthakumar Thiagarajan 3323df505adSVasanthakumar Thiagarajan scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item); 3333df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz; 3343df505adSVasanthakumar Thiagarajan 3353df505adSVasanthakumar Thiagarajan if (!virt_scat) 3363df505adSVasanthakumar Thiagarajan sg_sz = sizeof(struct scatterlist) * n_scat_entry; 337cfeab10bSVasanthakumar Thiagarajan else 338cfeab10bSVasanthakumar Thiagarajan buf_sz = 2 * L1_CACHE_BYTES + 339cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 3403df505adSVasanthakumar Thiagarajan 3413df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) { 3423df505adSVasanthakumar Thiagarajan /* allocate the scatter request */ 3433df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL); 3443df505adSVasanthakumar Thiagarajan if (!s_req) 3453df505adSVasanthakumar Thiagarajan return -ENOMEM; 3463df505adSVasanthakumar Thiagarajan 347cfeab10bSVasanthakumar Thiagarajan if (virt_scat) { 348cfeab10bSVasanthakumar Thiagarajan virt_buf = kzalloc(buf_sz, GFP_KERNEL); 349cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) { 350cfeab10bSVasanthakumar Thiagarajan kfree(s_req); 351cfeab10bSVasanthakumar Thiagarajan return -ENOMEM; 352cfeab10bSVasanthakumar Thiagarajan } 353cfeab10bSVasanthakumar Thiagarajan 354cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf = 355cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf); 356cfeab10bSVasanthakumar Thiagarajan } else { 3573df505adSVasanthakumar Thiagarajan /* allocate sglist */ 3583df505adSVasanthakumar Thiagarajan s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL); 3593df505adSVasanthakumar Thiagarajan 3603df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) { 3613df505adSVasanthakumar Thiagarajan kfree(s_req); 3623df505adSVasanthakumar Thiagarajan return -ENOMEM; 3633df505adSVasanthakumar Thiagarajan } 3643df505adSVasanthakumar Thiagarajan } 3653df505adSVasanthakumar Thiagarajan 3663df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */ 3673df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 3683df505adSVasanthakumar Thiagarajan if (!bus_req) { 3693df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries); 370cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 3713df505adSVasanthakumar Thiagarajan kfree(s_req); 3723df505adSVasanthakumar Thiagarajan return -ENOMEM; 3733df505adSVasanthakumar Thiagarajan } 3743df505adSVasanthakumar Thiagarajan 3753df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */ 3763df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req; 3773df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req; 3783df505adSVasanthakumar Thiagarajan 3794a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat; 3804a005c3eSVasanthakumar Thiagarajan 3813df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */ 3823df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req); 3833df505adSVasanthakumar Thiagarajan } 3843df505adSVasanthakumar Thiagarajan 3853df505adSVasanthakumar Thiagarajan return 0; 3863df505adSVasanthakumar Thiagarajan } 3873df505adSVasanthakumar Thiagarajan 388bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf, 389bdcd8170SKalle Valo u32 len, u32 request) 390bdcd8170SKalle Valo { 391bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 392bdcd8170SKalle Valo u8 *tbuf = NULL; 393bdcd8170SKalle Valo int ret; 394bdcd8170SKalle Valo bool bounced = false; 395bdcd8170SKalle Valo 396bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS) 397bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE); 398bdcd8170SKalle Valo 399bdcd8170SKalle Valo if (buf_needs_bounce(buf)) { 400bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) 401bdcd8170SKalle Valo return -ENOMEM; 402fdb28589SRaja Mani mutex_lock(&ar_sdio->dma_buffer_mutex); 403bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer; 404bdcd8170SKalle Valo memcpy(tbuf, buf, len); 405bdcd8170SKalle Valo bounced = true; 406bdcd8170SKalle Valo } else 407bdcd8170SKalle Valo tbuf = buf; 408bdcd8170SKalle Valo 409da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len); 410da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced) 411bdcd8170SKalle Valo memcpy(buf, tbuf, len); 412bdcd8170SKalle Valo 413fdb28589SRaja Mani if (bounced) 414fdb28589SRaja Mani mutex_unlock(&ar_sdio->dma_buffer_mutex); 415fdb28589SRaja Mani 416bdcd8170SKalle Valo return ret; 417bdcd8170SKalle Valo } 418bdcd8170SKalle Valo 419bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio, 420bdcd8170SKalle Valo struct bus_request *req) 421bdcd8170SKalle Valo { 422bdcd8170SKalle Valo if (req->scat_req) 423bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req); 424bdcd8170SKalle Valo else { 425bdcd8170SKalle Valo void *context; 426bdcd8170SKalle Valo int status; 427bdcd8170SKalle Valo 428bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address, 429bdcd8170SKalle Valo req->buffer, req->length, 430bdcd8170SKalle Valo req->request); 431bdcd8170SKalle Valo context = req->packet; 432bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 4338e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status); 434bdcd8170SKalle Valo } 435bdcd8170SKalle Valo } 436bdcd8170SKalle Valo 437bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work) 438bdcd8170SKalle Valo { 439bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 440bdcd8170SKalle Valo struct bus_request *req, *tmp_req; 441bdcd8170SKalle Valo 442bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work); 443bdcd8170SKalle Valo 444151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 445bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 446bdcd8170SKalle Valo list_del(&req->list); 447151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 448bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req); 449151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 450bdcd8170SKalle Valo } 451151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 452bdcd8170SKalle Valo } 453bdcd8170SKalle Valo 454bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func) 455bdcd8170SKalle Valo { 456bdcd8170SKalle Valo int status; 457bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 458bdcd8170SKalle Valo 459f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n"); 460f7325b85SKalle Valo 461bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 462bdcd8170SKalle Valo atomic_set(&ar_sdio->irq_handling, 1); 463bdcd8170SKalle Valo 464bdcd8170SKalle Valo /* 465bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when 466bdcd8170SKalle Valo * we process commands. 467bdcd8170SKalle Valo */ 468bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 469bdcd8170SKalle Valo 4708e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar); 471bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 472bdcd8170SKalle Valo atomic_set(&ar_sdio->irq_handling, 0); 473bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED); 474bdcd8170SKalle Valo } 475bdcd8170SKalle Valo 476b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar) 477bdcd8170SKalle Valo { 478b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 479bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func; 480bdcd8170SKalle Valo int ret = 0; 481bdcd8170SKalle Valo 482bdcd8170SKalle Valo if (!ar_sdio->is_disabled) 483bdcd8170SKalle Valo return 0; 484bdcd8170SKalle Valo 4853ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n"); 4863ef987beSKalle Valo 487bdcd8170SKalle Valo sdio_claim_host(func); 488bdcd8170SKalle Valo 489bdcd8170SKalle Valo ret = sdio_enable_func(func); 490bdcd8170SKalle Valo if (ret) { 491bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret); 492bdcd8170SKalle Valo sdio_release_host(func); 493bdcd8170SKalle Valo return ret; 494bdcd8170SKalle Valo } 495bdcd8170SKalle Valo 496bdcd8170SKalle Valo sdio_release_host(func); 497bdcd8170SKalle Valo 498bdcd8170SKalle Valo /* 499bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than 500bdcd8170SKalle Valo * 10 ms but let's be conservative here. 501bdcd8170SKalle Valo */ 502bdcd8170SKalle Valo msleep(10); 503bdcd8170SKalle Valo 504bdcd8170SKalle Valo ar_sdio->is_disabled = false; 505bdcd8170SKalle Valo 506bdcd8170SKalle Valo return ret; 507bdcd8170SKalle Valo } 508bdcd8170SKalle Valo 509b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar) 510bdcd8170SKalle Valo { 511b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 512bdcd8170SKalle Valo int ret; 513bdcd8170SKalle Valo 514bdcd8170SKalle Valo if (ar_sdio->is_disabled) 515bdcd8170SKalle Valo return 0; 516bdcd8170SKalle Valo 5173ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n"); 5183ef987beSKalle Valo 519bdcd8170SKalle Valo /* Disable the card */ 520bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 521bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func); 522bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 523bdcd8170SKalle Valo 524bdcd8170SKalle Valo if (ret) 525bdcd8170SKalle Valo return ret; 526bdcd8170SKalle Valo 527bdcd8170SKalle Valo ar_sdio->is_disabled = true; 528bdcd8170SKalle Valo 529bdcd8170SKalle Valo return ret; 530bdcd8170SKalle Valo } 531bdcd8170SKalle Valo 532bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer, 533bdcd8170SKalle Valo u32 length, u32 request, 534bdcd8170SKalle Valo struct htc_packet *packet) 535bdcd8170SKalle Valo { 536bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 537bdcd8170SKalle Valo struct bus_request *bus_req; 538bdcd8170SKalle Valo 539bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio); 540bdcd8170SKalle Valo 541bdcd8170SKalle Valo if (!bus_req) 542bdcd8170SKalle Valo return -ENOMEM; 543bdcd8170SKalle Valo 544bdcd8170SKalle Valo bus_req->address = address; 545bdcd8170SKalle Valo bus_req->buffer = buffer; 546bdcd8170SKalle Valo bus_req->length = length; 547bdcd8170SKalle Valo bus_req->request = request; 548bdcd8170SKalle Valo bus_req->packet = packet; 549bdcd8170SKalle Valo 550151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 551bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 552151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 553bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 554bdcd8170SKalle Valo 555bdcd8170SKalle Valo return 0; 556bdcd8170SKalle Valo } 557bdcd8170SKalle Valo 558bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar) 559bdcd8170SKalle Valo { 560bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 561bdcd8170SKalle Valo int ret; 562bdcd8170SKalle Valo 563bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 564bdcd8170SKalle Valo 565bdcd8170SKalle Valo /* Register the isr */ 566bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler); 567bdcd8170SKalle Valo if (ret) 568bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret); 569bdcd8170SKalle Valo 570bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 571bdcd8170SKalle Valo } 572bdcd8170SKalle Valo 573bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar) 574bdcd8170SKalle Valo { 575bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 576bdcd8170SKalle Valo int ret; 577bdcd8170SKalle Valo 578bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 579bdcd8170SKalle Valo 580bdcd8170SKalle Valo /* Mask our function IRQ */ 581bdcd8170SKalle Valo while (atomic_read(&ar_sdio->irq_handling)) { 582bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 583bdcd8170SKalle Valo schedule_timeout(HZ / 10); 584bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func); 585bdcd8170SKalle Valo } 586bdcd8170SKalle Valo 587bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func); 588bdcd8170SKalle Valo if (ret) 589bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret); 590bdcd8170SKalle Valo 591bdcd8170SKalle Valo sdio_release_host(ar_sdio->func); 592bdcd8170SKalle Valo } 593bdcd8170SKalle Valo 594bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar) 595bdcd8170SKalle Valo { 596bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 597bdcd8170SKalle Valo struct hif_scatter_req *node = NULL; 598bdcd8170SKalle Valo 599151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 600bdcd8170SKalle Valo 601bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) { 602bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req, 603bdcd8170SKalle Valo struct hif_scatter_req, list); 604bdcd8170SKalle Valo list_del(&node->list); 605bdcd8170SKalle Valo } 606bdcd8170SKalle Valo 607151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 608bdcd8170SKalle Valo 609bdcd8170SKalle Valo return node; 610bdcd8170SKalle Valo } 611bdcd8170SKalle Valo 612bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar, 613bdcd8170SKalle Valo struct hif_scatter_req *s_req) 614bdcd8170SKalle Valo { 615bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 616bdcd8170SKalle Valo 617151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 618bdcd8170SKalle Valo 619bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req); 620bdcd8170SKalle Valo 621151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 622bdcd8170SKalle Valo 623bdcd8170SKalle Valo } 624bdcd8170SKalle Valo 625c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */ 626c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar, 627c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req) 628c630d18aSVasanthakumar Thiagarajan { 629c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 630c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req; 631c630d18aSVasanthakumar Thiagarajan int status = 0; 632c630d18aSVasanthakumar Thiagarajan 633c630d18aSVasanthakumar Thiagarajan if (!scat_req->len) 634c630d18aSVasanthakumar Thiagarajan return -EINVAL; 635c630d18aSVasanthakumar Thiagarajan 636c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER, 637c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n", 638c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries); 639c630d18aSVasanthakumar Thiagarajan 640861dd058SVasanthakumar Thiagarajan if (request & HIF_SYNCHRONOUS) 641d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest); 642861dd058SVasanthakumar Thiagarajan else { 643151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock); 644d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq); 645151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock); 646c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work); 647c630d18aSVasanthakumar Thiagarajan } 648c630d18aSVasanthakumar Thiagarajan 649c630d18aSVasanthakumar Thiagarajan return status; 650c630d18aSVasanthakumar Thiagarajan } 651c630d18aSVasanthakumar Thiagarajan 65218a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */ 65318a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar) 65418a0f93eSVasanthakumar Thiagarajan { 65518a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 65618a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req; 65718a0f93eSVasanthakumar Thiagarajan 65818a0f93eSVasanthakumar Thiagarajan /* empty the free list */ 659151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 66018a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) { 66118a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list); 662151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 66318a0f93eSVasanthakumar Thiagarajan 66432a07e44SKalle Valo /* 66532a07e44SKalle Valo * FIXME: should we also call completion handler with 66632a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so 66732a07e44SKalle Valo * that the packet is properly freed? 66832a07e44SKalle Valo */ 66918a0f93eSVasanthakumar Thiagarajan if (s_req->busrequest) 67018a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest); 67118a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf); 67218a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries); 67318a0f93eSVasanthakumar Thiagarajan kfree(s_req); 67418a0f93eSVasanthakumar Thiagarajan 675151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock); 67618a0f93eSVasanthakumar Thiagarajan } 677151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock); 67818a0f93eSVasanthakumar Thiagarajan } 67918a0f93eSVasanthakumar Thiagarajan 68018a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */ 68150745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar) 68218a0f93eSVasanthakumar Thiagarajan { 68318a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 68450745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target; 685cfeab10bSVasanthakumar Thiagarajan int ret; 686cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false; 68718a0f93eSVasanthakumar Thiagarajan 68832a07e44SKalle Valo if (ar_sdio->scatter_enabled) 68932a07e44SKalle Valo return 0; 69032a07e44SKalle Valo 69132a07e44SKalle Valo ar_sdio->scatter_enabled = true; 69232a07e44SKalle Valo 69318a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */ 69418a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) { 695cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n", 69618a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs, 69718a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 698cfeab10bSVasanthakumar Thiagarajan virt_scat = true; 69918a0f93eSVasanthakumar Thiagarajan } 70018a0f93eSVasanthakumar Thiagarajan 701cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) { 70218a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 70318a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ, 704cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat); 705cfeab10bSVasanthakumar Thiagarajan 706cfeab10bSVasanthakumar Thiagarajan if (!ret) { 7073ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7083ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n", 709cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, 710cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ); 711cfeab10bSVasanthakumar Thiagarajan 71250745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ; 71350745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 714cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE; 715cfeab10bSVasanthakumar Thiagarajan } else { 716cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 717cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n"); 718cfeab10bSVasanthakumar Thiagarajan } 719cfeab10bSVasanthakumar Thiagarajan } 720cfeab10bSVasanthakumar Thiagarajan 721cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) { 722cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio, 723cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ, 724cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat); 725cfeab10bSVasanthakumar Thiagarajan 72618a0f93eSVasanthakumar Thiagarajan if (ret) { 727cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n"); 72818a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar); 72918a0f93eSVasanthakumar Thiagarajan return ret; 73018a0f93eSVasanthakumar Thiagarajan } 73118a0f93eSVasanthakumar Thiagarajan 7323ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 7333ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n", 734cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ); 735cfeab10bSVasanthakumar Thiagarajan 73650745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ; 73750745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq = 738cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER; 739cfeab10bSVasanthakumar Thiagarajan } 740cfeab10bSVasanthakumar Thiagarajan 74118a0f93eSVasanthakumar Thiagarajan return 0; 74218a0f93eSVasanthakumar Thiagarajan } 74318a0f93eSVasanthakumar Thiagarajan 744e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar) 745e28e8104SKalle Valo { 746e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 747e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func; 748e28e8104SKalle Valo int ret; 749e28e8104SKalle Valo 750e28e8104SKalle Valo sdio_claim_host(func); 751e28e8104SKalle Valo 752e28e8104SKalle Valo if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >= 753e28e8104SKalle Valo MANUFACTURER_ID_AR6003_BASE) { 754e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */ 755e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card, 756e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG, 757e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); 758e28e8104SKalle Valo if (ret) { 759e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n", 760e28e8104SKalle Valo ret); 761e28e8104SKalle Valo goto out; 762e28e8104SKalle Valo } 763e28e8104SKalle Valo 764e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n"); 765e28e8104SKalle Valo } 766e28e8104SKalle Valo 767e28e8104SKalle Valo /* give us some time to enable, in ms */ 768e28e8104SKalle Valo func->enable_timeout = 100; 769e28e8104SKalle Valo 770e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); 771e28e8104SKalle Valo if (ret) { 772e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n", 773e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret); 774e28e8104SKalle Valo sdio_release_host(func); 775e28e8104SKalle Valo goto out; 776e28e8104SKalle Valo } 777e28e8104SKalle Valo 778e28e8104SKalle Valo out: 779e28e8104SKalle Valo sdio_release_host(func); 780e28e8104SKalle Valo 781e28e8104SKalle Valo return ret; 782e28e8104SKalle Valo } 783e28e8104SKalle Valo 7840f60e9f4SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow) 785abcb344bSKalle Valo { 786abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 787abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func; 788abcb344bSKalle Valo mmc_pm_flag_t flags; 789abcb344bSKalle Valo int ret; 790abcb344bSKalle Valo 791abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func); 792abcb344bSKalle Valo 793b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags); 794b4b2a0b1SKalle Valo 7958277de15SKalle Valo if (!(flags & MMC_PM_KEEP_POWER) || 7968277de15SKalle Valo (ar->conf_flags & ATH6KL_CONF_SUSPEND_CUTPOWER)) { 797b4b2a0b1SKalle Valo /* as host doesn't support keep power we need to cut power */ 7980f60e9f4SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, 7990f60e9f4SRaja Mani NULL); 80017380859SSam Leffler } 801abcb344bSKalle Valo 802abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER); 803abcb344bSKalle Valo if (ret) { 804abcb344bSKalle Valo printk(KERN_ERR "ath6kl: set sdio pm flags failed: %d\n", 805abcb344bSKalle Valo ret); 806abcb344bSKalle Valo return ret; 807abcb344bSKalle Valo } 808abcb344bSKalle Valo 80910509f90SKalle Valo if (!(flags & MMC_PM_WAKE_SDIO_IRQ)) 81010509f90SKalle Valo goto deepsleep; 81110509f90SKalle Valo 81210509f90SKalle Valo /* sdio irq wakes up host */ 81310509f90SKalle Valo 81410509f90SKalle Valo if (ar->state == ATH6KL_STATE_SCHED_SCAN) { 81510509f90SKalle Valo ret = ath6kl_cfg80211_suspend(ar, 81610509f90SKalle Valo ATH6KL_CFG_SUSPEND_SCHED_SCAN, 81710509f90SKalle Valo NULL); 81810509f90SKalle Valo if (ret) { 81910509f90SKalle Valo ath6kl_warn("Schedule scan suspend failed: %d", ret); 82010509f90SKalle Valo return ret; 82110509f90SKalle Valo } 82210509f90SKalle Valo 82310509f90SKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 82410509f90SKalle Valo if (ret) 82510509f90SKalle Valo ath6kl_warn("set sdio wake irq flag failed: %d\n", ret); 82610509f90SKalle Valo 82710509f90SKalle Valo return ret; 82810509f90SKalle Valo } 82910509f90SKalle Valo 83010509f90SKalle Valo if (wow) { 831d7c44e0bSRaja Mani /* 832d7c44e0bSRaja Mani * The host sdio controller is capable of keep power and 833d7c44e0bSRaja Mani * sdio irq wake up at this point. It's fine to continue 834d7c44e0bSRaja Mani * wow suspend operation. 835d7c44e0bSRaja Mani */ 836d7c44e0bSRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow); 837d7c44e0bSRaja Mani if (ret) 838d7c44e0bSRaja Mani return ret; 839d7c44e0bSRaja Mani 840d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ); 841d7c44e0bSRaja Mani if (ret) 842d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret); 843d7c44e0bSRaja Mani 844d7c44e0bSRaja Mani return ret; 845d7c44e0bSRaja Mani } 846d7c44e0bSRaja Mani 84710509f90SKalle Valo deepsleep: 8480f60e9f4SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP, NULL); 849abcb344bSKalle Valo } 850abcb344bSKalle Valo 851aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar) 852aa6cffc1SChilam Ng { 853b4b2a0b1SKalle Valo switch (ar->state) { 854b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF: 855b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER: 856b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, 857b4b2a0b1SKalle Valo "sdio resume configuring sdio\n"); 858b4b2a0b1SKalle Valo 859b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */ 860b4b2a0b1SKalle Valo ath6kl_sdio_config(ar); 861b4b2a0b1SKalle Valo break; 862b4b2a0b1SKalle Valo 863b4b2a0b1SKalle Valo case ATH6KL_STATE_ON: 864b4b2a0b1SKalle Valo break; 865b4b2a0b1SKalle Valo 866b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP: 867b4b2a0b1SKalle Valo break; 868d7c44e0bSRaja Mani 869d7c44e0bSRaja Mani case ATH6KL_STATE_WOW: 870d7c44e0bSRaja Mani break; 87110509f90SKalle Valo case ATH6KL_STATE_SCHED_SCAN: 87210509f90SKalle Valo break; 873b4b2a0b1SKalle Valo } 874b4b2a0b1SKalle Valo 87552d81a68SKalle Valo ath6kl_cfg80211_resume(ar); 876aa6cffc1SChilam Ng 877aa6cffc1SChilam Ng return 0; 878aa6cffc1SChilam Ng } 879aa6cffc1SChilam Ng 880c7111495SKalle Valo /* set the window address register (using 4-byte register access ). */ 881c7111495SKalle Valo static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr) 882c7111495SKalle Valo { 883c7111495SKalle Valo int status; 884c7111495SKalle Valo u8 addr_val[4]; 885c7111495SKalle Valo s32 i; 886c7111495SKalle Valo 887c7111495SKalle Valo /* 888c7111495SKalle Valo * Write bytes 1,2,3 of the register to set the upper address bytes, 889c7111495SKalle Valo * the LSB is written last to initiate the access cycle 890c7111495SKalle Valo */ 891c7111495SKalle Valo 892c7111495SKalle Valo for (i = 1; i <= 3; i++) { 893c7111495SKalle Valo /* 894c7111495SKalle Valo * Fill the buffer with the address byte value we want to 895c7111495SKalle Valo * hit 4 times. 896c7111495SKalle Valo */ 897c7111495SKalle Valo memset(addr_val, ((u8 *)&addr)[i], 4); 898c7111495SKalle Valo 899c7111495SKalle Valo /* 900c7111495SKalle Valo * Hit each byte of the register address with a 4-byte 901c7111495SKalle Valo * write operation to the same address, this is a harmless 902c7111495SKalle Valo * operation. 903c7111495SKalle Valo */ 904c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val, 905c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_FIX); 906c7111495SKalle Valo if (status) 907c7111495SKalle Valo break; 908c7111495SKalle Valo } 909c7111495SKalle Valo 910c7111495SKalle Valo if (status) { 911c7111495SKalle Valo ath6kl_err("%s: failed to write initial bytes of 0x%x " 912c7111495SKalle Valo "to window reg: 0x%X\n", __func__, 913c7111495SKalle Valo addr, reg_addr); 914c7111495SKalle Valo return status; 915c7111495SKalle Valo } 916c7111495SKalle Valo 917c7111495SKalle Valo /* 918c7111495SKalle Valo * Write the address register again, this time write the whole 919c7111495SKalle Valo * 4-byte value. The effect here is that the LSB write causes the 920c7111495SKalle Valo * cycle to start, the extra 3 byte write to bytes 1,2,3 has no 921c7111495SKalle Valo * effect since we are writing the same values again 922c7111495SKalle Valo */ 923c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr), 924c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_INC); 925c7111495SKalle Valo 926c7111495SKalle Valo if (status) { 927c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n", 928c7111495SKalle Valo __func__, addr, reg_addr); 929c7111495SKalle Valo return status; 930c7111495SKalle Valo } 931c7111495SKalle Valo 932c7111495SKalle Valo return 0; 933c7111495SKalle Valo } 934c7111495SKalle Valo 935c7111495SKalle Valo static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data) 936c7111495SKalle Valo { 937c7111495SKalle Valo int status; 938c7111495SKalle Valo 939c7111495SKalle Valo /* set window register to start read cycle */ 940c7111495SKalle Valo status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS, 941c7111495SKalle Valo address); 942c7111495SKalle Valo 943c7111495SKalle Valo if (status) 944c7111495SKalle Valo return status; 945c7111495SKalle Valo 946c7111495SKalle Valo /* read the data */ 947c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 948c7111495SKalle Valo (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC); 949c7111495SKalle Valo if (status) { 950c7111495SKalle Valo ath6kl_err("%s: failed to read from window data addr\n", 951c7111495SKalle Valo __func__); 952c7111495SKalle Valo return status; 953c7111495SKalle Valo } 954c7111495SKalle Valo 955c7111495SKalle Valo return status; 956c7111495SKalle Valo } 957c7111495SKalle Valo 958c7111495SKalle Valo static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address, 959c7111495SKalle Valo __le32 data) 960c7111495SKalle Valo { 961c7111495SKalle Valo int status; 962c7111495SKalle Valo u32 val = (__force u32) data; 963c7111495SKalle Valo 964c7111495SKalle Valo /* set write data */ 965c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS, 966c7111495SKalle Valo (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC); 967c7111495SKalle Valo if (status) { 968c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window data addr\n", 969c7111495SKalle Valo __func__, data); 970c7111495SKalle Valo return status; 971c7111495SKalle Valo } 972c7111495SKalle Valo 973c7111495SKalle Valo /* set window register, which starts the write cycle */ 974c7111495SKalle Valo return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS, 975c7111495SKalle Valo address); 976c7111495SKalle Valo } 977c7111495SKalle Valo 97866b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar) 97966b693c3SKalle Valo { 98066b693c3SKalle Valo u32 addr; 98166b693c3SKalle Valo unsigned long timeout; 98266b693c3SKalle Valo int ret; 98366b693c3SKalle Valo 98466b693c3SKalle Valo ar->bmi.cmd_credits = 0; 98566b693c3SKalle Valo 98666b693c3SKalle Valo /* Read the counter register to get the command credits */ 98766b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; 98866b693c3SKalle Valo 98966b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 99066b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) { 99166b693c3SKalle Valo 99266b693c3SKalle Valo /* 99366b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte 99466b693c3SKalle Valo * read will hit the counter and cause a decrement, while the 99566b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this 99666b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned. 99766b693c3SKalle Valo */ 99866b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, 99966b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4, 100066b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 100166b693c3SKalle Valo if (ret) { 100266b693c3SKalle Valo ath6kl_err("Unable to decrement the command credit " 100366b693c3SKalle Valo "count register: %d\n", ret); 100466b693c3SKalle Valo return ret; 100566b693c3SKalle Valo } 100666b693c3SKalle Valo 100766b693c3SKalle Valo /* The counter is only 8 bits. 100866b693c3SKalle Valo * Ignore anything in the upper 3 bytes 100966b693c3SKalle Valo */ 101066b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF; 101166b693c3SKalle Valo } 101266b693c3SKalle Valo 101366b693c3SKalle Valo if (!ar->bmi.cmd_credits) { 101466b693c3SKalle Valo ath6kl_err("bmi communication timeout\n"); 101566b693c3SKalle Valo return -ETIMEDOUT; 101666b693c3SKalle Valo } 101766b693c3SKalle Valo 101866b693c3SKalle Valo return 0; 101966b693c3SKalle Valo } 102066b693c3SKalle Valo 102166b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar) 102266b693c3SKalle Valo { 102366b693c3SKalle Valo unsigned long timeout; 102466b693c3SKalle Valo u32 rx_word = 0; 102566b693c3SKalle Valo int ret = 0; 102666b693c3SKalle Valo 102766b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT); 102866b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) { 102966b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, 103066b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS, 103166b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word), 103266b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 103366b693c3SKalle Valo if (ret) { 103466b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n"); 103566b693c3SKalle Valo return ret; 103666b693c3SKalle Valo } 103766b693c3SKalle Valo 103866b693c3SKalle Valo /* all we really want is one bit */ 103966b693c3SKalle Valo rx_word &= (1 << ENDPOINT1); 104066b693c3SKalle Valo } 104166b693c3SKalle Valo 104266b693c3SKalle Valo if (!rx_word) { 104366b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n"); 104466b693c3SKalle Valo return -EINVAL; 104566b693c3SKalle Valo } 104666b693c3SKalle Valo 104766b693c3SKalle Valo return ret; 104866b693c3SKalle Valo } 104966b693c3SKalle Valo 105066b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len) 105166b693c3SKalle Valo { 105266b693c3SKalle Valo int ret; 105366b693c3SKalle Valo u32 addr; 105466b693c3SKalle Valo 105566b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar); 105666b693c3SKalle Valo if (ret) 105766b693c3SKalle Valo return ret; 105866b693c3SKalle Valo 105966b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 106066b693c3SKalle Valo 106166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 106266b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC); 106366b693c3SKalle Valo if (ret) 106466b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n"); 106566b693c3SKalle Valo 106666b693c3SKalle Valo return ret; 106766b693c3SKalle Valo } 106866b693c3SKalle Valo 106966b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len) 107066b693c3SKalle Valo { 107166b693c3SKalle Valo int ret; 107266b693c3SKalle Valo u32 addr; 107366b693c3SKalle Valo 107466b693c3SKalle Valo /* 107566b693c3SKalle Valo * During normal bootup, small reads may be required. 107666b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target 107766b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until 107866b693c3SKalle Valo * we know that response data is available. 107966b693c3SKalle Valo * 108066b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected 108166b693c3SKalle Valo * Target failure rather than risk problems at the HIF level. 108266b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage 108366b693c3SKalle Valo * data on some host controllers. And on an interconnect 108466b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which 108566b693c3SKalle Valo * does not provide any indication on data timeout, it avoids 108666b693c3SKalle Valo * a potential hang or garbage response. 108766b693c3SKalle Valo * 108866b693c3SKalle Valo * Synchronization is more difficult for reads larger than the 108966b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable 109066b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an 109166b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the 109266b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is 109366b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do 109466b693c3SKalle Valo * not occur in practice -- they're supported for debug/development. 109566b693c3SKalle Valo * 109666b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases: 109766b693c3SKalle Valo * CASE 1: length < 4 109866b693c3SKalle Valo * Should not happen 109966b693c3SKalle Valo * 110066b693c3SKalle Valo * CASE 2: 4 <= length <= 128 110166b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO 110266b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for 110366b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE 110466b693c3SKalle Valo * response is available in the the FIFO 110566b693c3SKalle Valo * 110666b693c3SKalle Valo * CASE 3: length > 128 110766b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO 110866b693c3SKalle Valo * 110966b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will 111066b693c3SKalle Valo * usually see a response quickly; but there may be some unusual 111166b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout. 111266b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for 111366b693c3SKalle Valo * BMI_EXECUTE. 111466b693c3SKalle Valo * 111566b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution, 111666b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep 111766b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 111866b693c3SKalle Valo * a function of Host processor speed. 111966b693c3SKalle Valo */ 112066b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */ 112166b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar); 112266b693c3SKalle Valo if (ret) 112366b693c3SKalle Valo return ret; 112466b693c3SKalle Valo } 112566b693c3SKalle Valo 112666b693c3SKalle Valo addr = ar->mbox_info.htc_addr; 112766b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len, 112866b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC); 112966b693c3SKalle Valo if (ret) { 113066b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n", 113166b693c3SKalle Valo ret); 113266b693c3SKalle Valo return ret; 113366b693c3SKalle Valo } 113466b693c3SKalle Valo 113566b693c3SKalle Valo return 0; 113666b693c3SKalle Valo } 113766b693c3SKalle Valo 113832a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar) 113932a07e44SKalle Valo { 114032a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar); 114132a07e44SKalle Valo struct bus_request *req, *tmp_req; 114232a07e44SKalle Valo void *context; 114332a07e44SKalle Valo 114432a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */ 114532a07e44SKalle Valo 114632a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 114732a07e44SKalle Valo 114832a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock); 114932a07e44SKalle Valo 115032a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 115132a07e44SKalle Valo list_del(&req->list); 115232a07e44SKalle Valo 115332a07e44SKalle Valo if (req->scat_req) { 115432a07e44SKalle Valo /* this is a scatter gather request */ 115532a07e44SKalle Valo req->scat_req->status = -ECANCELED; 115632a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target, 115732a07e44SKalle Valo req->scat_req); 115832a07e44SKalle Valo } else { 115932a07e44SKalle Valo context = req->packet; 116032a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req); 116132a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED); 116232a07e44SKalle Valo } 116332a07e44SKalle Valo } 116432a07e44SKalle Valo 116532a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock); 116632a07e44SKalle Valo 116732a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4); 116832a07e44SKalle Valo } 116932a07e44SKalle Valo 1170bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = { 1171bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync, 1172bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async, 1173bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable, 1174bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable, 1175bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get, 1176bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add, 1177bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter, 1178f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter, 1179bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter, 1180abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend, 1181aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume, 1182c7111495SKalle Valo .diag_read32 = ath6kl_sdio_diag_read32, 1183c7111495SKalle Valo .diag_write32 = ath6kl_sdio_diag_write32, 118466b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read, 118566b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write, 1186b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on, 1187b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off, 118832a07e44SKalle Valo .stop = ath6kl_sdio_stop, 1189bdcd8170SKalle Valo }; 1190bdcd8170SKalle Valo 1191b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP 1192b4b2a0b1SKalle Valo 1193b4b2a0b1SKalle Valo /* 1194b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during 1195b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers. 1196b4b2a0b1SKalle Valo */ 1197b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device) 1198b4b2a0b1SKalle Valo { 1199b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n"); 1200b4b2a0b1SKalle Valo 1201b4b2a0b1SKalle Valo return 0; 1202b4b2a0b1SKalle Valo } 1203b4b2a0b1SKalle Valo 1204b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device) 1205b4b2a0b1SKalle Valo { 1206b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n"); 1207b4b2a0b1SKalle Valo 1208b4b2a0b1SKalle Valo return 0; 1209b4b2a0b1SKalle Valo } 1210b4b2a0b1SKalle Valo 1211b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend, 1212b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume); 1213b4b2a0b1SKalle Valo 1214b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops) 1215b4b2a0b1SKalle Valo 1216b4b2a0b1SKalle Valo #else 1217b4b2a0b1SKalle Valo 1218b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL 1219b4b2a0b1SKalle Valo 1220b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */ 1221b4b2a0b1SKalle Valo 1222bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func, 1223bdcd8170SKalle Valo const struct sdio_device_id *id) 1224bdcd8170SKalle Valo { 1225bdcd8170SKalle Valo int ret; 1226bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1227bdcd8170SKalle Valo struct ath6kl *ar; 1228bdcd8170SKalle Valo int count; 1229bdcd8170SKalle Valo 12303ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 12313ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 1232f7325b85SKalle Valo func->num, func->vendor, func->device, 1233f7325b85SKalle Valo func->max_blksize, func->cur_blksize); 1234bdcd8170SKalle Valo 1235bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL); 1236bdcd8170SKalle Valo if (!ar_sdio) 1237bdcd8170SKalle Valo return -ENOMEM; 1238bdcd8170SKalle Valo 1239bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); 1240bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) { 1241bdcd8170SKalle Valo ret = -ENOMEM; 1242bdcd8170SKalle Valo goto err_hif; 1243bdcd8170SKalle Valo } 1244bdcd8170SKalle Valo 1245bdcd8170SKalle Valo ar_sdio->func = func; 1246bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio); 1247bdcd8170SKalle Valo 1248bdcd8170SKalle Valo ar_sdio->id = id; 1249bdcd8170SKalle Valo ar_sdio->is_disabled = true; 1250bdcd8170SKalle Valo 1251bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock); 1252bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock); 1253bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock); 1254fdb28589SRaja Mani mutex_init(&ar_sdio->dma_buffer_mutex); 1255bdcd8170SKalle Valo 1256bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req); 1257bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 1258bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 1259bdcd8170SKalle Valo 1260bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work); 1261bdcd8170SKalle Valo 1262bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) 1263bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]); 1264bdcd8170SKalle Valo 1265bdcd8170SKalle Valo ar = ath6kl_core_alloc(&ar_sdio->func->dev); 1266bdcd8170SKalle Valo if (!ar) { 1267bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n"); 1268bdcd8170SKalle Valo ret = -ENOMEM; 1269bdcd8170SKalle Valo goto err_dma; 1270bdcd8170SKalle Valo } 1271bdcd8170SKalle Valo 1272bdcd8170SKalle Valo ar_sdio->ar = ar; 127377eab1e9SKalle Valo ar->hif_type = ATH6KL_HIF_TYPE_SDIO; 1274bdcd8170SKalle Valo ar->hif_priv = ar_sdio; 1275bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops; 12761f4c894dSKalle Valo ar->bmi.max_data_size = 256; 1277bdcd8170SKalle Valo 1278bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar); 1279bdcd8170SKalle Valo 1280e28e8104SKalle Valo ret = ath6kl_sdio_config(ar); 1281bdcd8170SKalle Valo if (ret) { 1282e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret); 12838dafb70eSVasanthakumar Thiagarajan goto err_core_alloc; 1284bdcd8170SKalle Valo } 1285bdcd8170SKalle Valo 1286bdcd8170SKalle Valo ret = ath6kl_core_init(ar); 1287bdcd8170SKalle Valo if (ret) { 1288bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n"); 1289e28e8104SKalle Valo goto err_core_alloc; 1290bdcd8170SKalle Valo } 1291bdcd8170SKalle Valo 1292bdcd8170SKalle Valo return ret; 1293bdcd8170SKalle Valo 12948dafb70eSVasanthakumar Thiagarajan err_core_alloc: 12958dafb70eSVasanthakumar Thiagarajan ath6kl_core_free(ar_sdio->ar); 1296bdcd8170SKalle Valo err_dma: 1297bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1298bdcd8170SKalle Valo err_hif: 1299bdcd8170SKalle Valo kfree(ar_sdio); 1300bdcd8170SKalle Valo 1301bdcd8170SKalle Valo return ret; 1302bdcd8170SKalle Valo } 1303bdcd8170SKalle Valo 1304bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func) 1305bdcd8170SKalle Valo { 1306bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio; 1307bdcd8170SKalle Valo 13083ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 13093ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n", 1310f7325b85SKalle Valo func->num, func->vendor, func->device); 1311f7325b85SKalle Valo 1312bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func); 1313bdcd8170SKalle Valo 1314bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar); 1315bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work); 1316bdcd8170SKalle Valo 13176db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar); 1318bdcd8170SKalle Valo 1319bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer); 1320bdcd8170SKalle Valo kfree(ar_sdio); 1321bdcd8170SKalle Valo } 1322bdcd8170SKalle Valo 1323bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = { 1324bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))}, 1325bdcd8170SKalle Valo {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))}, 1326d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))}, 1327d93e2c2fSNaveen Gangadharan {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, 1328bdcd8170SKalle Valo {}, 1329bdcd8170SKalle Valo }; 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices); 1332bdcd8170SKalle Valo 1333bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = { 1334fde57764SKalle Valo .name = "ath6kl_sdio", 1335bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices, 1336bdcd8170SKalle Valo .probe = ath6kl_sdio_probe, 1337bdcd8170SKalle Valo .remove = ath6kl_sdio_remove, 1338b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS, 1339bdcd8170SKalle Valo }; 1340bdcd8170SKalle Valo 1341bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void) 1342bdcd8170SKalle Valo { 1343bdcd8170SKalle Valo int ret; 1344bdcd8170SKalle Valo 1345bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver); 1346bdcd8170SKalle Valo if (ret) 1347bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret); 1348bdcd8170SKalle Valo 1349bdcd8170SKalle Valo return ret; 1350bdcd8170SKalle Valo } 1351bdcd8170SKalle Valo 1352bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void) 1353bdcd8170SKalle Valo { 1354bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver); 1355bdcd8170SKalle Valo } 1356bdcd8170SKalle Valo 1357bdcd8170SKalle Valo module_init(ath6kl_sdio_init); 1358bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit); 1359bdcd8170SKalle Valo 1360bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc."); 1361bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices"); 1362bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL"); 1363bdcd8170SKalle Valo 13640d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_OTP_FILE); 13650d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FIRMWARE_FILE); 13660d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_PATCH_FILE); 13670d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE); 13680d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE); 13690d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_OTP_FILE); 13700d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FIRMWARE_FILE); 13710d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_PATCH_FILE); 13720d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE); 13730d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE); 1374f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_FIRMWARE_FILE); 1375f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE); 1376f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE); 1377f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_FIRMWARE_FILE); 1378f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE); 1379f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE); 1380