1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc.
31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4bdcd8170SKalle Valo *
5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any
6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above
7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies.
8bdcd8170SKalle Valo *
9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16bdcd8170SKalle Valo */
17bdcd8170SKalle Valo
189d9779e7SPaul Gortmaker #include <linux/module.h>
19bdcd8170SKalle Valo #include <linux/mmc/card.h>
20bdcd8170SKalle Valo #include <linux/mmc/mmc.h>
21bdcd8170SKalle Valo #include <linux/mmc/host.h>
22bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h>
23bdcd8170SKalle Valo #include <linux/mmc/sdio_ids.h>
24bdcd8170SKalle Valo #include <linux/mmc/sdio.h>
25bdcd8170SKalle Valo #include <linux/mmc/sd.h>
262e1cb23cSKalle Valo #include "hif.h"
27bdcd8170SKalle Valo #include "hif-ops.h"
28bdcd8170SKalle Valo #include "target.h"
29bdcd8170SKalle Valo #include "debug.h"
309df337a1SVivek Natarajan #include "cfg80211.h"
31e60c8154SKalle Valo #include "trace.h"
32bdcd8170SKalle Valo
33bdcd8170SKalle Valo struct ath6kl_sdio {
34bdcd8170SKalle Valo struct sdio_func *func;
35bdcd8170SKalle Valo
3612eb9444SKalle Valo /* protects access to bus_req_freeq */
37bdcd8170SKalle Valo spinlock_t lock;
38bdcd8170SKalle Valo
39bdcd8170SKalle Valo /* free list */
40bdcd8170SKalle Valo struct list_head bus_req_freeq;
41bdcd8170SKalle Valo
42bdcd8170SKalle Valo /* available bus requests */
43bdcd8170SKalle Valo struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
44bdcd8170SKalle Valo
45bdcd8170SKalle Valo struct ath6kl *ar;
46fdb28589SRaja Mani
47bdcd8170SKalle Valo u8 *dma_buffer;
48bdcd8170SKalle Valo
49fdb28589SRaja Mani /* protects access to dma_buffer */
50fdb28589SRaja Mani struct mutex dma_buffer_mutex;
51fdb28589SRaja Mani
52bdcd8170SKalle Valo /* scatter request list head */
53bdcd8170SKalle Valo struct list_head scat_req;
54bdcd8170SKalle Valo
55d1f41597SRaja Mani atomic_t irq_handling;
56d1f41597SRaja Mani wait_queue_head_t irq_wq;
579d82682dSVasanthakumar Thiagarajan
5812eb9444SKalle Valo /* protects access to scat_req */
59bdcd8170SKalle Valo spinlock_t scat_lock;
6012eb9444SKalle Valo
6132a07e44SKalle Valo bool scatter_enabled;
6232a07e44SKalle Valo
63bdcd8170SKalle Valo bool is_disabled;
64bdcd8170SKalle Valo const struct sdio_device_id *id;
65bdcd8170SKalle Valo struct work_struct wr_async_work;
66bdcd8170SKalle Valo struct list_head wr_asyncq;
6712eb9444SKalle Valo
6812eb9444SKalle Valo /* protects access to wr_asyncq */
69bdcd8170SKalle Valo spinlock_t wr_async_lock;
70bdcd8170SKalle Valo };
71bdcd8170SKalle Valo
72bdcd8170SKalle Valo #define CMD53_ARG_READ 0
73bdcd8170SKalle Valo #define CMD53_ARG_WRITE 1
74bdcd8170SKalle Valo #define CMD53_ARG_BLOCK_BASIS 1
75bdcd8170SKalle Valo #define CMD53_ARG_FIXED_ADDRESS 0
76bdcd8170SKalle Valo #define CMD53_ARG_INCR_ADDRESS 1
77bdcd8170SKalle Valo
78fdb6e483SJames Minor static int ath6kl_sdio_config(struct ath6kl *ar);
79fdb6e483SJames Minor
ath6kl_sdio_priv(struct ath6kl * ar)80bdcd8170SKalle Valo static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
81bdcd8170SKalle Valo {
82bdcd8170SKalle Valo return ar->hif_priv;
83bdcd8170SKalle Valo }
84bdcd8170SKalle Valo
85bdcd8170SKalle Valo /*
86bdcd8170SKalle Valo * Macro to check if DMA buffer is WORD-aligned and DMA-able.
87bdcd8170SKalle Valo * Most host controllers assume the buffer is DMA'able and will
88bdcd8170SKalle Valo * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
89bdcd8170SKalle Valo * check fails on stack memory.
90bdcd8170SKalle Valo */
buf_needs_bounce(u8 * buf)91bdcd8170SKalle Valo static inline bool buf_needs_bounce(u8 *buf)
92bdcd8170SKalle Valo {
93bdcd8170SKalle Valo return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
94bdcd8170SKalle Valo }
95bdcd8170SKalle Valo
ath6kl_sdio_set_mbox_info(struct ath6kl * ar)96bdcd8170SKalle Valo static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
97bdcd8170SKalle Valo {
98bdcd8170SKalle Valo struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
99bdcd8170SKalle Valo
100bdcd8170SKalle Valo /* EP1 has an extended range */
101bdcd8170SKalle Valo mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
102bdcd8170SKalle Valo mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
103bdcd8170SKalle Valo mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
104bdcd8170SKalle Valo mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
105bdcd8170SKalle Valo mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
106bdcd8170SKalle Valo mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
107bdcd8170SKalle Valo }
108bdcd8170SKalle Valo
ath6kl_sdio_set_cmd53_arg(u32 * arg,u8 rw,u8 func,u8 mode,u8 opcode,u32 addr,u16 blksz)109bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
110bdcd8170SKalle Valo u8 mode, u8 opcode, u32 addr,
111bdcd8170SKalle Valo u16 blksz)
112bdcd8170SKalle Valo {
113bdcd8170SKalle Valo *arg = (((rw & 1) << 31) |
114bdcd8170SKalle Valo ((func & 0x7) << 28) |
115bdcd8170SKalle Valo ((mode & 1) << 27) |
116bdcd8170SKalle Valo ((opcode & 1) << 26) |
117bdcd8170SKalle Valo ((addr & 0x1FFFF) << 9) |
118bdcd8170SKalle Valo (blksz & 0x1FF));
119bdcd8170SKalle Valo }
120bdcd8170SKalle Valo
ath6kl_sdio_set_cmd52_arg(u32 * arg,u8 write,u8 raw,unsigned int address,unsigned char val)121bdcd8170SKalle Valo static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
122bdcd8170SKalle Valo unsigned int address,
123bdcd8170SKalle Valo unsigned char val)
124bdcd8170SKalle Valo {
125bdcd8170SKalle Valo const u8 func = 0;
126bdcd8170SKalle Valo
127bdcd8170SKalle Valo *arg = ((write & 1) << 31) |
128bdcd8170SKalle Valo ((func & 0x7) << 28) |
129bdcd8170SKalle Valo ((raw & 1) << 27) |
130bdcd8170SKalle Valo (1 << 26) |
131bdcd8170SKalle Valo ((address & 0x1FFFF) << 9) |
132bdcd8170SKalle Valo (1 << 8) |
133bdcd8170SKalle Valo (val & 0xFF);
134bdcd8170SKalle Valo }
135bdcd8170SKalle Valo
ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card * card,unsigned int address,unsigned char byte)136bdcd8170SKalle Valo static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
137bdcd8170SKalle Valo unsigned int address,
138bdcd8170SKalle Valo unsigned char byte)
139bdcd8170SKalle Valo {
140bdcd8170SKalle Valo struct mmc_command io_cmd;
141bdcd8170SKalle Valo
142bdcd8170SKalle Valo memset(&io_cmd, 0, sizeof(io_cmd));
143bdcd8170SKalle Valo ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
144bdcd8170SKalle Valo io_cmd.opcode = SD_IO_RW_DIRECT;
145bdcd8170SKalle Valo io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
146bdcd8170SKalle Valo
147bdcd8170SKalle Valo return mmc_wait_for_cmd(card->host, &io_cmd, 0);
148bdcd8170SKalle Valo }
149bdcd8170SKalle Valo
ath6kl_sdio_io(struct sdio_func * func,u32 request,u32 addr,u8 * buf,u32 len)150da220695SVasanthakumar Thiagarajan static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
151da220695SVasanthakumar Thiagarajan u8 *buf, u32 len)
152da220695SVasanthakumar Thiagarajan {
153da220695SVasanthakumar Thiagarajan int ret = 0;
154da220695SVasanthakumar Thiagarajan
155861dd058SVasanthakumar Thiagarajan sdio_claim_host(func);
156861dd058SVasanthakumar Thiagarajan
157da220695SVasanthakumar Thiagarajan if (request & HIF_WRITE) {
158f7325b85SKalle Valo /* FIXME: looks like ugly workaround for something */
159da220695SVasanthakumar Thiagarajan if (addr >= HIF_MBOX_BASE_ADDR &&
160da220695SVasanthakumar Thiagarajan addr <= HIF_MBOX_END_ADDR)
161da220695SVasanthakumar Thiagarajan addr += (HIF_MBOX_WIDTH - len);
162da220695SVasanthakumar Thiagarajan
163f7325b85SKalle Valo /* FIXME: this also looks like ugly workaround */
164da220695SVasanthakumar Thiagarajan if (addr == HIF_MBOX0_EXT_BASE_ADDR)
165da220695SVasanthakumar Thiagarajan addr += HIF_MBOX0_EXT_WIDTH - len;
166da220695SVasanthakumar Thiagarajan
167da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS)
168da220695SVasanthakumar Thiagarajan ret = sdio_writesb(func, addr, buf, len);
169da220695SVasanthakumar Thiagarajan else
170da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_toio(func, addr, buf, len);
171da220695SVasanthakumar Thiagarajan } else {
172da220695SVasanthakumar Thiagarajan if (request & HIF_FIXED_ADDRESS)
173da220695SVasanthakumar Thiagarajan ret = sdio_readsb(func, buf, addr, len);
174da220695SVasanthakumar Thiagarajan else
175da220695SVasanthakumar Thiagarajan ret = sdio_memcpy_fromio(func, buf, addr, len);
176da220695SVasanthakumar Thiagarajan }
177da220695SVasanthakumar Thiagarajan
178861dd058SVasanthakumar Thiagarajan sdio_release_host(func);
179861dd058SVasanthakumar Thiagarajan
180f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
181f7325b85SKalle Valo request & HIF_WRITE ? "wr" : "rd", addr,
182f7325b85SKalle Valo request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
183f7325b85SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
184f7325b85SKalle Valo
185e60c8154SKalle Valo trace_ath6kl_sdio(addr, request, buf, len);
186e60c8154SKalle Valo
187da220695SVasanthakumar Thiagarajan return ret;
188da220695SVasanthakumar Thiagarajan }
189da220695SVasanthakumar Thiagarajan
ath6kl_sdio_alloc_busreq(struct ath6kl_sdio * ar_sdio)190bdcd8170SKalle Valo static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
191bdcd8170SKalle Valo {
192bdcd8170SKalle Valo struct bus_request *bus_req;
193bdcd8170SKalle Valo
194151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock);
195bdcd8170SKalle Valo
196bdcd8170SKalle Valo if (list_empty(&ar_sdio->bus_req_freeq)) {
197151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock);
198bdcd8170SKalle Valo return NULL;
199bdcd8170SKalle Valo }
200bdcd8170SKalle Valo
201bdcd8170SKalle Valo bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
202bdcd8170SKalle Valo struct bus_request, list);
203bdcd8170SKalle Valo list_del(&bus_req->list);
204bdcd8170SKalle Valo
205151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock);
206f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
207f7325b85SKalle Valo __func__, bus_req);
208bdcd8170SKalle Valo
209bdcd8170SKalle Valo return bus_req;
210bdcd8170SKalle Valo }
211bdcd8170SKalle Valo
ath6kl_sdio_free_bus_req(struct ath6kl_sdio * ar_sdio,struct bus_request * bus_req)212bdcd8170SKalle Valo static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
213bdcd8170SKalle Valo struct bus_request *bus_req)
214bdcd8170SKalle Valo {
215f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
216f7325b85SKalle Valo __func__, bus_req);
217bdcd8170SKalle Valo
218151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->lock);
219bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
220151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->lock);
221bdcd8170SKalle Valo }
222bdcd8170SKalle Valo
ath6kl_sdio_setup_scat_data(struct hif_scatter_req * scat_req,struct mmc_data * data)223bdcd8170SKalle Valo static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
224bdcd8170SKalle Valo struct mmc_data *data)
225bdcd8170SKalle Valo {
226bdcd8170SKalle Valo struct scatterlist *sg;
227bdcd8170SKalle Valo int i;
228bdcd8170SKalle Valo
229bdcd8170SKalle Valo data->blksz = HIF_MBOX_BLOCK_SIZE;
230bdcd8170SKalle Valo data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
231bdcd8170SKalle Valo
232bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER,
233bdcd8170SKalle Valo "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
234bdcd8170SKalle Valo (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
235bdcd8170SKalle Valo data->blksz, data->blocks, scat_req->len,
236bdcd8170SKalle Valo scat_req->scat_entries);
237bdcd8170SKalle Valo
238bdcd8170SKalle Valo data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
239bdcd8170SKalle Valo MMC_DATA_READ;
240bdcd8170SKalle Valo
241bdcd8170SKalle Valo /* fill SG entries */
242d4df7890SVasanthakumar Thiagarajan sg = scat_req->sgentries;
243bdcd8170SKalle Valo sg_init_table(sg, scat_req->scat_entries);
244bdcd8170SKalle Valo
245bdcd8170SKalle Valo /* assemble SG list */
246bdcd8170SKalle Valo for (i = 0; i < scat_req->scat_entries; i++, sg++) {
247bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
248bdcd8170SKalle Valo i, scat_req->scat_list[i].buf,
249bdcd8170SKalle Valo scat_req->scat_list[i].len);
250bdcd8170SKalle Valo
251bdcd8170SKalle Valo sg_set_buf(sg, scat_req->scat_list[i].buf,
252bdcd8170SKalle Valo scat_req->scat_list[i].len);
253bdcd8170SKalle Valo }
254bdcd8170SKalle Valo
255bdcd8170SKalle Valo /* set scatter-gather table for request */
256d4df7890SVasanthakumar Thiagarajan data->sg = scat_req->sgentries;
257bdcd8170SKalle Valo data->sg_len = scat_req->scat_entries;
258bdcd8170SKalle Valo }
259bdcd8170SKalle Valo
ath6kl_sdio_scat_rw(struct ath6kl_sdio * ar_sdio,struct bus_request * req)260bdcd8170SKalle Valo static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
261bdcd8170SKalle Valo struct bus_request *req)
262bdcd8170SKalle Valo {
263bdcd8170SKalle Valo struct mmc_request mmc_req;
264bdcd8170SKalle Valo struct mmc_command cmd;
265bdcd8170SKalle Valo struct mmc_data data;
266bdcd8170SKalle Valo struct hif_scatter_req *scat_req;
267bdcd8170SKalle Valo u8 opcode, rw;
268348a8fbcSVasanthakumar Thiagarajan int status, len;
269bdcd8170SKalle Valo
270bdcd8170SKalle Valo scat_req = req->scat_req;
271bdcd8170SKalle Valo
272348a8fbcSVasanthakumar Thiagarajan if (scat_req->virt_scat) {
273348a8fbcSVasanthakumar Thiagarajan len = scat_req->len;
274348a8fbcSVasanthakumar Thiagarajan if (scat_req->req & HIF_BLOCK_BASIS)
275348a8fbcSVasanthakumar Thiagarajan len = round_down(len, HIF_MBOX_BLOCK_SIZE);
276348a8fbcSVasanthakumar Thiagarajan
277348a8fbcSVasanthakumar Thiagarajan status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
278348a8fbcSVasanthakumar Thiagarajan scat_req->addr, scat_req->virt_dma_buf,
279348a8fbcSVasanthakumar Thiagarajan len);
280348a8fbcSVasanthakumar Thiagarajan goto scat_complete;
281348a8fbcSVasanthakumar Thiagarajan }
282348a8fbcSVasanthakumar Thiagarajan
283bdcd8170SKalle Valo memset(&mmc_req, 0, sizeof(struct mmc_request));
284bdcd8170SKalle Valo memset(&cmd, 0, sizeof(struct mmc_command));
285bdcd8170SKalle Valo memset(&data, 0, sizeof(struct mmc_data));
286bdcd8170SKalle Valo
287d4df7890SVasanthakumar Thiagarajan ath6kl_sdio_setup_scat_data(scat_req, &data);
288bdcd8170SKalle Valo
289bdcd8170SKalle Valo opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
290bdcd8170SKalle Valo CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
291bdcd8170SKalle Valo
292bdcd8170SKalle Valo rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
293bdcd8170SKalle Valo
294bdcd8170SKalle Valo /* Fixup the address so that the last byte will fall on MBOX EOM */
295bdcd8170SKalle Valo if (scat_req->req & HIF_WRITE) {
296bdcd8170SKalle Valo if (scat_req->addr == HIF_MBOX_BASE_ADDR)
297bdcd8170SKalle Valo scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
298bdcd8170SKalle Valo else
299bdcd8170SKalle Valo /* Uses extended address range */
300bdcd8170SKalle Valo scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
301bdcd8170SKalle Valo }
302bdcd8170SKalle Valo
303bdcd8170SKalle Valo /* set command argument */
304bdcd8170SKalle Valo ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
305bdcd8170SKalle Valo CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
306bdcd8170SKalle Valo data.blocks);
307bdcd8170SKalle Valo
308bdcd8170SKalle Valo cmd.opcode = SD_IO_RW_EXTENDED;
309bdcd8170SKalle Valo cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
310bdcd8170SKalle Valo
311bdcd8170SKalle Valo mmc_req.cmd = &cmd;
312bdcd8170SKalle Valo mmc_req.data = &data;
313bdcd8170SKalle Valo
314861dd058SVasanthakumar Thiagarajan sdio_claim_host(ar_sdio->func);
315861dd058SVasanthakumar Thiagarajan
316bdcd8170SKalle Valo mmc_set_data_timeout(&data, ar_sdio->func->card);
317e60c8154SKalle Valo
318e60c8154SKalle Valo trace_ath6kl_sdio_scat(scat_req->addr,
319e60c8154SKalle Valo scat_req->req,
320e60c8154SKalle Valo scat_req->len,
321e60c8154SKalle Valo scat_req->scat_entries,
322e60c8154SKalle Valo scat_req->scat_list);
323e60c8154SKalle Valo
324bdcd8170SKalle Valo /* synchronous call to process request */
325bdcd8170SKalle Valo mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
326bdcd8170SKalle Valo
327861dd058SVasanthakumar Thiagarajan sdio_release_host(ar_sdio->func);
328861dd058SVasanthakumar Thiagarajan
329bdcd8170SKalle Valo status = cmd.error ? cmd.error : data.error;
330348a8fbcSVasanthakumar Thiagarajan
331348a8fbcSVasanthakumar Thiagarajan scat_complete:
332bdcd8170SKalle Valo scat_req->status = status;
333bdcd8170SKalle Valo
334bdcd8170SKalle Valo if (scat_req->status)
335bdcd8170SKalle Valo ath6kl_err("Scatter write request failed:%d\n",
336bdcd8170SKalle Valo scat_req->status);
337bdcd8170SKalle Valo
338bdcd8170SKalle Valo if (scat_req->req & HIF_ASYNCHRONOUS)
339e041c7f9SVasanthakumar Thiagarajan scat_req->complete(ar_sdio->ar->htc_target, scat_req);
340bdcd8170SKalle Valo
341bdcd8170SKalle Valo return status;
342bdcd8170SKalle Valo }
343bdcd8170SKalle Valo
ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio * ar_sdio,int n_scat_entry,int n_scat_req,bool virt_scat)3443df505adSVasanthakumar Thiagarajan static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
3453df505adSVasanthakumar Thiagarajan int n_scat_entry, int n_scat_req,
3463df505adSVasanthakumar Thiagarajan bool virt_scat)
3473df505adSVasanthakumar Thiagarajan {
3483df505adSVasanthakumar Thiagarajan struct hif_scatter_req *s_req;
3493df505adSVasanthakumar Thiagarajan struct bus_request *bus_req;
35037291fc6SGeert Uytterhoeven int i, scat_req_sz, scat_list_sz, size;
351cfeab10bSVasanthakumar Thiagarajan u8 *virt_buf;
3523df505adSVasanthakumar Thiagarajan
35331b9cc9aSKalle Valo scat_list_sz = n_scat_entry * sizeof(struct hif_scatter_item);
3543df505adSVasanthakumar Thiagarajan scat_req_sz = sizeof(*s_req) + scat_list_sz;
3553df505adSVasanthakumar Thiagarajan
3563df505adSVasanthakumar Thiagarajan if (!virt_scat)
35737291fc6SGeert Uytterhoeven size = sizeof(struct scatterlist) * n_scat_entry;
358cfeab10bSVasanthakumar Thiagarajan else
35937291fc6SGeert Uytterhoeven size = 2 * L1_CACHE_BYTES +
360cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
3613df505adSVasanthakumar Thiagarajan
3623df505adSVasanthakumar Thiagarajan for (i = 0; i < n_scat_req; i++) {
3633df505adSVasanthakumar Thiagarajan /* allocate the scatter request */
3643df505adSVasanthakumar Thiagarajan s_req = kzalloc(scat_req_sz, GFP_KERNEL);
3653df505adSVasanthakumar Thiagarajan if (!s_req)
3663df505adSVasanthakumar Thiagarajan return -ENOMEM;
3673df505adSVasanthakumar Thiagarajan
368cfeab10bSVasanthakumar Thiagarajan if (virt_scat) {
36937291fc6SGeert Uytterhoeven virt_buf = kzalloc(size, GFP_KERNEL);
370cfeab10bSVasanthakumar Thiagarajan if (!virt_buf) {
371cfeab10bSVasanthakumar Thiagarajan kfree(s_req);
372cfeab10bSVasanthakumar Thiagarajan return -ENOMEM;
373cfeab10bSVasanthakumar Thiagarajan }
374cfeab10bSVasanthakumar Thiagarajan
375cfeab10bSVasanthakumar Thiagarajan s_req->virt_dma_buf =
376cfeab10bSVasanthakumar Thiagarajan (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
377cfeab10bSVasanthakumar Thiagarajan } else {
3783df505adSVasanthakumar Thiagarajan /* allocate sglist */
37937291fc6SGeert Uytterhoeven s_req->sgentries = kzalloc(size, GFP_KERNEL);
3803df505adSVasanthakumar Thiagarajan
3813df505adSVasanthakumar Thiagarajan if (!s_req->sgentries) {
3823df505adSVasanthakumar Thiagarajan kfree(s_req);
3833df505adSVasanthakumar Thiagarajan return -ENOMEM;
3843df505adSVasanthakumar Thiagarajan }
3853df505adSVasanthakumar Thiagarajan }
3863df505adSVasanthakumar Thiagarajan
3873df505adSVasanthakumar Thiagarajan /* allocate a bus request for this scatter request */
3883df505adSVasanthakumar Thiagarajan bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
3893df505adSVasanthakumar Thiagarajan if (!bus_req) {
3903df505adSVasanthakumar Thiagarajan kfree(s_req->sgentries);
391cfeab10bSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf);
3923df505adSVasanthakumar Thiagarajan kfree(s_req);
3933df505adSVasanthakumar Thiagarajan return -ENOMEM;
3943df505adSVasanthakumar Thiagarajan }
3953df505adSVasanthakumar Thiagarajan
3963df505adSVasanthakumar Thiagarajan /* assign the scatter request to this bus request */
3973df505adSVasanthakumar Thiagarajan bus_req->scat_req = s_req;
3983df505adSVasanthakumar Thiagarajan s_req->busrequest = bus_req;
3993df505adSVasanthakumar Thiagarajan
4004a005c3eSVasanthakumar Thiagarajan s_req->virt_scat = virt_scat;
4014a005c3eSVasanthakumar Thiagarajan
4023df505adSVasanthakumar Thiagarajan /* add it to the scatter pool */
4033df505adSVasanthakumar Thiagarajan hif_scatter_req_add(ar_sdio->ar, s_req);
4043df505adSVasanthakumar Thiagarajan }
4053df505adSVasanthakumar Thiagarajan
4063df505adSVasanthakumar Thiagarajan return 0;
4073df505adSVasanthakumar Thiagarajan }
4083df505adSVasanthakumar Thiagarajan
ath6kl_sdio_read_write_sync(struct ath6kl * ar,u32 addr,u8 * buf,u32 len,u32 request)409bdcd8170SKalle Valo static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
410bdcd8170SKalle Valo u32 len, u32 request)
411bdcd8170SKalle Valo {
412bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
413bdcd8170SKalle Valo u8 *tbuf = NULL;
414bdcd8170SKalle Valo int ret;
415bdcd8170SKalle Valo bool bounced = false;
416bdcd8170SKalle Valo
417bdcd8170SKalle Valo if (request & HIF_BLOCK_BASIS)
418bdcd8170SKalle Valo len = round_down(len, HIF_MBOX_BLOCK_SIZE);
419bdcd8170SKalle Valo
420bdcd8170SKalle Valo if (buf_needs_bounce(buf)) {
421bdcd8170SKalle Valo if (!ar_sdio->dma_buffer)
422bdcd8170SKalle Valo return -ENOMEM;
423fdb28589SRaja Mani mutex_lock(&ar_sdio->dma_buffer_mutex);
424bdcd8170SKalle Valo tbuf = ar_sdio->dma_buffer;
425daa16bc5SRaja Mani
426daa16bc5SRaja Mani if (request & HIF_WRITE)
427bdcd8170SKalle Valo memcpy(tbuf, buf, len);
428daa16bc5SRaja Mani
429bdcd8170SKalle Valo bounced = true;
430a5d8f9dfSKalle Valo } else {
431bdcd8170SKalle Valo tbuf = buf;
432a5d8f9dfSKalle Valo }
433bdcd8170SKalle Valo
434da220695SVasanthakumar Thiagarajan ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
435da220695SVasanthakumar Thiagarajan if ((request & HIF_READ) && bounced)
436bdcd8170SKalle Valo memcpy(buf, tbuf, len);
437bdcd8170SKalle Valo
438fdb28589SRaja Mani if (bounced)
439fdb28589SRaja Mani mutex_unlock(&ar_sdio->dma_buffer_mutex);
440fdb28589SRaja Mani
441bdcd8170SKalle Valo return ret;
442bdcd8170SKalle Valo }
443bdcd8170SKalle Valo
__ath6kl_sdio_write_async(struct ath6kl_sdio * ar_sdio,struct bus_request * req)444bdcd8170SKalle Valo static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
445bdcd8170SKalle Valo struct bus_request *req)
446bdcd8170SKalle Valo {
447a5d8f9dfSKalle Valo if (req->scat_req) {
448bdcd8170SKalle Valo ath6kl_sdio_scat_rw(ar_sdio, req);
449a5d8f9dfSKalle Valo } else {
450bdcd8170SKalle Valo void *context;
451bdcd8170SKalle Valo int status;
452bdcd8170SKalle Valo
453bdcd8170SKalle Valo status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
454bdcd8170SKalle Valo req->buffer, req->length,
455bdcd8170SKalle Valo req->request);
456bdcd8170SKalle Valo context = req->packet;
457bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req);
4588e8ddb2bSKalle Valo ath6kl_hif_rw_comp_handler(context, status);
459bdcd8170SKalle Valo }
460bdcd8170SKalle Valo }
461bdcd8170SKalle Valo
ath6kl_sdio_write_async_work(struct work_struct * work)462bdcd8170SKalle Valo static void ath6kl_sdio_write_async_work(struct work_struct *work)
463bdcd8170SKalle Valo {
464bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio;
465bdcd8170SKalle Valo struct bus_request *req, *tmp_req;
466bdcd8170SKalle Valo
467bdcd8170SKalle Valo ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
468bdcd8170SKalle Valo
469151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock);
470bdcd8170SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
471bdcd8170SKalle Valo list_del(&req->list);
472151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock);
473bdcd8170SKalle Valo __ath6kl_sdio_write_async(ar_sdio, req);
474151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock);
475bdcd8170SKalle Valo }
476151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock);
477bdcd8170SKalle Valo }
478bdcd8170SKalle Valo
ath6kl_sdio_irq_handler(struct sdio_func * func)479bdcd8170SKalle Valo static void ath6kl_sdio_irq_handler(struct sdio_func *func)
480bdcd8170SKalle Valo {
481bdcd8170SKalle Valo int status;
482bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio;
483bdcd8170SKalle Valo
484f7325b85SKalle Valo ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
485f7325b85SKalle Valo
486bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func);
487d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 1);
488bdcd8170SKalle Valo /*
489bdcd8170SKalle Valo * Release the host during interrups so we can pick it back up when
490bdcd8170SKalle Valo * we process commands.
491bdcd8170SKalle Valo */
492bdcd8170SKalle Valo sdio_release_host(ar_sdio->func);
493bdcd8170SKalle Valo
4948e8ddb2bSKalle Valo status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
495bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func);
496d1f41597SRaja Mani
497d1f41597SRaja Mani atomic_set(&ar_sdio->irq_handling, 0);
498d1f41597SRaja Mani wake_up(&ar_sdio->irq_wq);
499d1f41597SRaja Mani
500bdcd8170SKalle Valo WARN_ON(status && status != -ECANCELED);
501bdcd8170SKalle Valo }
502bdcd8170SKalle Valo
ath6kl_sdio_power_on(struct ath6kl * ar)503b2e75698SKalle Valo static int ath6kl_sdio_power_on(struct ath6kl *ar)
504bdcd8170SKalle Valo {
505b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
506bdcd8170SKalle Valo struct sdio_func *func = ar_sdio->func;
507bdcd8170SKalle Valo int ret = 0;
508bdcd8170SKalle Valo
509bdcd8170SKalle Valo if (!ar_sdio->is_disabled)
510bdcd8170SKalle Valo return 0;
511bdcd8170SKalle Valo
5123ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
5133ef987beSKalle Valo
514bdcd8170SKalle Valo sdio_claim_host(func);
515bdcd8170SKalle Valo
516bdcd8170SKalle Valo ret = sdio_enable_func(func);
517bdcd8170SKalle Valo if (ret) {
518bdcd8170SKalle Valo ath6kl_err("Unable to enable sdio func: %d)\n", ret);
519bdcd8170SKalle Valo sdio_release_host(func);
520bdcd8170SKalle Valo return ret;
521bdcd8170SKalle Valo }
522bdcd8170SKalle Valo
523bdcd8170SKalle Valo sdio_release_host(func);
524bdcd8170SKalle Valo
525bdcd8170SKalle Valo /*
526bdcd8170SKalle Valo * Wait for hardware to initialise. It should take a lot less than
527bdcd8170SKalle Valo * 10 ms but let's be conservative here.
528bdcd8170SKalle Valo */
529bdcd8170SKalle Valo msleep(10);
530bdcd8170SKalle Valo
531fdb6e483SJames Minor ret = ath6kl_sdio_config(ar);
532fdb6e483SJames Minor if (ret) {
533fdb6e483SJames Minor ath6kl_err("Failed to config sdio: %d\n", ret);
534fdb6e483SJames Minor goto out;
535fdb6e483SJames Minor }
536fdb6e483SJames Minor
537bdcd8170SKalle Valo ar_sdio->is_disabled = false;
538bdcd8170SKalle Valo
539fdb6e483SJames Minor out:
540bdcd8170SKalle Valo return ret;
541bdcd8170SKalle Valo }
542bdcd8170SKalle Valo
ath6kl_sdio_power_off(struct ath6kl * ar)543b2e75698SKalle Valo static int ath6kl_sdio_power_off(struct ath6kl *ar)
544bdcd8170SKalle Valo {
545b2e75698SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
546bdcd8170SKalle Valo int ret;
547bdcd8170SKalle Valo
548bdcd8170SKalle Valo if (ar_sdio->is_disabled)
549bdcd8170SKalle Valo return 0;
550bdcd8170SKalle Valo
5513ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
5523ef987beSKalle Valo
553bdcd8170SKalle Valo /* Disable the card */
554bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func);
555bdcd8170SKalle Valo ret = sdio_disable_func(ar_sdio->func);
556bdcd8170SKalle Valo sdio_release_host(ar_sdio->func);
557bdcd8170SKalle Valo
558bdcd8170SKalle Valo if (ret)
559bdcd8170SKalle Valo return ret;
560bdcd8170SKalle Valo
561bdcd8170SKalle Valo ar_sdio->is_disabled = true;
562bdcd8170SKalle Valo
563bdcd8170SKalle Valo return ret;
564bdcd8170SKalle Valo }
565bdcd8170SKalle Valo
ath6kl_sdio_write_async(struct ath6kl * ar,u32 address,u8 * buffer,u32 length,u32 request,struct htc_packet * packet)566bdcd8170SKalle Valo static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
567bdcd8170SKalle Valo u32 length, u32 request,
568bdcd8170SKalle Valo struct htc_packet *packet)
569bdcd8170SKalle Valo {
570bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
571bdcd8170SKalle Valo struct bus_request *bus_req;
572bdcd8170SKalle Valo
573bdcd8170SKalle Valo bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
574bdcd8170SKalle Valo
57593b42caeSVasanthakumar Thiagarajan if (WARN_ON_ONCE(!bus_req))
576bdcd8170SKalle Valo return -ENOMEM;
577bdcd8170SKalle Valo
578bdcd8170SKalle Valo bus_req->address = address;
579bdcd8170SKalle Valo bus_req->buffer = buffer;
580bdcd8170SKalle Valo bus_req->length = length;
581bdcd8170SKalle Valo bus_req->request = request;
582bdcd8170SKalle Valo bus_req->packet = packet;
583bdcd8170SKalle Valo
584151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock);
585bdcd8170SKalle Valo list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
586151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock);
587bdcd8170SKalle Valo queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
588bdcd8170SKalle Valo
589bdcd8170SKalle Valo return 0;
590bdcd8170SKalle Valo }
591bdcd8170SKalle Valo
ath6kl_sdio_irq_enable(struct ath6kl * ar)592bdcd8170SKalle Valo static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
593bdcd8170SKalle Valo {
594bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
595bdcd8170SKalle Valo int ret;
596bdcd8170SKalle Valo
597bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func);
598bdcd8170SKalle Valo
599bdcd8170SKalle Valo /* Register the isr */
600bdcd8170SKalle Valo ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
601bdcd8170SKalle Valo if (ret)
602bdcd8170SKalle Valo ath6kl_err("Failed to claim sdio irq: %d\n", ret);
603bdcd8170SKalle Valo
604bdcd8170SKalle Valo sdio_release_host(ar_sdio->func);
605bdcd8170SKalle Valo }
606bdcd8170SKalle Valo
ath6kl_sdio_is_on_irq(struct ath6kl * ar)607d1f41597SRaja Mani static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar)
608d1f41597SRaja Mani {
609d1f41597SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
610d1f41597SRaja Mani
611d1f41597SRaja Mani return !atomic_read(&ar_sdio->irq_handling);
612d1f41597SRaja Mani }
613d1f41597SRaja Mani
ath6kl_sdio_irq_disable(struct ath6kl * ar)614bdcd8170SKalle Valo static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
615bdcd8170SKalle Valo {
616bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
617bdcd8170SKalle Valo int ret;
618bdcd8170SKalle Valo
619bdcd8170SKalle Valo sdio_claim_host(ar_sdio->func);
620bdcd8170SKalle Valo
621d1f41597SRaja Mani if (atomic_read(&ar_sdio->irq_handling)) {
622d1f41597SRaja Mani sdio_release_host(ar_sdio->func);
623d1f41597SRaja Mani
624d1f41597SRaja Mani ret = wait_event_interruptible(ar_sdio->irq_wq,
625d1f41597SRaja Mani ath6kl_sdio_is_on_irq(ar));
626d1f41597SRaja Mani if (ret)
627d1f41597SRaja Mani return;
628d1f41597SRaja Mani
629d1f41597SRaja Mani sdio_claim_host(ar_sdio->func);
630d1f41597SRaja Mani }
631bdcd8170SKalle Valo
632bdcd8170SKalle Valo ret = sdio_release_irq(ar_sdio->func);
633bdcd8170SKalle Valo if (ret)
634bdcd8170SKalle Valo ath6kl_err("Failed to release sdio irq: %d\n", ret);
635bdcd8170SKalle Valo
636bdcd8170SKalle Valo sdio_release_host(ar_sdio->func);
637bdcd8170SKalle Valo }
638bdcd8170SKalle Valo
ath6kl_sdio_scatter_req_get(struct ath6kl * ar)639bdcd8170SKalle Valo static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
640bdcd8170SKalle Valo {
641bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
642bdcd8170SKalle Valo struct hif_scatter_req *node = NULL;
643bdcd8170SKalle Valo
644151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock);
645bdcd8170SKalle Valo
646bdcd8170SKalle Valo if (!list_empty(&ar_sdio->scat_req)) {
647bdcd8170SKalle Valo node = list_first_entry(&ar_sdio->scat_req,
648bdcd8170SKalle Valo struct hif_scatter_req, list);
649bdcd8170SKalle Valo list_del(&node->list);
650b29072ccSChilam Ng
651b29072ccSChilam Ng node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req);
652bdcd8170SKalle Valo }
653bdcd8170SKalle Valo
654151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock);
655bdcd8170SKalle Valo
656bdcd8170SKalle Valo return node;
657bdcd8170SKalle Valo }
658bdcd8170SKalle Valo
ath6kl_sdio_scatter_req_add(struct ath6kl * ar,struct hif_scatter_req * s_req)659bdcd8170SKalle Valo static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
660bdcd8170SKalle Valo struct hif_scatter_req *s_req)
661bdcd8170SKalle Valo {
662bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
663bdcd8170SKalle Valo
664151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock);
665bdcd8170SKalle Valo
666bdcd8170SKalle Valo list_add_tail(&s_req->list, &ar_sdio->scat_req);
667bdcd8170SKalle Valo
668151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock);
669bdcd8170SKalle Valo }
670bdcd8170SKalle Valo
671c630d18aSVasanthakumar Thiagarajan /* scatter gather read write request */
ath6kl_sdio_async_rw_scatter(struct ath6kl * ar,struct hif_scatter_req * scat_req)672c630d18aSVasanthakumar Thiagarajan static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
673c630d18aSVasanthakumar Thiagarajan struct hif_scatter_req *scat_req)
674c630d18aSVasanthakumar Thiagarajan {
675c630d18aSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
676c630d18aSVasanthakumar Thiagarajan u32 request = scat_req->req;
677c630d18aSVasanthakumar Thiagarajan int status = 0;
678c630d18aSVasanthakumar Thiagarajan
679c630d18aSVasanthakumar Thiagarajan if (!scat_req->len)
680c630d18aSVasanthakumar Thiagarajan return -EINVAL;
681c630d18aSVasanthakumar Thiagarajan
682c630d18aSVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_SCATTER,
683c630d18aSVasanthakumar Thiagarajan "hif-scatter: total len: %d scatter entries: %d\n",
684c630d18aSVasanthakumar Thiagarajan scat_req->len, scat_req->scat_entries);
685c630d18aSVasanthakumar Thiagarajan
686a5d8f9dfSKalle Valo if (request & HIF_SYNCHRONOUS) {
687d4df7890SVasanthakumar Thiagarajan status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
688a5d8f9dfSKalle Valo } else {
689151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->wr_async_lock);
690d4df7890SVasanthakumar Thiagarajan list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
691151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->wr_async_lock);
692c630d18aSVasanthakumar Thiagarajan queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
693c630d18aSVasanthakumar Thiagarajan }
694c630d18aSVasanthakumar Thiagarajan
695c630d18aSVasanthakumar Thiagarajan return status;
696c630d18aSVasanthakumar Thiagarajan }
697c630d18aSVasanthakumar Thiagarajan
69818a0f93eSVasanthakumar Thiagarajan /* clean up scatter support */
ath6kl_sdio_cleanup_scatter(struct ath6kl * ar)69918a0f93eSVasanthakumar Thiagarajan static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
70018a0f93eSVasanthakumar Thiagarajan {
70118a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
70218a0f93eSVasanthakumar Thiagarajan struct hif_scatter_req *s_req, *tmp_req;
70318a0f93eSVasanthakumar Thiagarajan
70418a0f93eSVasanthakumar Thiagarajan /* empty the free list */
705151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock);
70618a0f93eSVasanthakumar Thiagarajan list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
70718a0f93eSVasanthakumar Thiagarajan list_del(&s_req->list);
708151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock);
70918a0f93eSVasanthakumar Thiagarajan
71032a07e44SKalle Valo /*
71132a07e44SKalle Valo * FIXME: should we also call completion handler with
71232a07e44SKalle Valo * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
71332a07e44SKalle Valo * that the packet is properly freed?
71432a07e44SKalle Valo */
7153605d751SJames Minor if (s_req->busrequest) {
71696d179b5SWei Yongjun s_req->busrequest->scat_req = NULL;
71718a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
7183605d751SJames Minor }
71918a0f93eSVasanthakumar Thiagarajan kfree(s_req->virt_dma_buf);
72018a0f93eSVasanthakumar Thiagarajan kfree(s_req->sgentries);
72118a0f93eSVasanthakumar Thiagarajan kfree(s_req);
72218a0f93eSVasanthakumar Thiagarajan
723151bd30bSVasanthakumar Thiagarajan spin_lock_bh(&ar_sdio->scat_lock);
72418a0f93eSVasanthakumar Thiagarajan }
725151bd30bSVasanthakumar Thiagarajan spin_unlock_bh(&ar_sdio->scat_lock);
726db14b18aSJames Minor
727db14b18aSJames Minor ar_sdio->scatter_enabled = false;
72818a0f93eSVasanthakumar Thiagarajan }
72918a0f93eSVasanthakumar Thiagarajan
73018a0f93eSVasanthakumar Thiagarajan /* setup of HIF scatter resources */
ath6kl_sdio_enable_scatter(struct ath6kl * ar)73150745af7SVasanthakumar Thiagarajan static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
73218a0f93eSVasanthakumar Thiagarajan {
73318a0f93eSVasanthakumar Thiagarajan struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
73450745af7SVasanthakumar Thiagarajan struct htc_target *target = ar->htc_target;
735527f6570SAndi Kleen int ret = 0;
736cfeab10bSVasanthakumar Thiagarajan bool virt_scat = false;
73718a0f93eSVasanthakumar Thiagarajan
73832a07e44SKalle Valo if (ar_sdio->scatter_enabled)
73932a07e44SKalle Valo return 0;
74032a07e44SKalle Valo
74132a07e44SKalle Valo ar_sdio->scatter_enabled = true;
74232a07e44SKalle Valo
74318a0f93eSVasanthakumar Thiagarajan /* check if host supports scatter and it meets our requirements */
74418a0f93eSVasanthakumar Thiagarajan if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
745cfeab10bSVasanthakumar Thiagarajan ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
74618a0f93eSVasanthakumar Thiagarajan ar_sdio->func->card->host->max_segs,
74718a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ);
748cfeab10bSVasanthakumar Thiagarajan virt_scat = true;
74918a0f93eSVasanthakumar Thiagarajan }
75018a0f93eSVasanthakumar Thiagarajan
751cfeab10bSVasanthakumar Thiagarajan if (!virt_scat) {
75218a0f93eSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
75318a0f93eSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ,
754cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS, virt_scat);
755cfeab10bSVasanthakumar Thiagarajan
756cfeab10bSVasanthakumar Thiagarajan if (!ret) {
7573ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
7583ef987beSKalle Valo "hif-scatter enabled requests %d entries %d\n",
759cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQUESTS,
760cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_ENTRIES_PER_REQ);
761cfeab10bSVasanthakumar Thiagarajan
76250745af7SVasanthakumar Thiagarajan target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
76350745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq =
764cfeab10bSVasanthakumar Thiagarajan MAX_SCATTER_REQ_TRANSFER_SIZE;
765cfeab10bSVasanthakumar Thiagarajan } else {
766cfeab10bSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar);
767cfeab10bSVasanthakumar Thiagarajan ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
768cfeab10bSVasanthakumar Thiagarajan }
769cfeab10bSVasanthakumar Thiagarajan }
770cfeab10bSVasanthakumar Thiagarajan
771cfeab10bSVasanthakumar Thiagarajan if (virt_scat || ret) {
772cfeab10bSVasanthakumar Thiagarajan ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
773cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_ENTRIES_PER_REQ,
774cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, virt_scat);
775cfeab10bSVasanthakumar Thiagarajan
77618a0f93eSVasanthakumar Thiagarajan if (ret) {
777cfeab10bSVasanthakumar Thiagarajan ath6kl_err("failed to alloc virtual scatter resources !\n");
77818a0f93eSVasanthakumar Thiagarajan ath6kl_sdio_cleanup_scatter(ar);
77918a0f93eSVasanthakumar Thiagarajan return ret;
78018a0f93eSVasanthakumar Thiagarajan }
78118a0f93eSVasanthakumar Thiagarajan
7823ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
7833ef987beSKalle Valo "virtual scatter enabled requests %d entries %d\n",
784cfeab10bSVasanthakumar Thiagarajan ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
785cfeab10bSVasanthakumar Thiagarajan
78650745af7SVasanthakumar Thiagarajan target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
78750745af7SVasanthakumar Thiagarajan target->max_xfer_szper_scatreq =
788cfeab10bSVasanthakumar Thiagarajan ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
789cfeab10bSVasanthakumar Thiagarajan }
790cfeab10bSVasanthakumar Thiagarajan
79118a0f93eSVasanthakumar Thiagarajan return 0;
79218a0f93eSVasanthakumar Thiagarajan }
79318a0f93eSVasanthakumar Thiagarajan
ath6kl_sdio_config(struct ath6kl * ar)794e28e8104SKalle Valo static int ath6kl_sdio_config(struct ath6kl *ar)
795e28e8104SKalle Valo {
796e28e8104SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
797e28e8104SKalle Valo struct sdio_func *func = ar_sdio->func;
798e28e8104SKalle Valo int ret;
799e28e8104SKalle Valo
800e28e8104SKalle Valo sdio_claim_host(func);
801e28e8104SKalle Valo
802ecc2f396SPali Rohár if (ar_sdio->id->device >= SDIO_DEVICE_ID_ATHEROS_AR6003_00) {
803e28e8104SKalle Valo /* enable 4-bit ASYNC interrupt on AR6003 or later */
804e28e8104SKalle Valo ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
805e28e8104SKalle Valo CCCR_SDIO_IRQ_MODE_REG,
806e28e8104SKalle Valo SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
807e28e8104SKalle Valo if (ret) {
808e28e8104SKalle Valo ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
809e28e8104SKalle Valo ret);
810e28e8104SKalle Valo goto out;
811e28e8104SKalle Valo }
812e28e8104SKalle Valo
813e28e8104SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
814e28e8104SKalle Valo }
815e28e8104SKalle Valo
816e28e8104SKalle Valo /* give us some time to enable, in ms */
817e28e8104SKalle Valo func->enable_timeout = 100;
818e28e8104SKalle Valo
819e28e8104SKalle Valo ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
820e28e8104SKalle Valo if (ret) {
821e28e8104SKalle Valo ath6kl_err("Set sdio block size %d failed: %d)\n",
822e28e8104SKalle Valo HIF_MBOX_BLOCK_SIZE, ret);
823e28e8104SKalle Valo goto out;
824e28e8104SKalle Valo }
825e28e8104SKalle Valo
826e28e8104SKalle Valo out:
827e28e8104SKalle Valo sdio_release_host(func);
828e28e8104SKalle Valo
829e28e8104SKalle Valo return ret;
830e28e8104SKalle Valo }
831e28e8104SKalle Valo
ath6kl_set_sdio_pm_caps(struct ath6kl * ar)832e390af77SRaja Mani static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar)
833abcb344bSKalle Valo {
834abcb344bSKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
835abcb344bSKalle Valo struct sdio_func *func = ar_sdio->func;
836abcb344bSKalle Valo mmc_pm_flag_t flags;
837abcb344bSKalle Valo int ret;
838abcb344bSKalle Valo
839abcb344bSKalle Valo flags = sdio_get_host_pm_caps(func);
840abcb344bSKalle Valo
841b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
842b4b2a0b1SKalle Valo
843e390af77SRaja Mani if (!(flags & MMC_PM_WAKE_SDIO_IRQ) ||
844e390af77SRaja Mani !(flags & MMC_PM_KEEP_POWER))
845e390af77SRaja Mani return -EINVAL;
846abcb344bSKalle Valo
847abcb344bSKalle Valo ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
848abcb344bSKalle Valo if (ret) {
849e390af77SRaja Mani ath6kl_err("set sdio keep pwr flag failed: %d\n", ret);
850abcb344bSKalle Valo return ret;
851abcb344bSKalle Valo }
852abcb344bSKalle Valo
85310509f90SKalle Valo /* sdio irq wakes up host */
854d7c44e0bSRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
855d7c44e0bSRaja Mani if (ret)
856d7c44e0bSRaja Mani ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
857d7c44e0bSRaja Mani
858d7c44e0bSRaja Mani return ret;
859d7c44e0bSRaja Mani }
860d7c44e0bSRaja Mani
ath6kl_sdio_suspend(struct ath6kl * ar,struct cfg80211_wowlan * wow)861e390af77SRaja Mani static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
862e390af77SRaja Mani {
863e390af77SRaja Mani struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
864e390af77SRaja Mani struct sdio_func *func = ar_sdio->func;
865e390af77SRaja Mani mmc_pm_flag_t flags;
8661e9a905dSRaja Mani bool try_deepsleep = false;
867e390af77SRaja Mani int ret;
868e390af77SRaja Mani
869e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_WOW ||
870e390af77SRaja Mani (!ar->suspend_mode && wow)) {
871e390af77SRaja Mani ret = ath6kl_set_sdio_pm_caps(ar);
872e390af77SRaja Mani if (ret)
873e390af77SRaja Mani goto cut_pwr;
874e390af77SRaja Mani
875e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
8761e9a905dSRaja Mani if (ret && ret != -ENOTCONN)
8771e9a905dSRaja Mani ath6kl_err("wow suspend failed: %d\n", ret);
878e390af77SRaja Mani
8797433a490SKalle Valo if (ret &&
8807433a490SKalle Valo (!ar->wow_suspend_mode ||
8811e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP))
8821e9a905dSRaja Mani try_deepsleep = true;
8831e9a905dSRaja Mani else if (ret &&
8841e9a905dSRaja Mani ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR)
8851e9a905dSRaja Mani goto cut_pwr;
8861e9a905dSRaja Mani if (!ret)
887e390af77SRaja Mani return 0;
888e390af77SRaja Mani }
889e390af77SRaja Mani
890e390af77SRaja Mani if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP ||
8911e9a905dSRaja Mani !ar->suspend_mode || try_deepsleep) {
892e390af77SRaja Mani flags = sdio_get_host_pm_caps(func);
893e390af77SRaja Mani if (!(flags & MMC_PM_KEEP_POWER))
894e390af77SRaja Mani goto cut_pwr;
895e390af77SRaja Mani
896e390af77SRaja Mani ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
897e390af77SRaja Mani if (ret)
898e390af77SRaja Mani goto cut_pwr;
899e390af77SRaja Mani
900cca4d5adSSantosh Sajjan /*
901cca4d5adSSantosh Sajjan * Workaround to support Deep Sleep with MSM, set the host pm
902cca4d5adSSantosh Sajjan * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable
903cca4d5adSSantosh Sajjan * the sdc2_clock and internally allows MSM to enter
904cca4d5adSSantosh Sajjan * TCXO shutdown properly.
905cca4d5adSSantosh Sajjan */
906cca4d5adSSantosh Sajjan if ((flags & MMC_PM_WAKE_SDIO_IRQ)) {
907cca4d5adSSantosh Sajjan ret = sdio_set_host_pm_flags(func,
908cca4d5adSSantosh Sajjan MMC_PM_WAKE_SDIO_IRQ);
909cca4d5adSSantosh Sajjan if (ret)
910cca4d5adSSantosh Sajjan goto cut_pwr;
911cca4d5adSSantosh Sajjan }
912cca4d5adSSantosh Sajjan
913e390af77SRaja Mani ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP,
914e390af77SRaja Mani NULL);
915e390af77SRaja Mani if (ret)
916e390af77SRaja Mani goto cut_pwr;
917e390af77SRaja Mani
918e390af77SRaja Mani return 0;
919e390af77SRaja Mani }
920e390af77SRaja Mani
921e390af77SRaja Mani cut_pwr:
9225699257fSMing Jiang if (func->card && func->card->host)
9235699257fSMing Jiang func->card->host->pm_flags &= ~MMC_PM_KEEP_POWER;
9245699257fSMing Jiang
925e390af77SRaja Mani return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL);
926abcb344bSKalle Valo }
927abcb344bSKalle Valo
ath6kl_sdio_resume(struct ath6kl * ar)928aa6cffc1SChilam Ng static int ath6kl_sdio_resume(struct ath6kl *ar)
929aa6cffc1SChilam Ng {
930b4b2a0b1SKalle Valo switch (ar->state) {
931b4b2a0b1SKalle Valo case ATH6KL_STATE_OFF:
932b4b2a0b1SKalle Valo case ATH6KL_STATE_CUTPOWER:
933b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND,
934b4b2a0b1SKalle Valo "sdio resume configuring sdio\n");
935b4b2a0b1SKalle Valo
936b4b2a0b1SKalle Valo /* need to set sdio settings after power is cut from sdio */
937b4b2a0b1SKalle Valo ath6kl_sdio_config(ar);
938b4b2a0b1SKalle Valo break;
939b4b2a0b1SKalle Valo
940b4b2a0b1SKalle Valo case ATH6KL_STATE_ON:
941b4b2a0b1SKalle Valo break;
942b4b2a0b1SKalle Valo
943b4b2a0b1SKalle Valo case ATH6KL_STATE_DEEPSLEEP:
944b4b2a0b1SKalle Valo break;
945d7c44e0bSRaja Mani
946d7c44e0bSRaja Mani case ATH6KL_STATE_WOW:
947d7c44e0bSRaja Mani break;
948390a8c8fSRaja Mani
949390a8c8fSRaja Mani case ATH6KL_STATE_SUSPENDING:
950390a8c8fSRaja Mani break;
951390a8c8fSRaja Mani
952390a8c8fSRaja Mani case ATH6KL_STATE_RESUMING:
953390a8c8fSRaja Mani break;
95484caf800SVasanthakumar Thiagarajan
95584caf800SVasanthakumar Thiagarajan case ATH6KL_STATE_RECOVERY:
95684caf800SVasanthakumar Thiagarajan break;
957b4b2a0b1SKalle Valo }
958b4b2a0b1SKalle Valo
95952d81a68SKalle Valo ath6kl_cfg80211_resume(ar);
960aa6cffc1SChilam Ng
961aa6cffc1SChilam Ng return 0;
962aa6cffc1SChilam Ng }
963aa6cffc1SChilam Ng
964c7111495SKalle Valo /* set the window address register (using 4-byte register access ). */
ath6kl_set_addrwin_reg(struct ath6kl * ar,u32 reg_addr,u32 addr)965c7111495SKalle Valo static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
966c7111495SKalle Valo {
967c7111495SKalle Valo int status;
968c7111495SKalle Valo u8 addr_val[4];
969c7111495SKalle Valo s32 i;
970c7111495SKalle Valo
971c7111495SKalle Valo /*
972c7111495SKalle Valo * Write bytes 1,2,3 of the register to set the upper address bytes,
973c7111495SKalle Valo * the LSB is written last to initiate the access cycle
974c7111495SKalle Valo */
975c7111495SKalle Valo
976c7111495SKalle Valo for (i = 1; i <= 3; i++) {
977c7111495SKalle Valo /*
978c7111495SKalle Valo * Fill the buffer with the address byte value we want to
979c7111495SKalle Valo * hit 4 times.
980c7111495SKalle Valo */
981c7111495SKalle Valo memset(addr_val, ((u8 *)&addr)[i], 4);
982c7111495SKalle Valo
983c7111495SKalle Valo /*
984c7111495SKalle Valo * Hit each byte of the register address with a 4-byte
985c7111495SKalle Valo * write operation to the same address, this is a harmless
986c7111495SKalle Valo * operation.
987c7111495SKalle Valo */
988c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
989c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_FIX);
990c7111495SKalle Valo if (status)
991c7111495SKalle Valo break;
992c7111495SKalle Valo }
993c7111495SKalle Valo
994c7111495SKalle Valo if (status) {
995cdeb8602SKalle Valo ath6kl_err("%s: failed to write initial bytes of 0x%x to window reg: 0x%X\n",
996cdeb8602SKalle Valo __func__, addr, reg_addr);
997c7111495SKalle Valo return status;
998c7111495SKalle Valo }
999c7111495SKalle Valo
1000c7111495SKalle Valo /*
1001c7111495SKalle Valo * Write the address register again, this time write the whole
1002c7111495SKalle Valo * 4-byte value. The effect here is that the LSB write causes the
1003c7111495SKalle Valo * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
1004c7111495SKalle Valo * effect since we are writing the same values again
1005c7111495SKalle Valo */
1006c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
1007c7111495SKalle Valo 4, HIF_WR_SYNC_BYTE_INC);
1008c7111495SKalle Valo
1009c7111495SKalle Valo if (status) {
1010c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
1011c7111495SKalle Valo __func__, addr, reg_addr);
1012c7111495SKalle Valo return status;
1013c7111495SKalle Valo }
1014c7111495SKalle Valo
1015c7111495SKalle Valo return 0;
1016c7111495SKalle Valo }
1017c7111495SKalle Valo
ath6kl_sdio_diag_read32(struct ath6kl * ar,u32 address,u32 * data)1018c7111495SKalle Valo static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
1019c7111495SKalle Valo {
1020c7111495SKalle Valo int status;
1021c7111495SKalle Valo
1022c7111495SKalle Valo /* set window register to start read cycle */
1023c7111495SKalle Valo status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
1024c7111495SKalle Valo address);
1025c7111495SKalle Valo
1026c7111495SKalle Valo if (status)
1027c7111495SKalle Valo return status;
1028c7111495SKalle Valo
1029c7111495SKalle Valo /* read the data */
1030c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1031c7111495SKalle Valo (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
1032c7111495SKalle Valo if (status) {
1033c7111495SKalle Valo ath6kl_err("%s: failed to read from window data addr\n",
1034c7111495SKalle Valo __func__);
1035c7111495SKalle Valo return status;
1036c7111495SKalle Valo }
1037c7111495SKalle Valo
1038c7111495SKalle Valo return status;
1039c7111495SKalle Valo }
1040c7111495SKalle Valo
ath6kl_sdio_diag_write32(struct ath6kl * ar,u32 address,__le32 data)1041c7111495SKalle Valo static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
1042c7111495SKalle Valo __le32 data)
1043c7111495SKalle Valo {
1044c7111495SKalle Valo int status;
1045c7111495SKalle Valo u32 val = (__force u32) data;
1046c7111495SKalle Valo
1047c7111495SKalle Valo /* set write data */
1048c7111495SKalle Valo status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1049c7111495SKalle Valo (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
1050c7111495SKalle Valo if (status) {
1051c7111495SKalle Valo ath6kl_err("%s: failed to write 0x%x to window data addr\n",
1052c7111495SKalle Valo __func__, data);
1053c7111495SKalle Valo return status;
1054c7111495SKalle Valo }
1055c7111495SKalle Valo
1056c7111495SKalle Valo /* set window register, which starts the write cycle */
1057c7111495SKalle Valo return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
1058c7111495SKalle Valo address);
1059c7111495SKalle Valo }
1060c7111495SKalle Valo
ath6kl_sdio_bmi_credits(struct ath6kl * ar)106166b693c3SKalle Valo static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
106266b693c3SKalle Valo {
106366b693c3SKalle Valo u32 addr;
106466b693c3SKalle Valo unsigned long timeout;
106566b693c3SKalle Valo int ret;
106666b693c3SKalle Valo
106766b693c3SKalle Valo ar->bmi.cmd_credits = 0;
106866b693c3SKalle Valo
106966b693c3SKalle Valo /* Read the counter register to get the command credits */
107066b693c3SKalle Valo addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
107166b693c3SKalle Valo
107266b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
107366b693c3SKalle Valo while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
107466b693c3SKalle Valo /*
107566b693c3SKalle Valo * Hit the credit counter with a 4-byte access, the first byte
107666b693c3SKalle Valo * read will hit the counter and cause a decrement, while the
107766b693c3SKalle Valo * remaining 3 bytes has no effect. The rationale behind this
107866b693c3SKalle Valo * is to make all HIF accesses 4-byte aligned.
107966b693c3SKalle Valo */
108066b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr,
108166b693c3SKalle Valo (u8 *)&ar->bmi.cmd_credits, 4,
108266b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC);
108366b693c3SKalle Valo if (ret) {
1084cdeb8602SKalle Valo ath6kl_err("Unable to decrement the command credit count register: %d\n",
1085cdeb8602SKalle Valo ret);
108666b693c3SKalle Valo return ret;
108766b693c3SKalle Valo }
108866b693c3SKalle Valo
108966b693c3SKalle Valo /* The counter is only 8 bits.
109066b693c3SKalle Valo * Ignore anything in the upper 3 bytes
109166b693c3SKalle Valo */
109266b693c3SKalle Valo ar->bmi.cmd_credits &= 0xFF;
109366b693c3SKalle Valo }
109466b693c3SKalle Valo
109566b693c3SKalle Valo if (!ar->bmi.cmd_credits) {
109666b693c3SKalle Valo ath6kl_err("bmi communication timeout\n");
109766b693c3SKalle Valo return -ETIMEDOUT;
109866b693c3SKalle Valo }
109966b693c3SKalle Valo
110066b693c3SKalle Valo return 0;
110166b693c3SKalle Valo }
110266b693c3SKalle Valo
ath6kl_bmi_get_rx_lkahd(struct ath6kl * ar)110366b693c3SKalle Valo static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
110466b693c3SKalle Valo {
110566b693c3SKalle Valo unsigned long timeout;
110666b693c3SKalle Valo u32 rx_word = 0;
110766b693c3SKalle Valo int ret = 0;
110866b693c3SKalle Valo
110966b693c3SKalle Valo timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
111066b693c3SKalle Valo while ((time_before(jiffies, timeout)) && !rx_word) {
111166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar,
111266b693c3SKalle Valo RX_LOOKAHEAD_VALID_ADDRESS,
111366b693c3SKalle Valo (u8 *)&rx_word, sizeof(rx_word),
111466b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC);
111566b693c3SKalle Valo if (ret) {
111666b693c3SKalle Valo ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
111766b693c3SKalle Valo return ret;
111866b693c3SKalle Valo }
111966b693c3SKalle Valo
112066b693c3SKalle Valo /* all we really want is one bit */
112166b693c3SKalle Valo rx_word &= (1 << ENDPOINT1);
112266b693c3SKalle Valo }
112366b693c3SKalle Valo
112466b693c3SKalle Valo if (!rx_word) {
112566b693c3SKalle Valo ath6kl_err("bmi_recv_buf FIFO empty\n");
112666b693c3SKalle Valo return -EINVAL;
112766b693c3SKalle Valo }
112866b693c3SKalle Valo
112966b693c3SKalle Valo return ret;
113066b693c3SKalle Valo }
113166b693c3SKalle Valo
ath6kl_sdio_bmi_write(struct ath6kl * ar,u8 * buf,u32 len)113266b693c3SKalle Valo static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
113366b693c3SKalle Valo {
113466b693c3SKalle Valo int ret;
113566b693c3SKalle Valo u32 addr;
113666b693c3SKalle Valo
113766b693c3SKalle Valo ret = ath6kl_sdio_bmi_credits(ar);
113866b693c3SKalle Valo if (ret)
113966b693c3SKalle Valo return ret;
114066b693c3SKalle Valo
114166b693c3SKalle Valo addr = ar->mbox_info.htc_addr;
114266b693c3SKalle Valo
114366b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
114466b693c3SKalle Valo HIF_WR_SYNC_BYTE_INC);
1145bf978145SMohammed Shafi Shajakhan if (ret) {
114666b693c3SKalle Valo ath6kl_err("unable to send the bmi data to the device\n");
114766b693c3SKalle Valo return ret;
114866b693c3SKalle Valo }
114966b693c3SKalle Valo
1150bf978145SMohammed Shafi Shajakhan return 0;
1151bf978145SMohammed Shafi Shajakhan }
1152bf978145SMohammed Shafi Shajakhan
ath6kl_sdio_bmi_read(struct ath6kl * ar,u8 * buf,u32 len)115366b693c3SKalle Valo static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
115466b693c3SKalle Valo {
115566b693c3SKalle Valo int ret;
115666b693c3SKalle Valo u32 addr;
115766b693c3SKalle Valo
115866b693c3SKalle Valo /*
115966b693c3SKalle Valo * During normal bootup, small reads may be required.
116066b693c3SKalle Valo * Rather than issue an HIF Read and then wait as the Target
116166b693c3SKalle Valo * adds successive bytes to the FIFO, we wait here until
116266b693c3SKalle Valo * we know that response data is available.
116366b693c3SKalle Valo *
116466b693c3SKalle Valo * This allows us to cleanly timeout on an unexpected
116566b693c3SKalle Valo * Target failure rather than risk problems at the HIF level.
116666b693c3SKalle Valo * In particular, this avoids SDIO timeouts and possibly garbage
116766b693c3SKalle Valo * data on some host controllers. And on an interconnect
116866b693c3SKalle Valo * such as Compact Flash (as well as some SDIO masters) which
116966b693c3SKalle Valo * does not provide any indication on data timeout, it avoids
117066b693c3SKalle Valo * a potential hang or garbage response.
117166b693c3SKalle Valo *
117266b693c3SKalle Valo * Synchronization is more difficult for reads larger than the
117366b693c3SKalle Valo * size of the MBOX FIFO (128B), because the Target is unable
117466b693c3SKalle Valo * to push the 129th byte of data until AFTER the Host posts an
117566b693c3SKalle Valo * HIF Read and removes some FIFO data. So for large reads the
117666b693c3SKalle Valo * Host proceeds to post an HIF Read BEFORE all the data is
117766b693c3SKalle Valo * actually available to read. Fortunately, large BMI reads do
117866b693c3SKalle Valo * not occur in practice -- they're supported for debug/development.
117966b693c3SKalle Valo *
118066b693c3SKalle Valo * So Host/Target BMI synchronization is divided into these cases:
118166b693c3SKalle Valo * CASE 1: length < 4
118266b693c3SKalle Valo * Should not happen
118366b693c3SKalle Valo *
118466b693c3SKalle Valo * CASE 2: 4 <= length <= 128
118566b693c3SKalle Valo * Wait for first 4 bytes to be in FIFO
118666b693c3SKalle Valo * If CONSERVATIVE_BMI_READ is enabled, also wait for
118766b693c3SKalle Valo * a BMI command credit, which indicates that the ENTIRE
1188*6456741fSJilin Yuan * response is available in the FIFO
118966b693c3SKalle Valo *
119066b693c3SKalle Valo * CASE 3: length > 128
119166b693c3SKalle Valo * Wait for the first 4 bytes to be in FIFO
119266b693c3SKalle Valo *
119366b693c3SKalle Valo * For most uses, a small timeout should be sufficient and we will
119466b693c3SKalle Valo * usually see a response quickly; but there may be some unusual
119566b693c3SKalle Valo * (debug) cases of BMI_EXECUTE where we want an larger timeout.
119666b693c3SKalle Valo * For now, we use an unbounded busy loop while waiting for
119766b693c3SKalle Valo * BMI_EXECUTE.
119866b693c3SKalle Valo *
119966b693c3SKalle Valo * If BMI_EXECUTE ever needs to support longer-latency execution,
120066b693c3SKalle Valo * especially in production, this code needs to be enhanced to sleep
120166b693c3SKalle Valo * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
120266b693c3SKalle Valo * a function of Host processor speed.
120366b693c3SKalle Valo */
120466b693c3SKalle Valo if (len >= 4) { /* NB: Currently, always true */
120566b693c3SKalle Valo ret = ath6kl_bmi_get_rx_lkahd(ar);
120666b693c3SKalle Valo if (ret)
120766b693c3SKalle Valo return ret;
120866b693c3SKalle Valo }
120966b693c3SKalle Valo
121066b693c3SKalle Valo addr = ar->mbox_info.htc_addr;
121166b693c3SKalle Valo ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
121266b693c3SKalle Valo HIF_RD_SYNC_BYTE_INC);
121366b693c3SKalle Valo if (ret) {
121466b693c3SKalle Valo ath6kl_err("Unable to read the bmi data from the device: %d\n",
121566b693c3SKalle Valo ret);
121666b693c3SKalle Valo return ret;
121766b693c3SKalle Valo }
121866b693c3SKalle Valo
121966b693c3SKalle Valo return 0;
122066b693c3SKalle Valo }
122166b693c3SKalle Valo
ath6kl_sdio_stop(struct ath6kl * ar)122232a07e44SKalle Valo static void ath6kl_sdio_stop(struct ath6kl *ar)
122332a07e44SKalle Valo {
122432a07e44SKalle Valo struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
122532a07e44SKalle Valo struct bus_request *req, *tmp_req;
122632a07e44SKalle Valo void *context;
122732a07e44SKalle Valo
122832a07e44SKalle Valo /* FIXME: make sure that wq is not queued again */
122932a07e44SKalle Valo
123032a07e44SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work);
123132a07e44SKalle Valo
123232a07e44SKalle Valo spin_lock_bh(&ar_sdio->wr_async_lock);
123332a07e44SKalle Valo
123432a07e44SKalle Valo list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
123532a07e44SKalle Valo list_del(&req->list);
123632a07e44SKalle Valo
123732a07e44SKalle Valo if (req->scat_req) {
123832a07e44SKalle Valo /* this is a scatter gather request */
123932a07e44SKalle Valo req->scat_req->status = -ECANCELED;
124032a07e44SKalle Valo req->scat_req->complete(ar_sdio->ar->htc_target,
124132a07e44SKalle Valo req->scat_req);
124232a07e44SKalle Valo } else {
124332a07e44SKalle Valo context = req->packet;
124432a07e44SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, req);
124532a07e44SKalle Valo ath6kl_hif_rw_comp_handler(context, -ECANCELED);
124632a07e44SKalle Valo }
124732a07e44SKalle Valo }
124832a07e44SKalle Valo
124932a07e44SKalle Valo spin_unlock_bh(&ar_sdio->wr_async_lock);
125032a07e44SKalle Valo
125132a07e44SKalle Valo WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
125232a07e44SKalle Valo }
125332a07e44SKalle Valo
1254bdcd8170SKalle Valo static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1255bdcd8170SKalle Valo .read_write_sync = ath6kl_sdio_read_write_sync,
1256bdcd8170SKalle Valo .write_async = ath6kl_sdio_write_async,
1257bdcd8170SKalle Valo .irq_enable = ath6kl_sdio_irq_enable,
1258bdcd8170SKalle Valo .irq_disable = ath6kl_sdio_irq_disable,
1259bdcd8170SKalle Valo .scatter_req_get = ath6kl_sdio_scatter_req_get,
1260bdcd8170SKalle Valo .scatter_req_add = ath6kl_sdio_scatter_req_add,
1261bdcd8170SKalle Valo .enable_scatter = ath6kl_sdio_enable_scatter,
1262f74a7361SVasanthakumar Thiagarajan .scat_req_rw = ath6kl_sdio_async_rw_scatter,
1263bdcd8170SKalle Valo .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
1264abcb344bSKalle Valo .suspend = ath6kl_sdio_suspend,
1265aa6cffc1SChilam Ng .resume = ath6kl_sdio_resume,
1266c7111495SKalle Valo .diag_read32 = ath6kl_sdio_diag_read32,
1267c7111495SKalle Valo .diag_write32 = ath6kl_sdio_diag_write32,
126866b693c3SKalle Valo .bmi_read = ath6kl_sdio_bmi_read,
126966b693c3SKalle Valo .bmi_write = ath6kl_sdio_bmi_write,
1270b2e75698SKalle Valo .power_on = ath6kl_sdio_power_on,
1271b2e75698SKalle Valo .power_off = ath6kl_sdio_power_off,
127232a07e44SKalle Valo .stop = ath6kl_sdio_stop,
1273bdcd8170SKalle Valo };
1274bdcd8170SKalle Valo
1275b4b2a0b1SKalle Valo #ifdef CONFIG_PM_SLEEP
1276b4b2a0b1SKalle Valo
1277b4b2a0b1SKalle Valo /*
1278b4b2a0b1SKalle Valo * Empty handlers so that mmc subsystem doesn't remove us entirely during
1279b4b2a0b1SKalle Valo * suspend. We instead follow cfg80211 suspend/resume handlers.
1280b4b2a0b1SKalle Valo */
ath6kl_sdio_pm_suspend(struct device * device)1281b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_suspend(struct device *device)
1282b4b2a0b1SKalle Valo {
1283b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1284b4b2a0b1SKalle Valo
1285b4b2a0b1SKalle Valo return 0;
1286b4b2a0b1SKalle Valo }
1287b4b2a0b1SKalle Valo
ath6kl_sdio_pm_resume(struct device * device)1288b4b2a0b1SKalle Valo static int ath6kl_sdio_pm_resume(struct device *device)
1289b4b2a0b1SKalle Valo {
1290b4b2a0b1SKalle Valo ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1291b4b2a0b1SKalle Valo
1292b4b2a0b1SKalle Valo return 0;
1293b4b2a0b1SKalle Valo }
1294b4b2a0b1SKalle Valo
1295b4b2a0b1SKalle Valo static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1296b4b2a0b1SKalle Valo ath6kl_sdio_pm_resume);
1297b4b2a0b1SKalle Valo
1298b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1299b4b2a0b1SKalle Valo
1300b4b2a0b1SKalle Valo #else
1301b4b2a0b1SKalle Valo
1302b4b2a0b1SKalle Valo #define ATH6KL_SDIO_PM_OPS NULL
1303b4b2a0b1SKalle Valo
1304b4b2a0b1SKalle Valo #endif /* CONFIG_PM_SLEEP */
1305b4b2a0b1SKalle Valo
ath6kl_sdio_probe(struct sdio_func * func,const struct sdio_device_id * id)1306bdcd8170SKalle Valo static int ath6kl_sdio_probe(struct sdio_func *func,
1307bdcd8170SKalle Valo const struct sdio_device_id *id)
1308bdcd8170SKalle Valo {
1309bdcd8170SKalle Valo int ret;
1310bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio;
1311bdcd8170SKalle Valo struct ath6kl *ar;
1312bdcd8170SKalle Valo int count;
1313bdcd8170SKalle Valo
13143ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
13153ef987beSKalle Valo "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1316f7325b85SKalle Valo func->num, func->vendor, func->device,
1317f7325b85SKalle Valo func->max_blksize, func->cur_blksize);
1318bdcd8170SKalle Valo
1319bdcd8170SKalle Valo ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1320bdcd8170SKalle Valo if (!ar_sdio)
1321bdcd8170SKalle Valo return -ENOMEM;
1322bdcd8170SKalle Valo
1323bdcd8170SKalle Valo ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1324bdcd8170SKalle Valo if (!ar_sdio->dma_buffer) {
1325bdcd8170SKalle Valo ret = -ENOMEM;
1326bdcd8170SKalle Valo goto err_hif;
1327bdcd8170SKalle Valo }
1328bdcd8170SKalle Valo
1329bdcd8170SKalle Valo ar_sdio->func = func;
1330bdcd8170SKalle Valo sdio_set_drvdata(func, ar_sdio);
1331bdcd8170SKalle Valo
1332bdcd8170SKalle Valo ar_sdio->id = id;
1333bdcd8170SKalle Valo ar_sdio->is_disabled = true;
1334bdcd8170SKalle Valo
1335bdcd8170SKalle Valo spin_lock_init(&ar_sdio->lock);
1336bdcd8170SKalle Valo spin_lock_init(&ar_sdio->scat_lock);
1337bdcd8170SKalle Valo spin_lock_init(&ar_sdio->wr_async_lock);
1338fdb28589SRaja Mani mutex_init(&ar_sdio->dma_buffer_mutex);
1339bdcd8170SKalle Valo
1340bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->scat_req);
1341bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1342bdcd8170SKalle Valo INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1343bdcd8170SKalle Valo
1344bdcd8170SKalle Valo INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1345bdcd8170SKalle Valo
1346d1f41597SRaja Mani init_waitqueue_head(&ar_sdio->irq_wq);
1347d1f41597SRaja Mani
1348bdcd8170SKalle Valo for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1349bdcd8170SKalle Valo ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1350bdcd8170SKalle Valo
135145eaa78fSKalle Valo ar = ath6kl_core_create(&ar_sdio->func->dev);
1352bdcd8170SKalle Valo if (!ar) {
1353bdcd8170SKalle Valo ath6kl_err("Failed to alloc ath6kl core\n");
1354bdcd8170SKalle Valo ret = -ENOMEM;
1355bdcd8170SKalle Valo goto err_dma;
1356bdcd8170SKalle Valo }
1357bdcd8170SKalle Valo
1358bdcd8170SKalle Valo ar_sdio->ar = ar;
135977eab1e9SKalle Valo ar->hif_type = ATH6KL_HIF_TYPE_SDIO;
1360bdcd8170SKalle Valo ar->hif_priv = ar_sdio;
1361bdcd8170SKalle Valo ar->hif_ops = &ath6kl_sdio_ops;
13621f4c894dSKalle Valo ar->bmi.max_data_size = 256;
1363bdcd8170SKalle Valo
1364bdcd8170SKalle Valo ath6kl_sdio_set_mbox_info(ar);
1365bdcd8170SKalle Valo
1366e28e8104SKalle Valo ret = ath6kl_sdio_config(ar);
1367bdcd8170SKalle Valo if (ret) {
1368e28e8104SKalle Valo ath6kl_err("Failed to config sdio: %d\n", ret);
13698dafb70eSVasanthakumar Thiagarajan goto err_core_alloc;
1370bdcd8170SKalle Valo }
1371bdcd8170SKalle Valo
1372e76ac2bfSKalle Valo ret = ath6kl_core_init(ar, ATH6KL_HTC_TYPE_MBOX);
1373bdcd8170SKalle Valo if (ret) {
1374bdcd8170SKalle Valo ath6kl_err("Failed to init ath6kl core\n");
1375e28e8104SKalle Valo goto err_core_alloc;
1376bdcd8170SKalle Valo }
1377bdcd8170SKalle Valo
1378bdcd8170SKalle Valo return ret;
1379bdcd8170SKalle Valo
13808dafb70eSVasanthakumar Thiagarajan err_core_alloc:
138145eaa78fSKalle Valo ath6kl_core_destroy(ar_sdio->ar);
1382bdcd8170SKalle Valo err_dma:
1383bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer);
1384bdcd8170SKalle Valo err_hif:
1385bdcd8170SKalle Valo kfree(ar_sdio);
1386bdcd8170SKalle Valo
1387bdcd8170SKalle Valo return ret;
1388bdcd8170SKalle Valo }
1389bdcd8170SKalle Valo
ath6kl_sdio_remove(struct sdio_func * func)1390bdcd8170SKalle Valo static void ath6kl_sdio_remove(struct sdio_func *func)
1391bdcd8170SKalle Valo {
1392bdcd8170SKalle Valo struct ath6kl_sdio *ar_sdio;
1393bdcd8170SKalle Valo
13943ef987beSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT,
13953ef987beSKalle Valo "sdio removed func %d vendor 0x%x device 0x%x\n",
1396f7325b85SKalle Valo func->num, func->vendor, func->device);
1397f7325b85SKalle Valo
1398bdcd8170SKalle Valo ar_sdio = sdio_get_drvdata(func);
1399bdcd8170SKalle Valo
1400bdcd8170SKalle Valo ath6kl_stop_txrx(ar_sdio->ar);
1401bdcd8170SKalle Valo cancel_work_sync(&ar_sdio->wr_async_work);
1402bdcd8170SKalle Valo
14036db8fa53SVasanthakumar Thiagarajan ath6kl_core_cleanup(ar_sdio->ar);
14040e7de662SVasanthakumar Thiagarajan ath6kl_core_destroy(ar_sdio->ar);
1405bdcd8170SKalle Valo
1406bdcd8170SKalle Valo kfree(ar_sdio->dma_buffer);
1407bdcd8170SKalle Valo kfree(ar_sdio);
1408bdcd8170SKalle Valo }
1409bdcd8170SKalle Valo
1410bdcd8170SKalle Valo static const struct sdio_device_id ath6kl_sdio_devices[] = {
1411ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6003_00)},
1412ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6003_01)},
1413ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6004_00)},
1414ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6004_01)},
1415ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6004_02)},
1416ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6004_18)},
1417ecc2f396SPali Rohár {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6004_19)},
1418bdcd8170SKalle Valo {},
1419bdcd8170SKalle Valo };
1420bdcd8170SKalle Valo
1421bdcd8170SKalle Valo MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1422bdcd8170SKalle Valo
1423bdcd8170SKalle Valo static struct sdio_driver ath6kl_sdio_driver = {
1424241b128bSKalle Valo .name = "ath6kl_sdio",
1425bdcd8170SKalle Valo .id_table = ath6kl_sdio_devices,
1426bdcd8170SKalle Valo .probe = ath6kl_sdio_probe,
1427bdcd8170SKalle Valo .remove = ath6kl_sdio_remove,
1428b4b2a0b1SKalle Valo .drv.pm = ATH6KL_SDIO_PM_OPS,
1429bdcd8170SKalle Valo };
1430bdcd8170SKalle Valo
ath6kl_sdio_init(void)1431bdcd8170SKalle Valo static int __init ath6kl_sdio_init(void)
1432bdcd8170SKalle Valo {
1433bdcd8170SKalle Valo int ret;
1434bdcd8170SKalle Valo
1435bdcd8170SKalle Valo ret = sdio_register_driver(&ath6kl_sdio_driver);
1436bdcd8170SKalle Valo if (ret)
1437bdcd8170SKalle Valo ath6kl_err("sdio driver registration failed: %d\n", ret);
1438bdcd8170SKalle Valo
1439bdcd8170SKalle Valo return ret;
1440bdcd8170SKalle Valo }
1441bdcd8170SKalle Valo
ath6kl_sdio_exit(void)1442bdcd8170SKalle Valo static void __exit ath6kl_sdio_exit(void)
1443bdcd8170SKalle Valo {
1444bdcd8170SKalle Valo sdio_unregister_driver(&ath6kl_sdio_driver);
1445bdcd8170SKalle Valo }
1446bdcd8170SKalle Valo
1447bdcd8170SKalle Valo module_init(ath6kl_sdio_init);
1448bdcd8170SKalle Valo module_exit(ath6kl_sdio_exit);
1449bdcd8170SKalle Valo
1450bdcd8170SKalle Valo MODULE_AUTHOR("Atheros Communications, Inc.");
1451bdcd8170SKalle Valo MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1452bdcd8170SKalle Valo MODULE_LICENSE("Dual BSD/GPL");
1453bdcd8170SKalle Valo
1454c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE);
1455c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE);
1456c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE);
14570d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE);
14580d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE);
1459c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE);
1460c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE);
1461c0038972SKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE);
14620d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE);
14630d0192baSKalle Valo MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE);
1464c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE);
1465f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE);
1466f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE);
1467c0038972SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE);
1468f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE);
1469f0ea5d58SKalle Valo MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE);
14706146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_FW_DIR "/" AR6004_HW_1_2_FIRMWARE_FILE);
14716146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_BOARD_DATA_FILE);
14726146ca69SRay Chen MODULE_FIRMWARE(AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE);
1473bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_FW_DIR "/" AR6004_HW_1_3_FIRMWARE_FILE);
1474bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_BOARD_DATA_FILE);
1475bf744f11SBala Shanmugam MODULE_FIRMWARE(AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE);
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